driver core: Suppress sysfs warnings for device_rename().
[deliverable/linux.git] / arch / s390 / kernel / time.c
CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
1da177e4
LT
15#include <linux/errno.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <linux/mm.h>
22#include <linux/interrupt.h>
23#include <linux/time.h>
3367b994 24#include <linux/sysdev.h>
1da177e4
LT
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/smp.h>
28#include <linux/types.h>
29#include <linux/profile.h>
30#include <linux/timex.h>
31#include <linux/notifier.h>
dc64bef5 32#include <linux/clocksource.h>
5a62b192 33#include <linux/clockchips.h>
d2fec595 34#include <linux/bootmem.h>
1da177e4
LT
35#include <asm/uaccess.h>
36#include <asm/delay.h>
37#include <asm/s390_ext.h>
38#include <asm/div64.h>
39#include <asm/irq.h>
5a489b98 40#include <asm/irq_regs.h>
1da177e4 41#include <asm/timer.h>
d54853ef 42#include <asm/etr.h>
a806170e 43#include <asm/cio.h>
1da177e4
LT
44
45/* change this if you have some constant time drift */
46#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
47#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
48
d54853ef
MS
49/* The value of the TOD clock for 1.1.1970. */
50#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
51
1da177e4
LT
52/*
53 * Create a small time difference between the timer interrupts
54 * on the different cpus to avoid lock contention.
55 */
56#define CPU_DEVIATION (smp_processor_id() << 12)
57
58#define TICK_SIZE tick
59
1da177e4 60static ext_int_info_t ext_int_info_cc;
d54853ef 61static ext_int_info_t ext_int_etr_cc;
1da177e4 62static u64 jiffies_timer_cc;
5a62b192
HC
63
64static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 65
1da177e4
LT
66/*
67 * Scheduler clock - returns current time in nanosec units.
68 */
69unsigned long long sched_clock(void)
70{
c0015f91 71 return ((get_clock_xt() - jiffies_timer_cc) * 125) >> 9;
1da177e4
LT
72}
73
32f65f27
JG
74/*
75 * Monotonic_clock - returns # of nanoseconds passed since time_init()
76 */
77unsigned long long monotonic_clock(void)
78{
79 return sched_clock();
80}
81EXPORT_SYMBOL(monotonic_clock);
82
1da177e4
LT
83void tod_to_timeval(__u64 todval, struct timespec *xtime)
84{
85 unsigned long long sec;
86
87 sec = todval >> 12;
88 do_div(sec, 1000000);
89 xtime->tv_sec = sec;
90 todval -= (sec * 1000000) << 12;
91 xtime->tv_nsec = ((todval * 1000) >> 12);
92}
93
1da177e4 94#ifdef CONFIG_PROFILING
5a489b98 95#define s390_do_profile() profile_tick(CPU_PROFILING)
1da177e4 96#else
5a489b98 97#define s390_do_profile() do { ; } while(0)
1da177e4
LT
98#endif /* CONFIG_PROFILING */
99
5a62b192 100void clock_comparator_work(void)
1da177e4 101{
5a62b192 102 struct clock_event_device *cd;
1da177e4 103
5a62b192
HC
104 S390_lowcore.clock_comparator = -1ULL;
105 set_clock_comparator(S390_lowcore.clock_comparator);
106 cd = &__get_cpu_var(comparators);
107 cd->event_handler(cd);
5a489b98 108 s390_do_profile();
1da177e4
LT
109}
110
1da177e4 111/*
5a62b192 112 * Fixup the clock comparator.
1da177e4 113 */
5a62b192 114static void fixup_clock_comparator(unsigned long long delta)
1da177e4 115{
5a62b192
HC
116 /* If nobody is waiting there's nothing to fix. */
117 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 118 return;
5a62b192
HC
119 S390_lowcore.clock_comparator += delta;
120 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
121}
122
5a62b192
HC
123static int s390_next_event(unsigned long delta,
124 struct clock_event_device *evt)
1da177e4 125{
5a62b192
HC
126 S390_lowcore.clock_comparator = get_clock() + delta;
127 set_clock_comparator(S390_lowcore.clock_comparator);
128 return 0;
1da177e4
LT
129}
130
5a62b192
HC
131static void s390_set_mode(enum clock_event_mode mode,
132 struct clock_event_device *evt)
1da177e4 133{
d54853ef
MS
134}
135
136/*
137 * Set up lowcore and control register of the current cpu to
138 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
139 */
140void init_cpu_timer(void)
141{
5a62b192
HC
142 struct clock_event_device *cd;
143 int cpu;
144
145 S390_lowcore.clock_comparator = -1ULL;
146 set_clock_comparator(S390_lowcore.clock_comparator);
147
148 cpu = smp_processor_id();
149 cd = &per_cpu(comparators, cpu);
150 cd->name = "comparator";
151 cd->features = CLOCK_EVT_FEAT_ONESHOT;
152 cd->mult = 16777;
153 cd->shift = 12;
154 cd->min_delta_ns = 1;
155 cd->max_delta_ns = LONG_MAX;
156 cd->rating = 400;
157 cd->cpumask = cpumask_of_cpu(cpu);
158 cd->set_next_event = s390_next_event;
159 cd->set_mode = s390_set_mode;
160
161 clockevents_register_device(cd);
d54853ef
MS
162
163 /* Enable clock comparator timer interrupt. */
164 __ctl_set_bit(0,11);
165
d2fec595 166 /* Always allow the timing alert external interrupt. */
d54853ef
MS
167 __ctl_set_bit(0, 4);
168}
169
170static void clock_comparator_interrupt(__u16 code)
171{
d54853ef
MS
172}
173
d2fec595
MS
174static void etr_timing_alert(struct etr_irq_parm *);
175static void stp_timing_alert(struct stp_irq_parm *);
176
177static void timing_alert_interrupt(__u16 code)
178{
179 if (S390_lowcore.ext_params & 0x00c40000)
180 etr_timing_alert((struct etr_irq_parm *)
181 &S390_lowcore.ext_params);
182 if (S390_lowcore.ext_params & 0x00038000)
183 stp_timing_alert((struct stp_irq_parm *)
184 &S390_lowcore.ext_params);
185}
186
d54853ef 187static void etr_reset(void);
d2fec595 188static void stp_reset(void);
d54853ef
MS
189
190/*
191 * Get the TOD clock running.
192 */
193static u64 __init reset_tod_clock(void)
194{
195 u64 time;
196
197 etr_reset();
d2fec595 198 stp_reset();
d54853ef
MS
199 if (store_clock(&time) == 0)
200 return time;
201 /* TOD clock not running. Set the clock to Unix Epoch. */
202 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
203 panic("TOD clock not operational.");
1da177e4 204
d54853ef 205 return TOD_UNIX_EPOCH;
1da177e4
LT
206}
207
dc64bef5
MS
208static cycle_t read_tod_clock(void)
209{
210 return get_clock();
211}
212
213static struct clocksource clocksource_tod = {
214 .name = "tod",
d2cb0e6e 215 .rating = 400,
dc64bef5
MS
216 .read = read_tod_clock,
217 .mask = -1ULL,
218 .mult = 1000,
219 .shift = 12,
cc02d809 220 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
221};
222
223
1da177e4
LT
224/*
225 * Initialize the TOD clock and the CPU timer of
226 * the boot cpu.
227 */
228void __init time_init(void)
229{
5a62b192
HC
230 u64 init_timer_cc;
231
d54853ef 232 init_timer_cc = reset_tod_clock();
1da177e4
LT
233 jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY;
234
235 /* set xtime */
d54853ef 236 tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime);
1da177e4
LT
237 set_normalized_timespec(&wall_to_monotonic,
238 -xtime.tv_sec, -xtime.tv_nsec);
239
240 /* request the clock comparator external interrupt */
d54853ef
MS
241 if (register_early_external_interrupt(0x1004,
242 clock_comparator_interrupt,
1da177e4
LT
243 &ext_int_info_cc) != 0)
244 panic("Couldn't request external interrupt 0x1004");
245
dc64bef5
MS
246 if (clocksource_register(&clocksource_tod) != 0)
247 panic("Could not register TOD clock source");
248
d2fec595
MS
249 /* request the timing alert external interrupt */
250 if (register_early_external_interrupt(0x1406,
251 timing_alert_interrupt,
d54853ef
MS
252 &ext_int_etr_cc) != 0)
253 panic("Couldn't request external interrupt 0x1406");
254
255 /* Enable TOD clock interrupts on the boot cpu. */
256 init_cpu_timer();
1da177e4 257
1da177e4
LT
258#ifdef CONFIG_VIRT_TIMER
259 vtime_init();
260#endif
d54853ef
MS
261}
262
d2fec595
MS
263/*
264 * The time is "clock". old is what we think the time is.
265 * Adjust the value by a multiple of jiffies and add the delta to ntp.
266 * "delay" is an approximation how long the synchronization took. If
267 * the time correction is positive, then "delay" is subtracted from
268 * the time difference and only the remaining part is passed to ntp.
269 */
270static unsigned long long adjust_time(unsigned long long old,
271 unsigned long long clock,
272 unsigned long long delay)
273{
274 unsigned long long delta, ticks;
275 struct timex adjust;
276
277 if (clock > old) {
278 /* It is later than we thought. */
279 delta = ticks = clock - old;
280 delta = ticks = (delta < delay) ? 0 : delta - delay;
281 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
282 adjust.offset = ticks * (1000000 / HZ);
283 } else {
284 /* It is earlier than we thought. */
285 delta = ticks = old - clock;
286 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
287 delta = -delta;
288 adjust.offset = -ticks * (1000000 / HZ);
289 }
290 jiffies_timer_cc += delta;
291 if (adjust.offset != 0) {
292 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
293 adjust.offset);
294 adjust.modes = ADJ_OFFSET_SINGLESHOT;
295 do_adjtimex(&adjust);
296 }
297 return delta;
298}
299
300static DEFINE_PER_CPU(atomic_t, clock_sync_word);
301static unsigned long clock_sync_flags;
302
303#define CLOCK_SYNC_HAS_ETR 0
304#define CLOCK_SYNC_HAS_STP 1
305#define CLOCK_SYNC_ETR 2
306#define CLOCK_SYNC_STP 3
307
308/*
309 * The synchronous get_clock function. It will write the current clock
310 * value to the clock pointer and return 0 if the clock is in sync with
311 * the external time source. If the clock mode is local it will return
312 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
313 * reference.
314 */
315int get_sync_clock(unsigned long long *clock)
316{
317 atomic_t *sw_ptr;
318 unsigned int sw0, sw1;
319
320 sw_ptr = &get_cpu_var(clock_sync_word);
321 sw0 = atomic_read(sw_ptr);
322 *clock = get_clock();
323 sw1 = atomic_read(sw_ptr);
324 put_cpu_var(clock_sync_sync);
325 if (sw0 == sw1 && (sw0 & 0x80000000U))
326 /* Success: time is in sync. */
327 return 0;
328 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
329 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
330 return -ENOSYS;
331 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
332 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
333 return -EACCES;
334 return -EAGAIN;
335}
336EXPORT_SYMBOL(get_sync_clock);
337
338/*
339 * Make get_sync_clock return -EAGAIN.
340 */
341static void disable_sync_clock(void *dummy)
342{
343 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
344 /*
345 * Clear the in-sync bit 2^31. All get_sync_clock calls will
346 * fail until the sync bit is turned back on. In addition
347 * increase the "sequence" counter to avoid the race of an
348 * etr event and the complete recovery against get_sync_clock.
349 */
350 atomic_clear_mask(0x80000000, sw_ptr);
351 atomic_inc(sw_ptr);
352}
353
354/*
355 * Make get_sync_clock return 0 again.
356 * Needs to be called from a context disabled for preemption.
357 */
358static void enable_sync_clock(void)
359{
360 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
361 atomic_set_mask(0x80000000, sw_ptr);
362}
363
d54853ef
MS
364/*
365 * External Time Reference (ETR) code.
366 */
367static int etr_port0_online;
368static int etr_port1_online;
d2fec595 369static int etr_steai_available;
d54853ef
MS
370
371static int __init early_parse_etr(char *p)
372{
373 if (strncmp(p, "off", 3) == 0)
374 etr_port0_online = etr_port1_online = 0;
375 else if (strncmp(p, "port0", 5) == 0)
376 etr_port0_online = 1;
377 else if (strncmp(p, "port1", 5) == 0)
378 etr_port1_online = 1;
379 else if (strncmp(p, "on", 2) == 0)
380 etr_port0_online = etr_port1_online = 1;
381 return 0;
382}
383early_param("etr", early_parse_etr);
384
385enum etr_event {
386 ETR_EVENT_PORT0_CHANGE,
387 ETR_EVENT_PORT1_CHANGE,
388 ETR_EVENT_PORT_ALERT,
389 ETR_EVENT_SYNC_CHECK,
390 ETR_EVENT_SWITCH_LOCAL,
391 ETR_EVENT_UPDATE,
392};
393
d54853ef
MS
394/*
395 * Valid bit combinations of the eacr register are (x = don't care):
396 * e0 e1 dp p0 p1 ea es sl
397 * 0 0 x 0 0 0 0 0 initial, disabled state
398 * 0 0 x 0 1 1 0 0 port 1 online
399 * 0 0 x 1 0 1 0 0 port 0 online
400 * 0 0 x 1 1 1 0 0 both ports online
401 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
402 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
403 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
404 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
405 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
406 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
407 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
408 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
409 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
410 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
411 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
412 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
413 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
414 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
415 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
416 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
417 */
418static struct etr_eacr etr_eacr;
419static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
420static struct etr_aib etr_port0;
421static int etr_port0_uptodate;
422static struct etr_aib etr_port1;
423static int etr_port1_uptodate;
424static unsigned long etr_events;
425static struct timer_list etr_timer;
d54853ef
MS
426
427static void etr_timeout(unsigned long dummy);
ecdcc023
MS
428static void etr_work_fn(struct work_struct *work);
429static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 430
d54853ef
MS
431/*
432 * Reset ETR attachment.
433 */
434static void etr_reset(void)
435{
436 etr_eacr = (struct etr_eacr) {
437 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
438 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
439 .es = 0, .sl = 0 };
d2fec595 440 if (etr_setr(&etr_eacr) == 0) {
d54853ef 441 etr_tolec = get_clock();
d2fec595
MS
442 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
443 } else if (etr_port0_online || etr_port1_online) {
444 printk(KERN_WARNING "Running on non ETR capable "
445 "machine, only local mode available.\n");
446 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
447 }
448}
449
ecdcc023 450static int __init etr_init(void)
d54853ef
MS
451{
452 struct etr_aib aib;
453
d2fec595 454 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 455 return 0;
d54853ef
MS
456 /* Check if this machine has the steai instruction. */
457 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 458 etr_steai_available = 1;
d54853ef 459 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
460 if (etr_port0_online) {
461 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
ecdcc023 462 schedule_work(&etr_work);
d54853ef
MS
463 }
464 if (etr_port1_online) {
465 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
ecdcc023 466 schedule_work(&etr_work);
d54853ef 467 }
ecdcc023 468 return 0;
d54853ef
MS
469}
470
ecdcc023
MS
471arch_initcall(etr_init);
472
d54853ef
MS
473/*
474 * Two sorts of ETR machine checks. The architecture reads:
475 * "When a machine-check niterruption occurs and if a switch-to-local or
476 * ETR-sync-check interrupt request is pending but disabled, this pending
477 * disabled interruption request is indicated and is cleared".
478 * Which means that we can get etr_switch_to_local events from the machine
479 * check handler although the interruption condition is disabled. Lovely..
480 */
481
482/*
483 * Switch to local machine check. This is called when the last usable
484 * ETR port goes inactive. After switch to local the clock is not in sync.
485 */
486void etr_switch_to_local(void)
487{
488 if (!etr_eacr.sl)
489 return;
d2fec595
MS
490 if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
491 disable_sync_clock(NULL);
d54853ef 492 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
ecdcc023 493 schedule_work(&etr_work);
d54853ef
MS
494}
495
496/*
497 * ETR sync check machine check. This is called when the ETR OTE and the
498 * local clock OTE are farther apart than the ETR sync check tolerance.
499 * After a ETR sync check the clock is not in sync. The machine check
500 * is broadcasted to all cpus at the same time.
501 */
502void etr_sync_check(void)
503{
504 if (!etr_eacr.es)
505 return;
d2fec595
MS
506 if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
507 disable_sync_clock(NULL);
d54853ef 508 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
ecdcc023 509 schedule_work(&etr_work);
d54853ef
MS
510}
511
512/*
d2fec595 513 * ETR timing alert. There are two causes:
d54853ef
MS
514 * 1) port state change, check the usability of the port
515 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
516 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
517 * or ETR-data word 4 (edf4) has changed.
518 */
d2fec595 519static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 520{
d54853ef
MS
521 if (intparm->pc0)
522 /* ETR port 0 state change. */
523 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
524 if (intparm->pc1)
525 /* ETR port 1 state change. */
526 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
527 if (intparm->eai)
528 /*
529 * ETR port alert on either port 0, 1 or both.
530 * Both ports are not up-to-date now.
531 */
532 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
ecdcc023 533 schedule_work(&etr_work);
d54853ef
MS
534}
535
536static void etr_timeout(unsigned long dummy)
537{
538 set_bit(ETR_EVENT_UPDATE, &etr_events);
ecdcc023 539 schedule_work(&etr_work);
d54853ef
MS
540}
541
542/*
543 * Check if the etr mode is pss.
544 */
545static inline int etr_mode_is_pps(struct etr_eacr eacr)
546{
547 return eacr.es && !eacr.sl;
548}
549
550/*
551 * Check if the etr mode is etr.
552 */
553static inline int etr_mode_is_etr(struct etr_eacr eacr)
554{
555 return eacr.es && eacr.sl;
556}
557
558/*
559 * Check if the port can be used for TOD synchronization.
560 * For PPS mode the port has to receive OTEs. For ETR mode
561 * the port has to receive OTEs, the ETR stepping bit has to
562 * be zero and the validity bits for data frame 1, 2, and 3
563 * have to be 1.
564 */
565static int etr_port_valid(struct etr_aib *aib, int port)
566{
567 unsigned int psc;
568
569 /* Check that this port is receiving OTEs. */
570 if (aib->tsp == 0)
571 return 0;
572
573 psc = port ? aib->esw.psc1 : aib->esw.psc0;
574 if (psc == etr_lpsc_pps_mode)
575 return 1;
576 if (psc == etr_lpsc_operational_step)
577 return !aib->esw.y && aib->slsw.v1 &&
578 aib->slsw.v2 && aib->slsw.v3;
579 return 0;
580}
581
582/*
583 * Check if two ports are on the same network.
584 */
585static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
586{
587 // FIXME: any other fields we have to compare?
588 return aib1->edf1.net_id == aib2->edf1.net_id;
589}
590
591/*
592 * Wrapper for etr_stei that converts physical port states
593 * to logical port states to be consistent with the output
594 * of stetr (see etr_psc vs. etr_lpsc).
595 */
596static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
597{
598 BUG_ON(etr_steai(aib, func) != 0);
599 /* Convert port state to logical port state. */
600 if (aib->esw.psc0 == 1)
601 aib->esw.psc0 = 2;
602 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
603 aib->esw.psc0 = 1;
604 if (aib->esw.psc1 == 1)
605 aib->esw.psc1 = 2;
606 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
607 aib->esw.psc1 = 1;
608}
609
610/*
611 * Check if the aib a2 is still connected to the same attachment as
612 * aib a1, the etv values differ by one and a2 is valid.
613 */
614static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
615{
616 int state_a1, state_a2;
617
618 /* Paranoia check: e0/e1 should better be the same. */
619 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
620 a1->esw.eacr.e1 != a2->esw.eacr.e1)
621 return 0;
622
623 /* Still connected to the same etr ? */
624 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
625 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
626 if (state_a1 == etr_lpsc_operational_step) {
627 if (state_a2 != etr_lpsc_operational_step ||
628 a1->edf1.net_id != a2->edf1.net_id ||
629 a1->edf1.etr_id != a2->edf1.etr_id ||
630 a1->edf1.etr_pn != a2->edf1.etr_pn)
631 return 0;
632 } else if (state_a2 != etr_lpsc_pps_mode)
633 return 0;
634
635 /* The ETV value of a2 needs to be ETV of a1 + 1. */
636 if (a1->edf2.etv + 1 != a2->edf2.etv)
637 return 0;
638
639 if (!etr_port_valid(a2, p))
640 return 0;
641
642 return 1;
643}
644
d2fec595 645struct clock_sync_data {
5a62b192
HC
646 int in_sync;
647 unsigned long long fixup_cc;
d2fec595 648};
5a62b192 649
d2fec595 650static void clock_sync_cpu_start(void *dummy)
d54853ef 651{
d2fec595
MS
652 struct clock_sync_data *sync = dummy;
653
654 enable_sync_clock();
d54853ef
MS
655 /*
656 * This looks like a busy wait loop but it isn't. etr_sync_cpus
657 * is called on all other cpus while the TOD clocks is stopped.
658 * __udelay will stop the cpu on an enabled wait psw until the
659 * TOD is running again.
660 */
d2fec595 661 while (sync->in_sync == 0) {
d54853ef 662 __udelay(1);
6c732de2
HC
663 /*
664 * A different cpu changes *in_sync. Therefore use
665 * barrier() to force memory access.
666 */
667 barrier();
668 }
d2fec595 669 if (sync->in_sync != 1)
d54853ef 670 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 671 disable_sync_clock(NULL);
d54853ef
MS
672 /*
673 * This round of TOD syncing is done. Set the clock comparator
674 * to the next tick and let the processor continue.
675 */
d2fec595 676 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
677}
678
d2fec595 679static void clock_sync_cpu_end(void *dummy)
d54853ef
MS
680{
681}
682
683/*
684 * Sync the TOD clock using the port refered to by aibp. This port
685 * has to be enabled and the other port has to be disabled. The
686 * last eacr update has to be more than 1.6 seconds in the past.
687 */
688static int etr_sync_clock(struct etr_aib *aib, int port)
689{
690 struct etr_aib *sync_port;
d2fec595 691 struct clock_sync_data etr_sync;
5a62b192
HC
692 unsigned long long clock, old_clock, delay, delta;
693 int follows;
d54853ef
MS
694 int rc;
695
696 /* Check if the current aib is adjacent to the sync port aib. */
697 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
698 follows = etr_aib_follows(sync_port, aib, port);
699 memcpy(sync_port, aib, sizeof(*aib));
700 if (!follows)
701 return -EAGAIN;
702
703 /*
704 * Catch all other cpus and make them wait until we have
705 * successfully synced the clock. smp_call_function will
706 * return after all other cpus are in etr_sync_cpu_start.
707 */
5a62b192 708 memset(&etr_sync, 0, sizeof(etr_sync));
d54853ef 709 preempt_disable();
1a781a77 710 smp_call_function(clock_sync_cpu_start, &etr_sync, 0);
d54853ef 711 local_irq_disable();
d2fec595 712 enable_sync_clock();
d54853ef
MS
713
714 /* Set clock to next OTE. */
715 __ctl_set_bit(14, 21);
716 __ctl_set_bit(0, 29);
717 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 718 old_clock = get_clock();
d54853ef
MS
719 if (set_clock(clock) == 0) {
720 __udelay(1); /* Wait for the clock to start. */
721 __ctl_clear_bit(0, 29);
722 __ctl_clear_bit(14, 21);
723 etr_stetr(aib);
724 /* Adjust Linux timing variables. */
725 delay = (unsigned long long)
726 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 727 delta = adjust_time(old_clock, clock, delay);
5a62b192
HC
728 etr_sync.fixup_cc = delta;
729 fixup_clock_comparator(delta);
d54853ef
MS
730 /* Verify that the clock is properly set. */
731 if (!etr_aib_follows(sync_port, aib, port)) {
732 /* Didn't work. */
d2fec595 733 disable_sync_clock(NULL);
5a62b192 734 etr_sync.in_sync = -EAGAIN;
d54853ef
MS
735 rc = -EAGAIN;
736 } else {
5a62b192 737 etr_sync.in_sync = 1;
d54853ef
MS
738 rc = 0;
739 }
740 } else {
741 /* Could not set the clock ?!? */
742 __ctl_clear_bit(0, 29);
743 __ctl_clear_bit(14, 21);
d2fec595 744 disable_sync_clock(NULL);
5a62b192 745 etr_sync.in_sync = -EAGAIN;
d54853ef
MS
746 rc = -EAGAIN;
747 }
748 local_irq_enable();
1a781a77 749 smp_call_function(clock_sync_cpu_end, NULL, 0);
d54853ef
MS
750 preempt_enable();
751 return rc;
752}
753
754/*
755 * Handle the immediate effects of the different events.
756 * The port change event is used for online/offline changes.
757 */
758static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
759{
760 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
761 eacr.es = 0;
762 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
763 eacr.es = eacr.sl = 0;
764 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
765 etr_port0_uptodate = etr_port1_uptodate = 0;
766
767 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
768 if (eacr.e0)
769 /*
770 * Port change of an enabled port. We have to
771 * assume that this can have caused an stepping
772 * port switch.
773 */
774 etr_tolec = get_clock();
775 eacr.p0 = etr_port0_online;
776 if (!eacr.p0)
777 eacr.e0 = 0;
778 etr_port0_uptodate = 0;
779 }
780 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
781 if (eacr.e1)
782 /*
783 * Port change of an enabled port. We have to
784 * assume that this can have caused an stepping
785 * port switch.
786 */
787 etr_tolec = get_clock();
788 eacr.p1 = etr_port1_online;
789 if (!eacr.p1)
790 eacr.e1 = 0;
791 etr_port1_uptodate = 0;
792 }
793 clear_bit(ETR_EVENT_UPDATE, &etr_events);
794 return eacr;
795}
796
797/*
798 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
799 * one of the ports needs an update.
800 */
801static void etr_set_tolec_timeout(unsigned long long now)
802{
803 unsigned long micros;
804
805 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
806 (!etr_eacr.p1 || etr_port1_uptodate))
807 return;
808 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
809 micros = (micros > 1600000) ? 0 : 1600000 - micros;
810 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
811}
812
813/*
814 * Set up a time that expires after 1/2 second.
815 */
816static void etr_set_sync_timeout(void)
817{
818 mod_timer(&etr_timer, jiffies + HZ/2);
819}
820
821/*
822 * Update the aib information for one or both ports.
823 */
824static struct etr_eacr etr_handle_update(struct etr_aib *aib,
825 struct etr_eacr eacr)
826{
827 /* With both ports disabled the aib information is useless. */
828 if (!eacr.e0 && !eacr.e1)
829 return eacr;
830
ecdcc023 831 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
832 if (aib->esw.q == 0) {
833 /* Information for port 0 stored. */
834 if (eacr.p0 && !etr_port0_uptodate) {
835 etr_port0 = *aib;
836 if (etr_port0_online)
837 etr_port0_uptodate = 1;
838 }
839 } else {
840 /* Information for port 1 stored. */
841 if (eacr.p1 && !etr_port1_uptodate) {
842 etr_port1 = *aib;
843 if (etr_port0_online)
844 etr_port1_uptodate = 1;
845 }
846 }
847
848 /*
849 * Do not try to get the alternate port aib if the clock
850 * is not in sync yet.
851 */
d2fec595 852 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags) && !eacr.es)
d54853ef
MS
853 return eacr;
854
855 /*
856 * If steai is available we can get the information about
857 * the other port immediately. If only stetr is available the
858 * data-port bit toggle has to be used.
859 */
d2fec595 860 if (etr_steai_available) {
d54853ef
MS
861 if (eacr.p0 && !etr_port0_uptodate) {
862 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
863 etr_port0_uptodate = 1;
864 }
865 if (eacr.p1 && !etr_port1_uptodate) {
866 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
867 etr_port1_uptodate = 1;
868 }
869 } else {
870 /*
871 * One port was updated above, if the other
872 * port is not uptodate toggle dp bit.
873 */
874 if ((eacr.p0 && !etr_port0_uptodate) ||
875 (eacr.p1 && !etr_port1_uptodate))
876 eacr.dp ^= 1;
877 else
878 eacr.dp = 0;
879 }
880 return eacr;
881}
882
883/*
884 * Write new etr control register if it differs from the current one.
885 * Return 1 if etr_tolec has been updated as well.
886 */
887static void etr_update_eacr(struct etr_eacr eacr)
888{
889 int dp_changed;
890
891 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
892 /* No change, return. */
893 return;
894 /*
895 * The disable of an active port of the change of the data port
896 * bit can/will cause a change in the data port.
897 */
898 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
899 (etr_eacr.dp ^ eacr.dp) != 0;
900 etr_eacr = eacr;
901 etr_setr(&etr_eacr);
902 if (dp_changed)
903 etr_tolec = get_clock();
904}
905
906/*
907 * ETR tasklet. In this function you'll find the main logic. In
908 * particular this is the only function that calls etr_update_eacr(),
909 * it "controls" the etr control register.
910 */
ecdcc023 911static void etr_work_fn(struct work_struct *work)
d54853ef
MS
912{
913 unsigned long long now;
914 struct etr_eacr eacr;
915 struct etr_aib aib;
916 int sync_port;
917
918 /* Create working copy of etr_eacr. */
919 eacr = etr_eacr;
920
921 /* Check for the different events and their immediate effects. */
922 eacr = etr_handle_events(eacr);
923
924 /* Check if ETR is supposed to be active. */
925 eacr.ea = eacr.p0 || eacr.p1;
926 if (!eacr.ea) {
927 /* Both ports offline. Reset everything. */
928 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 929 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
930 del_timer_sync(&etr_timer);
931 etr_update_eacr(eacr);
d2fec595 932 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
933 return;
934 }
935
936 /* Store aib to get the current ETR status word. */
937 BUG_ON(etr_stetr(&aib) != 0);
938 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
939 now = get_clock();
940
941 /*
942 * Update the port information if the last stepping port change
943 * or data port change is older than 1.6 seconds.
944 */
945 if (now >= etr_tolec + (1600000 << 12))
946 eacr = etr_handle_update(&aib, eacr);
947
948 /*
949 * Select ports to enable. The prefered synchronization mode is PPS.
950 * If a port can be enabled depends on a number of things:
951 * 1) The port needs to be online and uptodate. A port is not
952 * disabled just because it is not uptodate, but it is only
953 * enabled if it is uptodate.
954 * 2) The port needs to have the same mode (pps / etr).
955 * 3) The port needs to be usable -> etr_port_valid() == 1
956 * 4) To enable the second port the clock needs to be in sync.
957 * 5) If both ports are useable and are ETR ports, the network id
958 * has to be the same.
959 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
960 */
961 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
962 eacr.sl = 0;
963 eacr.e0 = 1;
964 if (!etr_mode_is_pps(etr_eacr))
965 eacr.es = 0;
966 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
967 eacr.e1 = 0;
968 // FIXME: uptodate checks ?
969 else if (etr_port0_uptodate && etr_port1_uptodate)
970 eacr.e1 = 1;
971 sync_port = (etr_port0_uptodate &&
972 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
973 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
974 eacr.sl = 0;
975 eacr.e0 = 0;
976 eacr.e1 = 1;
977 if (!etr_mode_is_pps(etr_eacr))
978 eacr.es = 0;
979 sync_port = (etr_port1_uptodate &&
980 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
981 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
982 eacr.sl = 1;
983 eacr.e0 = 1;
984 if (!etr_mode_is_etr(etr_eacr))
985 eacr.es = 0;
986 if (!eacr.es || !eacr.p1 ||
987 aib.esw.psc1 != etr_lpsc_operational_alt)
988 eacr.e1 = 0;
989 else if (etr_port0_uptodate && etr_port1_uptodate &&
990 etr_compare_network(&etr_port0, &etr_port1))
991 eacr.e1 = 1;
992 sync_port = (etr_port0_uptodate &&
993 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
994 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
995 eacr.sl = 1;
996 eacr.e0 = 0;
997 eacr.e1 = 1;
998 if (!etr_mode_is_etr(etr_eacr))
999 eacr.es = 0;
1000 sync_port = (etr_port1_uptodate &&
1001 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1002 } else {
1003 /* Both ports not usable. */
1004 eacr.es = eacr.sl = 0;
1005 sync_port = -1;
d2fec595 1006 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1007 }
1008
d2fec595
MS
1009 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
1010 eacr.es = 0;
1011
d54853ef
MS
1012 /*
1013 * If the clock is in sync just update the eacr and return.
1014 * If there is no valid sync port wait for a port update.
1015 */
d2fec595
MS
1016 if (test_bit(CLOCK_SYNC_STP, &clock_sync_flags) ||
1017 eacr.es || sync_port < 0) {
d54853ef
MS
1018 etr_update_eacr(eacr);
1019 etr_set_tolec_timeout(now);
1020 return;
1021 }
1022
1023 /*
1024 * Prepare control register for clock syncing
1025 * (reset data port bit, set sync check control.
1026 */
1027 eacr.dp = 0;
1028 eacr.es = 1;
1029
1030 /*
1031 * Update eacr and try to synchronize the clock. If the update
1032 * of eacr caused a stepping port switch (or if we have to
1033 * assume that a stepping port switch has occured) or the
1034 * clock syncing failed, reset the sync check control bit
1035 * and set up a timer to try again after 0.5 seconds
1036 */
1037 etr_update_eacr(eacr);
d2fec595 1038 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1039 if (now < etr_tolec + (1600000 << 12) ||
1040 etr_sync_clock(&aib, sync_port) != 0) {
1041 /* Sync failed. Try again in 1/2 second. */
1042 eacr.es = 0;
1043 etr_update_eacr(eacr);
d2fec595 1044 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1045 etr_set_sync_timeout();
1046 } else
1047 etr_set_tolec_timeout(now);
1048}
1049
1050/*
1051 * Sysfs interface functions
1052 */
1053static struct sysdev_class etr_sysclass = {
af5ca3f4 1054 .name = "etr",
d54853ef
MS
1055};
1056
1057static struct sys_device etr_port0_dev = {
1058 .id = 0,
1059 .cls = &etr_sysclass,
1060};
1061
1062static struct sys_device etr_port1_dev = {
1063 .id = 1,
1064 .cls = &etr_sysclass,
1065};
1066
1067/*
1068 * ETR class attributes
1069 */
1070static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf)
1071{
1072 return sprintf(buf, "%i\n", etr_port0.esw.p);
1073}
1074
1075static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1076
1077static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf)
1078{
1079 char *mode_str;
1080
1081 if (etr_mode_is_pps(etr_eacr))
1082 mode_str = "pps";
1083 else if (etr_mode_is_etr(etr_eacr))
1084 mode_str = "etr";
1085 else
1086 mode_str = "local";
1087 return sprintf(buf, "%s\n", mode_str);
1088}
1089
1090static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1091
1092/*
1093 * ETR port attributes
1094 */
1095static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1096{
1097 if (dev == &etr_port0_dev)
1098 return etr_port0_online ? &etr_port0 : NULL;
1099 else
1100 return etr_port1_online ? &etr_port1 : NULL;
1101}
1102
1103static ssize_t etr_online_show(struct sys_device *dev, char *buf)
1104{
1105 unsigned int online;
1106
1107 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1108 return sprintf(buf, "%i\n", online);
1109}
1110
1111static ssize_t etr_online_store(struct sys_device *dev,
1112 const char *buf, size_t count)
1113{
1114 unsigned int value;
1115
1116 value = simple_strtoul(buf, NULL, 0);
1117 if (value != 0 && value != 1)
1118 return -EINVAL;
d2fec595
MS
1119 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1120 return -EOPNOTSUPP;
d54853ef
MS
1121 if (dev == &etr_port0_dev) {
1122 if (etr_port0_online == value)
1123 return count; /* Nothing to do. */
1124 etr_port0_online = value;
1125 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
ecdcc023 1126 schedule_work(&etr_work);
d54853ef
MS
1127 } else {
1128 if (etr_port1_online == value)
1129 return count; /* Nothing to do. */
1130 etr_port1_online = value;
1131 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
ecdcc023 1132 schedule_work(&etr_work);
d54853ef
MS
1133 }
1134 return count;
1135}
1136
1137static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1138
1139static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf)
1140{
1141 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1142 etr_eacr.e0 : etr_eacr.e1);
1143}
1144
1145static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1146
1147static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf)
1148{
1149 if (!etr_port0_online && !etr_port1_online)
1150 /* Status word is not uptodate if both ports are offline. */
1151 return -ENODATA;
1152 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1153 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1154}
1155
1156static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1157
1158static ssize_t etr_untuned_show(struct sys_device *dev, char *buf)
1159{
1160 struct etr_aib *aib = etr_aib_from_dev(dev);
1161
1162 if (!aib || !aib->slsw.v1)
1163 return -ENODATA;
1164 return sprintf(buf, "%i\n", aib->edf1.u);
1165}
1166
1167static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1168
1169static ssize_t etr_network_id_show(struct sys_device *dev, char *buf)
1170{
1171 struct etr_aib *aib = etr_aib_from_dev(dev);
1172
1173 if (!aib || !aib->slsw.v1)
1174 return -ENODATA;
1175 return sprintf(buf, "%i\n", aib->edf1.net_id);
1176}
1177
1178static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1179
1180static ssize_t etr_id_show(struct sys_device *dev, char *buf)
1181{
1182 struct etr_aib *aib = etr_aib_from_dev(dev);
1183
1184 if (!aib || !aib->slsw.v1)
1185 return -ENODATA;
1186 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1187}
1188
1189static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1190
1191static ssize_t etr_port_number_show(struct sys_device *dev, char *buf)
1192{
1193 struct etr_aib *aib = etr_aib_from_dev(dev);
1194
1195 if (!aib || !aib->slsw.v1)
1196 return -ENODATA;
1197 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1198}
1199
1200static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1201
1202static ssize_t etr_coupled_show(struct sys_device *dev, char *buf)
1203{
1204 struct etr_aib *aib = etr_aib_from_dev(dev);
1205
1206 if (!aib || !aib->slsw.v3)
1207 return -ENODATA;
1208 return sprintf(buf, "%i\n", aib->edf3.c);
1209}
1210
1211static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1212
1213static ssize_t etr_local_time_show(struct sys_device *dev, char *buf)
1214{
1215 struct etr_aib *aib = etr_aib_from_dev(dev);
1216
1217 if (!aib || !aib->slsw.v3)
1218 return -ENODATA;
1219 return sprintf(buf, "%i\n", aib->edf3.blto);
1220}
1221
1222static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1223
1224static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf)
1225{
1226 struct etr_aib *aib = etr_aib_from_dev(dev);
1227
1228 if (!aib || !aib->slsw.v3)
1229 return -ENODATA;
1230 return sprintf(buf, "%i\n", aib->edf3.buo);
1231}
1232
1233static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1234
1235static struct sysdev_attribute *etr_port_attributes[] = {
1236 &attr_online,
1237 &attr_stepping_control,
1238 &attr_state_code,
1239 &attr_untuned,
1240 &attr_network,
1241 &attr_id,
1242 &attr_port,
1243 &attr_coupled,
1244 &attr_local_time,
1245 &attr_utc_offset,
1246 NULL
1247};
1248
1249static int __init etr_register_port(struct sys_device *dev)
1250{
1251 struct sysdev_attribute **attr;
1252 int rc;
1253
1254 rc = sysdev_register(dev);
1255 if (rc)
1256 goto out;
1257 for (attr = etr_port_attributes; *attr; attr++) {
1258 rc = sysdev_create_file(dev, *attr);
1259 if (rc)
1260 goto out_unreg;
1261 }
1262 return 0;
1263out_unreg:
1264 for (; attr >= etr_port_attributes; attr--)
1265 sysdev_remove_file(dev, *attr);
1266 sysdev_unregister(dev);
1267out:
1268 return rc;
1269}
1270
1271static void __init etr_unregister_port(struct sys_device *dev)
1272{
1273 struct sysdev_attribute **attr;
1274
1275 for (attr = etr_port_attributes; *attr; attr++)
1276 sysdev_remove_file(dev, *attr);
1277 sysdev_unregister(dev);
1278}
1279
1280static int __init etr_init_sysfs(void)
1281{
1282 int rc;
1283
1284 rc = sysdev_class_register(&etr_sysclass);
1285 if (rc)
1286 goto out;
1287 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1288 if (rc)
1289 goto out_unreg_class;
1290 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1291 if (rc)
1292 goto out_remove_stepping_port;
1293 rc = etr_register_port(&etr_port0_dev);
1294 if (rc)
1295 goto out_remove_stepping_mode;
1296 rc = etr_register_port(&etr_port1_dev);
1297 if (rc)
1298 goto out_remove_port0;
1299 return 0;
1300
1301out_remove_port0:
1302 etr_unregister_port(&etr_port0_dev);
1303out_remove_stepping_mode:
1304 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1305out_remove_stepping_port:
1306 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1307out_unreg_class:
1308 sysdev_class_unregister(&etr_sysclass);
1309out:
1310 return rc;
1da177e4
LT
1311}
1312
d54853ef 1313device_initcall(etr_init_sysfs);
d2fec595
MS
1314
1315/*
1316 * Server Time Protocol (STP) code.
1317 */
1318static int stp_online;
1319static struct stp_sstpi stp_info;
1320static void *stp_page;
1321
1322static void stp_work_fn(struct work_struct *work);
1323static DECLARE_WORK(stp_work, stp_work_fn);
1324
1325static int __init early_parse_stp(char *p)
1326{
1327 if (strncmp(p, "off", 3) == 0)
1328 stp_online = 0;
1329 else if (strncmp(p, "on", 2) == 0)
1330 stp_online = 1;
1331 return 0;
1332}
1333early_param("stp", early_parse_stp);
1334
1335/*
1336 * Reset STP attachment.
1337 */
1338static void stp_reset(void)
1339{
1340 int rc;
1341
1342 stp_page = alloc_bootmem_pages(PAGE_SIZE);
1343 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
1344 if (rc == 1)
1345 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1346 else if (stp_online) {
1347 printk(KERN_WARNING "Running on non STP capable machine.\n");
1348 free_bootmem((unsigned long) stp_page, PAGE_SIZE);
1349 stp_page = NULL;
1350 stp_online = 0;
1351 }
1352}
1353
1354static int __init stp_init(void)
1355{
1356 if (test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags) && stp_online)
1357 schedule_work(&stp_work);
1358 return 0;
1359}
1360
1361arch_initcall(stp_init);
1362
1363/*
1364 * STP timing alert. There are three causes:
1365 * 1) timing status change
1366 * 2) link availability change
1367 * 3) time control parameter change
1368 * In all three cases we are only interested in the clock source state.
1369 * If a STP clock source is now available use it.
1370 */
1371static void stp_timing_alert(struct stp_irq_parm *intparm)
1372{
1373 if (intparm->tsc || intparm->lac || intparm->tcpc)
1374 schedule_work(&stp_work);
1375}
1376
1377/*
1378 * STP sync check machine check. This is called when the timing state
1379 * changes from the synchronized state to the unsynchronized state.
1380 * After a STP sync check the clock is not in sync. The machine check
1381 * is broadcasted to all cpus at the same time.
1382 */
1383void stp_sync_check(void)
1384{
1385 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
1386 return;
1387 disable_sync_clock(NULL);
1388 schedule_work(&stp_work);
1389}
1390
1391/*
1392 * STP island condition machine check. This is called when an attached
1393 * server attempts to communicate over an STP link and the servers
1394 * have matching CTN ids and have a valid stratum-1 configuration
1395 * but the configurations do not match.
1396 */
1397void stp_island_check(void)
1398{
1399 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
1400 return;
1401 disable_sync_clock(NULL);
1402 schedule_work(&stp_work);
1403}
1404
1405/*
1406 * STP tasklet. Check for the STP state and take over the clock
1407 * synchronization if the STP clock source is usable.
1408 */
1409static void stp_work_fn(struct work_struct *work)
1410{
1411 struct clock_sync_data stp_sync;
1412 unsigned long long old_clock, delta;
1413 int rc;
1414
1415 if (!stp_online) {
1416 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
1417 return;
1418 }
1419
1420 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1421 if (rc)
1422 return;
1423
1424 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1425 if (rc || stp_info.c == 0)
1426 return;
1427
1428 /*
1429 * Catch all other cpus and make them wait until we have
1430 * successfully synced the clock. smp_call_function will
1431 * return after all other cpus are in clock_sync_cpu_start.
1432 */
1433 memset(&stp_sync, 0, sizeof(stp_sync));
1434 preempt_disable();
f6f88e9b 1435 smp_call_function(clock_sync_cpu_start, &stp_sync, 0);
d2fec595
MS
1436 local_irq_disable();
1437 enable_sync_clock();
1438
1439 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1440 if (test_and_clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
1441 schedule_work(&etr_work);
1442
1443 rc = 0;
1444 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1445 stp_info.todoff[2] || stp_info.todoff[3] ||
1446 stp_info.tmd != 2) {
1447 old_clock = get_clock();
1448 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1449 if (rc == 0) {
1450 delta = adjust_time(old_clock, get_clock(), 0);
1451 fixup_clock_comparator(delta);
1452 rc = chsc_sstpi(stp_page, &stp_info,
1453 sizeof(struct stp_sstpi));
1454 if (rc == 0 && stp_info.tmd != 2)
1455 rc = -EAGAIN;
1456 }
1457 }
1458 if (rc) {
1459 disable_sync_clock(NULL);
1460 stp_sync.in_sync = -EAGAIN;
1461 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1462 if (etr_port0_online || etr_port1_online)
1463 schedule_work(&etr_work);
1464 } else
1465 stp_sync.in_sync = 1;
1466
1467 local_irq_enable();
f6f88e9b 1468 smp_call_function(clock_sync_cpu_end, NULL, 0);
d2fec595
MS
1469 preempt_enable();
1470}
1471
1472/*
1473 * STP class sysfs interface functions
1474 */
1475static struct sysdev_class stp_sysclass = {
1476 .name = "stp",
1477};
1478
1479static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf)
1480{
1481 if (!stp_online)
1482 return -ENODATA;
1483 return sprintf(buf, "%016llx\n",
1484 *(unsigned long long *) stp_info.ctnid);
1485}
1486
1487static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
1488
1489static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf)
1490{
1491 if (!stp_online)
1492 return -ENODATA;
1493 return sprintf(buf, "%i\n", stp_info.ctn);
1494}
1495
1496static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
1497
1498static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf)
1499{
1500 if (!stp_online || !(stp_info.vbits & 0x2000))
1501 return -ENODATA;
1502 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1503}
1504
1505static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
1506
1507static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf)
1508{
1509 if (!stp_online || !(stp_info.vbits & 0x8000))
1510 return -ENODATA;
1511 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1512}
1513
1514static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
1515
1516static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf)
1517{
1518 if (!stp_online)
1519 return -ENODATA;
1520 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1521}
1522
1523static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
1524
1525static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf)
1526{
1527 if (!stp_online || !(stp_info.vbits & 0x0800))
1528 return -ENODATA;
1529 return sprintf(buf, "%i\n", (int) stp_info.tto);
1530}
1531
1532static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
1533
1534static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf)
1535{
1536 if (!stp_online || !(stp_info.vbits & 0x4000))
1537 return -ENODATA;
1538 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1539}
1540
1541static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
1542 stp_time_zone_offset_show, NULL);
1543
1544static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf)
1545{
1546 if (!stp_online)
1547 return -ENODATA;
1548 return sprintf(buf, "%i\n", stp_info.tmd);
1549}
1550
1551static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
1552
1553static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf)
1554{
1555 if (!stp_online)
1556 return -ENODATA;
1557 return sprintf(buf, "%i\n", stp_info.tst);
1558}
1559
1560static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
1561
1562static ssize_t stp_online_show(struct sysdev_class *class, char *buf)
1563{
1564 return sprintf(buf, "%i\n", stp_online);
1565}
1566
1567static ssize_t stp_online_store(struct sysdev_class *class,
1568 const char *buf, size_t count)
1569{
1570 unsigned int value;
1571
1572 value = simple_strtoul(buf, NULL, 0);
1573 if (value != 0 && value != 1)
1574 return -EINVAL;
1575 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1576 return -EOPNOTSUPP;
1577 stp_online = value;
1578 schedule_work(&stp_work);
1579 return count;
1580}
1581
1582/*
1583 * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
1584 * stp/online but attr_online already exists in this file ..
1585 */
1586static struct sysdev_class_attribute attr_stp_online = {
1587 .attr = { .name = "online", .mode = 0600 },
1588 .show = stp_online_show,
1589 .store = stp_online_store,
1590};
1591
1592static struct sysdev_class_attribute *stp_attributes[] = {
1593 &attr_ctn_id,
1594 &attr_ctn_type,
1595 &attr_dst_offset,
1596 &attr_leap_seconds,
1597 &attr_stp_online,
1598 &attr_stratum,
1599 &attr_time_offset,
1600 &attr_time_zone_offset,
1601 &attr_timing_mode,
1602 &attr_timing_state,
1603 NULL
1604};
1605
1606static int __init stp_init_sysfs(void)
1607{
1608 struct sysdev_class_attribute **attr;
1609 int rc;
1610
1611 rc = sysdev_class_register(&stp_sysclass);
1612 if (rc)
1613 goto out;
1614 for (attr = stp_attributes; *attr; attr++) {
1615 rc = sysdev_class_create_file(&stp_sysclass, *attr);
1616 if (rc)
1617 goto out_unreg;
1618 }
1619 return 0;
1620out_unreg:
1621 for (; attr >= stp_attributes; attr--)
1622 sysdev_class_remove_file(&stp_sysclass, *attr);
1623 sysdev_class_unregister(&stp_sysclass);
1624out:
1625 return rc;
1626}
1627
1628device_initcall(stp_init_sysfs);
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