dw_apb_timer: constify clocksource name
[deliverable/linux.git] / arch / s390 / kernel / time.c
CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
feab6501
MS
15#define KMSG_COMPONENT "time"
16#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
17
052ff461 18#include <linux/kernel_stat.h>
1da177e4
LT
19#include <linux/errno.h>
20#include <linux/module.h>
21#include <linux/sched.h>
22#include <linux/kernel.h>
23#include <linux/param.h>
24#include <linux/string.h>
25#include <linux/mm.h>
26#include <linux/interrupt.h>
750887de
HC
27#include <linux/cpu.h>
28#include <linux/stop_machine.h>
1da177e4 29#include <linux/time.h>
3367b994 30#include <linux/sysdev.h>
1da177e4
LT
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/smp.h>
34#include <linux/types.h>
35#include <linux/profile.h>
36#include <linux/timex.h>
37#include <linux/notifier.h>
dc64bef5 38#include <linux/clocksource.h>
5a62b192 39#include <linux/clockchips.h>
5a0e3ad6 40#include <linux/gfp.h>
860dba45 41#include <linux/kprobes.h>
1da177e4
LT
42#include <asm/uaccess.h>
43#include <asm/delay.h>
1da177e4 44#include <asm/div64.h>
b020632e 45#include <asm/vdso.h>
1da177e4 46#include <asm/irq.h>
5a489b98 47#include <asm/irq_regs.h>
1da177e4 48#include <asm/timer.h>
d54853ef 49#include <asm/etr.h>
a806170e 50#include <asm/cio.h>
1da177e4
LT
51
52/* change this if you have some constant time drift */
53#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
54#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
55
b6112ccb 56u64 sched_clock_base_cc = -1; /* Force to data section. */
05e7ff7d 57EXPORT_SYMBOL_GPL(sched_clock_base_cc);
b6112ccb 58
5a62b192 59static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 60
1da177e4
LT
61/*
62 * Scheduler clock - returns current time in nanosec units.
63 */
860dba45 64unsigned long long notrace __kprobes sched_clock(void)
1da177e4 65{
05e7ff7d 66 return (get_clock_monotonic() * 125) >> 9;
1da177e4
LT
67}
68
32f65f27
JG
69/*
70 * Monotonic_clock - returns # of nanoseconds passed since time_init()
71 */
72unsigned long long monotonic_clock(void)
73{
74 return sched_clock();
75}
76EXPORT_SYMBOL(monotonic_clock);
77
b1e2ba8d 78void tod_to_timeval(__u64 todval, struct timespec *xt)
1da177e4
LT
79{
80 unsigned long long sec;
81
82 sec = todval >> 12;
83 do_div(sec, 1000000);
b1e2ba8d 84 xt->tv_sec = sec;
1da177e4 85 todval -= (sec * 1000000) << 12;
b1e2ba8d 86 xt->tv_nsec = ((todval * 1000) >> 12);
1da177e4 87}
b592e89a 88EXPORT_SYMBOL(tod_to_timeval);
1da177e4 89
5a62b192 90void clock_comparator_work(void)
1da177e4 91{
5a62b192 92 struct clock_event_device *cd;
1da177e4 93
5a62b192
HC
94 S390_lowcore.clock_comparator = -1ULL;
95 set_clock_comparator(S390_lowcore.clock_comparator);
96 cd = &__get_cpu_var(comparators);
97 cd->event_handler(cd);
1da177e4
LT
98}
99
1da177e4 100/*
5a62b192 101 * Fixup the clock comparator.
1da177e4 102 */
5a62b192 103static void fixup_clock_comparator(unsigned long long delta)
1da177e4 104{
5a62b192
HC
105 /* If nobody is waiting there's nothing to fix. */
106 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 107 return;
5a62b192
HC
108 S390_lowcore.clock_comparator += delta;
109 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
110}
111
4f37a68c 112static int s390_next_ktime(ktime_t expires,
5a62b192 113 struct clock_event_device *evt)
1da177e4 114{
4f37a68c
MS
115 s64 nsecs;
116
117 nsecs = ktime_to_ns(ktime_sub(expires, ktime_get_monotonic_offset()));
118 do_div(nsecs, 125);
119 S390_lowcore.clock_comparator = TOD_UNIX_EPOCH + (nsecs << 9);
5a62b192
HC
120 set_clock_comparator(S390_lowcore.clock_comparator);
121 return 0;
1da177e4
LT
122}
123
5a62b192
HC
124static void s390_set_mode(enum clock_event_mode mode,
125 struct clock_event_device *evt)
1da177e4 126{
d54853ef
MS
127}
128
129/*
130 * Set up lowcore and control register of the current cpu to
131 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
132 */
133void init_cpu_timer(void)
134{
5a62b192
HC
135 struct clock_event_device *cd;
136 int cpu;
137
138 S390_lowcore.clock_comparator = -1ULL;
139 set_clock_comparator(S390_lowcore.clock_comparator);
140
141 cpu = smp_processor_id();
142 cd = &per_cpu(comparators, cpu);
143 cd->name = "comparator";
4f37a68c
MS
144 cd->features = CLOCK_EVT_FEAT_ONESHOT |
145 CLOCK_EVT_FEAT_KTIME;
5a62b192
HC
146 cd->mult = 16777;
147 cd->shift = 12;
148 cd->min_delta_ns = 1;
149 cd->max_delta_ns = LONG_MAX;
150 cd->rating = 400;
320ab2b0 151 cd->cpumask = cpumask_of(cpu);
4f37a68c 152 cd->set_next_ktime = s390_next_ktime;
5a62b192
HC
153 cd->set_mode = s390_set_mode;
154
155 clockevents_register_device(cd);
d54853ef
MS
156
157 /* Enable clock comparator timer interrupt. */
158 __ctl_set_bit(0,11);
159
d2fec595 160 /* Always allow the timing alert external interrupt. */
d54853ef
MS
161 __ctl_set_bit(0, 4);
162}
163
f6649a7e
MS
164static void clock_comparator_interrupt(unsigned int ext_int_code,
165 unsigned int param32,
166 unsigned long param64)
d54853ef 167{
052ff461 168 kstat_cpu(smp_processor_id()).irqs[EXTINT_CLK]++;
d3d238c7
HC
169 if (S390_lowcore.clock_comparator == -1ULL)
170 set_clock_comparator(S390_lowcore.clock_comparator);
d54853ef
MS
171}
172
d2fec595
MS
173static void etr_timing_alert(struct etr_irq_parm *);
174static void stp_timing_alert(struct stp_irq_parm *);
175
f6649a7e
MS
176static void timing_alert_interrupt(unsigned int ext_int_code,
177 unsigned int param32, unsigned long param64)
d2fec595 178{
052ff461 179 kstat_cpu(smp_processor_id()).irqs[EXTINT_TLA]++;
f6649a7e
MS
180 if (param32 & 0x00c40000)
181 etr_timing_alert((struct etr_irq_parm *) &param32);
182 if (param32 & 0x00038000)
183 stp_timing_alert((struct stp_irq_parm *) &param32);
d2fec595
MS
184}
185
d54853ef 186static void etr_reset(void);
d2fec595 187static void stp_reset(void);
d54853ef 188
d4f587c6 189void read_persistent_clock(struct timespec *ts)
d54853ef 190{
d4f587c6 191 tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, ts);
1da177e4 192}
d54853ef 193
23970e38
MS
194void read_boot_clock(struct timespec *ts)
195{
196 tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts);
1da177e4
LT
197}
198
8e19608e 199static cycle_t read_tod_clock(struct clocksource *cs)
dc64bef5
MS
200{
201 return get_clock();
202}
203
204static struct clocksource clocksource_tod = {
205 .name = "tod",
d2cb0e6e 206 .rating = 400,
dc64bef5
MS
207 .read = read_tod_clock,
208 .mask = -1ULL,
209 .mult = 1000,
210 .shift = 12,
cc02d809 211 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
212};
213
f1b82746
MS
214struct clocksource * __init clocksource_default_clock(void)
215{
216 return &clocksource_tod;
217}
dc64bef5 218
7615856e
JS
219void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
220 struct clocksource *clock, u32 mult)
b020632e
MS
221{
222 if (clock != &clocksource_tod)
223 return;
224
225 /* Make userspace gettimeofday spin until we're done. */
226 ++vdso_data->tb_update_count;
227 smp_wmb();
228 vdso_data->xtime_tod_stamp = clock->cycle_last;
b1e2ba8d
JS
229 vdso_data->xtime_clock_sec = wall_time->tv_sec;
230 vdso_data->xtime_clock_nsec = wall_time->tv_nsec;
7615856e
JS
231 vdso_data->wtom_clock_sec = wtm->tv_sec;
232 vdso_data->wtom_clock_nsec = wtm->tv_nsec;
157a1a27 233 vdso_data->ntp_mult = mult;
b020632e
MS
234 smp_wmb();
235 ++vdso_data->tb_update_count;
236}
237
238extern struct timezone sys_tz;
239
240void update_vsyscall_tz(void)
241{
242 /* Make userspace gettimeofday spin until we're done. */
243 ++vdso_data->tb_update_count;
244 smp_wmb();
245 vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
246 vdso_data->tz_dsttime = sys_tz.tz_dsttime;
247 smp_wmb();
248 ++vdso_data->tb_update_count;
249}
250
1da177e4
LT
251/*
252 * Initialize the TOD clock and the CPU timer of
253 * the boot cpu.
254 */
255void __init time_init(void)
256{
b6112ccb
MS
257 /* Reset time synchronization interfaces. */
258 etr_reset();
259 stp_reset();
1da177e4 260
1da177e4 261 /* request the clock comparator external interrupt */
d7d1104f 262 if (register_external_interrupt(0x1004, clock_comparator_interrupt))
1da177e4
LT
263 panic("Couldn't request external interrupt 0x1004");
264
d2fec595 265 /* request the timing alert external interrupt */
d7d1104f 266 if (register_external_interrupt(0x1406, timing_alert_interrupt))
d54853ef
MS
267 panic("Couldn't request external interrupt 0x1406");
268
ab96e798
MS
269 if (clocksource_register(&clocksource_tod) != 0)
270 panic("Could not register TOD clock source");
271
d54853ef
MS
272 /* Enable TOD clock interrupts on the boot cpu. */
273 init_cpu_timer();
ab96e798 274
c185b783 275 /* Enable cpu timer interrupts on the boot cpu. */
1da177e4 276 vtime_init();
d54853ef
MS
277}
278
d2fec595
MS
279/*
280 * The time is "clock". old is what we think the time is.
281 * Adjust the value by a multiple of jiffies and add the delta to ntp.
282 * "delay" is an approximation how long the synchronization took. If
283 * the time correction is positive, then "delay" is subtracted from
284 * the time difference and only the remaining part is passed to ntp.
285 */
286static unsigned long long adjust_time(unsigned long long old,
287 unsigned long long clock,
288 unsigned long long delay)
289{
290 unsigned long long delta, ticks;
291 struct timex adjust;
292
293 if (clock > old) {
294 /* It is later than we thought. */
295 delta = ticks = clock - old;
296 delta = ticks = (delta < delay) ? 0 : delta - delay;
297 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
298 adjust.offset = ticks * (1000000 / HZ);
299 } else {
300 /* It is earlier than we thought. */
301 delta = ticks = old - clock;
302 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
303 delta = -delta;
304 adjust.offset = -ticks * (1000000 / HZ);
305 }
8107d829 306 sched_clock_base_cc += delta;
d2fec595 307 if (adjust.offset != 0) {
feab6501
MS
308 pr_notice("The ETR interface has adjusted the clock "
309 "by %li microseconds\n", adjust.offset);
d2fec595
MS
310 adjust.modes = ADJ_OFFSET_SINGLESHOT;
311 do_adjtimex(&adjust);
312 }
313 return delta;
314}
315
316static DEFINE_PER_CPU(atomic_t, clock_sync_word);
8283cb43 317static DEFINE_MUTEX(clock_sync_mutex);
d2fec595
MS
318static unsigned long clock_sync_flags;
319
320#define CLOCK_SYNC_HAS_ETR 0
321#define CLOCK_SYNC_HAS_STP 1
322#define CLOCK_SYNC_ETR 2
323#define CLOCK_SYNC_STP 3
324
325/*
326 * The synchronous get_clock function. It will write the current clock
327 * value to the clock pointer and return 0 if the clock is in sync with
328 * the external time source. If the clock mode is local it will return
329 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
330 * reference.
331 */
332int get_sync_clock(unsigned long long *clock)
333{
334 atomic_t *sw_ptr;
335 unsigned int sw0, sw1;
336
337 sw_ptr = &get_cpu_var(clock_sync_word);
338 sw0 = atomic_read(sw_ptr);
339 *clock = get_clock();
340 sw1 = atomic_read(sw_ptr);
bd119ee2 341 put_cpu_var(clock_sync_word);
d2fec595
MS
342 if (sw0 == sw1 && (sw0 & 0x80000000U))
343 /* Success: time is in sync. */
344 return 0;
345 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
346 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
347 return -ENOSYS;
348 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
349 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
350 return -EACCES;
351 return -EAGAIN;
352}
353EXPORT_SYMBOL(get_sync_clock);
354
355/*
356 * Make get_sync_clock return -EAGAIN.
357 */
358static void disable_sync_clock(void *dummy)
359{
360 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
361 /*
362 * Clear the in-sync bit 2^31. All get_sync_clock calls will
363 * fail until the sync bit is turned back on. In addition
364 * increase the "sequence" counter to avoid the race of an
365 * etr event and the complete recovery against get_sync_clock.
366 */
367 atomic_clear_mask(0x80000000, sw_ptr);
368 atomic_inc(sw_ptr);
369}
370
371/*
372 * Make get_sync_clock return 0 again.
373 * Needs to be called from a context disabled for preemption.
374 */
375static void enable_sync_clock(void)
376{
377 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
378 atomic_set_mask(0x80000000, sw_ptr);
379}
380
8283cb43
MS
381/*
382 * Function to check if the clock is in sync.
383 */
384static inline int check_sync_clock(void)
385{
386 atomic_t *sw_ptr;
387 int rc;
388
389 sw_ptr = &get_cpu_var(clock_sync_word);
390 rc = (atomic_read(sw_ptr) & 0x80000000U) != 0;
bd119ee2 391 put_cpu_var(clock_sync_word);
8283cb43
MS
392 return rc;
393}
394
750887de
HC
395/* Single threaded workqueue used for etr and stp sync events */
396static struct workqueue_struct *time_sync_wq;
397
398static void __init time_init_wq(void)
399{
179cb81a
HC
400 if (time_sync_wq)
401 return;
402 time_sync_wq = create_singlethread_workqueue("timesync");
750887de
HC
403}
404
d54853ef
MS
405/*
406 * External Time Reference (ETR) code.
407 */
408static int etr_port0_online;
409static int etr_port1_online;
d2fec595 410static int etr_steai_available;
d54853ef
MS
411
412static int __init early_parse_etr(char *p)
413{
414 if (strncmp(p, "off", 3) == 0)
415 etr_port0_online = etr_port1_online = 0;
416 else if (strncmp(p, "port0", 5) == 0)
417 etr_port0_online = 1;
418 else if (strncmp(p, "port1", 5) == 0)
419 etr_port1_online = 1;
420 else if (strncmp(p, "on", 2) == 0)
421 etr_port0_online = etr_port1_online = 1;
422 return 0;
423}
424early_param("etr", early_parse_etr);
425
426enum etr_event {
427 ETR_EVENT_PORT0_CHANGE,
428 ETR_EVENT_PORT1_CHANGE,
429 ETR_EVENT_PORT_ALERT,
430 ETR_EVENT_SYNC_CHECK,
431 ETR_EVENT_SWITCH_LOCAL,
432 ETR_EVENT_UPDATE,
433};
434
d54853ef
MS
435/*
436 * Valid bit combinations of the eacr register are (x = don't care):
437 * e0 e1 dp p0 p1 ea es sl
438 * 0 0 x 0 0 0 0 0 initial, disabled state
439 * 0 0 x 0 1 1 0 0 port 1 online
440 * 0 0 x 1 0 1 0 0 port 0 online
441 * 0 0 x 1 1 1 0 0 both ports online
442 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
443 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
444 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
445 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
446 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
447 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
448 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
449 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
450 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
451 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
452 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
453 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
454 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
455 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
456 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
457 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
458 */
459static struct etr_eacr etr_eacr;
460static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
461static struct etr_aib etr_port0;
462static int etr_port0_uptodate;
463static struct etr_aib etr_port1;
464static int etr_port1_uptodate;
465static unsigned long etr_events;
466static struct timer_list etr_timer;
d54853ef
MS
467
468static void etr_timeout(unsigned long dummy);
ecdcc023 469static void etr_work_fn(struct work_struct *work);
0b3016b7 470static DEFINE_MUTEX(etr_work_mutex);
ecdcc023 471static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 472
d54853ef
MS
473/*
474 * Reset ETR attachment.
475 */
476static void etr_reset(void)
477{
478 etr_eacr = (struct etr_eacr) {
479 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
480 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
481 .es = 0, .sl = 0 };
d2fec595 482 if (etr_setr(&etr_eacr) == 0) {
d54853ef 483 etr_tolec = get_clock();
d2fec595 484 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
8283cb43
MS
485 if (etr_port0_online && etr_port1_online)
486 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d2fec595 487 } else if (etr_port0_online || etr_port1_online) {
feab6501
MS
488 pr_warning("The real or virtual hardware system does "
489 "not provide an ETR interface\n");
d2fec595 490 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
491 }
492}
493
ecdcc023 494static int __init etr_init(void)
d54853ef
MS
495{
496 struct etr_aib aib;
497
d2fec595 498 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 499 return 0;
750887de 500 time_init_wq();
d54853ef
MS
501 /* Check if this machine has the steai instruction. */
502 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 503 etr_steai_available = 1;
d54853ef 504 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
505 if (etr_port0_online) {
506 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 507 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
508 }
509 if (etr_port1_online) {
510 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 511 queue_work(time_sync_wq, &etr_work);
d54853ef 512 }
ecdcc023 513 return 0;
d54853ef
MS
514}
515
ecdcc023
MS
516arch_initcall(etr_init);
517
d54853ef
MS
518/*
519 * Two sorts of ETR machine checks. The architecture reads:
520 * "When a machine-check niterruption occurs and if a switch-to-local or
521 * ETR-sync-check interrupt request is pending but disabled, this pending
522 * disabled interruption request is indicated and is cleared".
523 * Which means that we can get etr_switch_to_local events from the machine
524 * check handler although the interruption condition is disabled. Lovely..
525 */
526
527/*
528 * Switch to local machine check. This is called when the last usable
529 * ETR port goes inactive. After switch to local the clock is not in sync.
530 */
531void etr_switch_to_local(void)
532{
533 if (!etr_eacr.sl)
534 return;
8283cb43 535 disable_sync_clock(NULL);
33fea794
MS
536 if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) {
537 etr_eacr.es = etr_eacr.sl = 0;
538 etr_setr(&etr_eacr);
539 queue_work(time_sync_wq, &etr_work);
540 }
d54853ef
MS
541}
542
543/*
544 * ETR sync check machine check. This is called when the ETR OTE and the
545 * local clock OTE are farther apart than the ETR sync check tolerance.
546 * After a ETR sync check the clock is not in sync. The machine check
547 * is broadcasted to all cpus at the same time.
548 */
549void etr_sync_check(void)
550{
551 if (!etr_eacr.es)
552 return;
8283cb43 553 disable_sync_clock(NULL);
33fea794
MS
554 if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) {
555 etr_eacr.es = 0;
556 etr_setr(&etr_eacr);
557 queue_work(time_sync_wq, &etr_work);
558 }
d54853ef
MS
559}
560
561/*
d2fec595 562 * ETR timing alert. There are two causes:
d54853ef
MS
563 * 1) port state change, check the usability of the port
564 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
565 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
566 * or ETR-data word 4 (edf4) has changed.
567 */
d2fec595 568static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 569{
d54853ef
MS
570 if (intparm->pc0)
571 /* ETR port 0 state change. */
572 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
573 if (intparm->pc1)
574 /* ETR port 1 state change. */
575 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
576 if (intparm->eai)
577 /*
578 * ETR port alert on either port 0, 1 or both.
579 * Both ports are not up-to-date now.
580 */
581 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
750887de 582 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
583}
584
585static void etr_timeout(unsigned long dummy)
586{
587 set_bit(ETR_EVENT_UPDATE, &etr_events);
750887de 588 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
589}
590
591/*
592 * Check if the etr mode is pss.
593 */
594static inline int etr_mode_is_pps(struct etr_eacr eacr)
595{
596 return eacr.es && !eacr.sl;
597}
598
599/*
600 * Check if the etr mode is etr.
601 */
602static inline int etr_mode_is_etr(struct etr_eacr eacr)
603{
604 return eacr.es && eacr.sl;
605}
606
607/*
608 * Check if the port can be used for TOD synchronization.
609 * For PPS mode the port has to receive OTEs. For ETR mode
610 * the port has to receive OTEs, the ETR stepping bit has to
611 * be zero and the validity bits for data frame 1, 2, and 3
612 * have to be 1.
613 */
614static int etr_port_valid(struct etr_aib *aib, int port)
615{
616 unsigned int psc;
617
618 /* Check that this port is receiving OTEs. */
619 if (aib->tsp == 0)
620 return 0;
621
622 psc = port ? aib->esw.psc1 : aib->esw.psc0;
623 if (psc == etr_lpsc_pps_mode)
624 return 1;
625 if (psc == etr_lpsc_operational_step)
626 return !aib->esw.y && aib->slsw.v1 &&
627 aib->slsw.v2 && aib->slsw.v3;
628 return 0;
629}
630
631/*
632 * Check if two ports are on the same network.
633 */
634static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
635{
636 // FIXME: any other fields we have to compare?
637 return aib1->edf1.net_id == aib2->edf1.net_id;
638}
639
640/*
641 * Wrapper for etr_stei that converts physical port states
642 * to logical port states to be consistent with the output
643 * of stetr (see etr_psc vs. etr_lpsc).
644 */
645static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
646{
647 BUG_ON(etr_steai(aib, func) != 0);
648 /* Convert port state to logical port state. */
649 if (aib->esw.psc0 == 1)
650 aib->esw.psc0 = 2;
651 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
652 aib->esw.psc0 = 1;
653 if (aib->esw.psc1 == 1)
654 aib->esw.psc1 = 2;
655 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
656 aib->esw.psc1 = 1;
657}
658
659/*
660 * Check if the aib a2 is still connected to the same attachment as
661 * aib a1, the etv values differ by one and a2 is valid.
662 */
663static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
664{
665 int state_a1, state_a2;
666
667 /* Paranoia check: e0/e1 should better be the same. */
668 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
669 a1->esw.eacr.e1 != a2->esw.eacr.e1)
670 return 0;
671
672 /* Still connected to the same etr ? */
673 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
674 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
675 if (state_a1 == etr_lpsc_operational_step) {
676 if (state_a2 != etr_lpsc_operational_step ||
677 a1->edf1.net_id != a2->edf1.net_id ||
678 a1->edf1.etr_id != a2->edf1.etr_id ||
679 a1->edf1.etr_pn != a2->edf1.etr_pn)
680 return 0;
681 } else if (state_a2 != etr_lpsc_pps_mode)
682 return 0;
683
684 /* The ETV value of a2 needs to be ETV of a1 + 1. */
685 if (a1->edf2.etv + 1 != a2->edf2.etv)
686 return 0;
687
688 if (!etr_port_valid(a2, p))
689 return 0;
690
691 return 1;
692}
693
d2fec595 694struct clock_sync_data {
750887de 695 atomic_t cpus;
5a62b192
HC
696 int in_sync;
697 unsigned long long fixup_cc;
750887de
HC
698 int etr_port;
699 struct etr_aib *etr_aib;
d2fec595 700};
5a62b192 701
750887de 702static void clock_sync_cpu(struct clock_sync_data *sync)
d54853ef 703{
750887de 704 atomic_dec(&sync->cpus);
d2fec595 705 enable_sync_clock();
d54853ef
MS
706 /*
707 * This looks like a busy wait loop but it isn't. etr_sync_cpus
708 * is called on all other cpus while the TOD clocks is stopped.
709 * __udelay will stop the cpu on an enabled wait psw until the
710 * TOD is running again.
711 */
d2fec595 712 while (sync->in_sync == 0) {
d54853ef 713 __udelay(1);
6c732de2
HC
714 /*
715 * A different cpu changes *in_sync. Therefore use
716 * barrier() to force memory access.
717 */
718 barrier();
719 }
d2fec595 720 if (sync->in_sync != 1)
d54853ef 721 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 722 disable_sync_clock(NULL);
d54853ef
MS
723 /*
724 * This round of TOD syncing is done. Set the clock comparator
725 * to the next tick and let the processor continue.
726 */
d2fec595 727 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
728}
729
d54853ef 730/*
25985edc 731 * Sync the TOD clock using the port referred to by aibp. This port
d54853ef
MS
732 * has to be enabled and the other port has to be disabled. The
733 * last eacr update has to be more than 1.6 seconds in the past.
734 */
750887de 735static int etr_sync_clock(void *data)
d54853ef 736{
750887de 737 static int first;
5a62b192 738 unsigned long long clock, old_clock, delay, delta;
750887de
HC
739 struct clock_sync_data *etr_sync;
740 struct etr_aib *sync_port, *aib;
741 int port;
d54853ef
MS
742 int rc;
743
750887de 744 etr_sync = data;
d54853ef 745
750887de
HC
746 if (xchg(&first, 1) == 1) {
747 /* Slave */
748 clock_sync_cpu(etr_sync);
749 return 0;
750 }
751
752 /* Wait until all other cpus entered the sync function. */
753 while (atomic_read(&etr_sync->cpus) != 0)
754 cpu_relax();
755
756 port = etr_sync->etr_port;
757 aib = etr_sync->etr_aib;
758 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
d2fec595 759 enable_sync_clock();
d54853ef
MS
760
761 /* Set clock to next OTE. */
762 __ctl_set_bit(14, 21);
763 __ctl_set_bit(0, 29);
764 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 765 old_clock = get_clock();
d54853ef
MS
766 if (set_clock(clock) == 0) {
767 __udelay(1); /* Wait for the clock to start. */
768 __ctl_clear_bit(0, 29);
769 __ctl_clear_bit(14, 21);
770 etr_stetr(aib);
771 /* Adjust Linux timing variables. */
772 delay = (unsigned long long)
773 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 774 delta = adjust_time(old_clock, clock, delay);
750887de 775 etr_sync->fixup_cc = delta;
5a62b192 776 fixup_clock_comparator(delta);
d54853ef
MS
777 /* Verify that the clock is properly set. */
778 if (!etr_aib_follows(sync_port, aib, port)) {
779 /* Didn't work. */
d2fec595 780 disable_sync_clock(NULL);
750887de 781 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
782 rc = -EAGAIN;
783 } else {
750887de 784 etr_sync->in_sync = 1;
d54853ef
MS
785 rc = 0;
786 }
787 } else {
788 /* Could not set the clock ?!? */
789 __ctl_clear_bit(0, 29);
790 __ctl_clear_bit(14, 21);
d2fec595 791 disable_sync_clock(NULL);
750887de 792 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
793 rc = -EAGAIN;
794 }
750887de
HC
795 xchg(&first, 0);
796 return rc;
797}
798
799static int etr_sync_clock_stop(struct etr_aib *aib, int port)
800{
801 struct clock_sync_data etr_sync;
802 struct etr_aib *sync_port;
803 int follows;
804 int rc;
805
806 /* Check if the current aib is adjacent to the sync port aib. */
807 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
808 follows = etr_aib_follows(sync_port, aib, port);
809 memcpy(sync_port, aib, sizeof(*aib));
810 if (!follows)
811 return -EAGAIN;
812 memset(&etr_sync, 0, sizeof(etr_sync));
813 etr_sync.etr_aib = aib;
814 etr_sync.etr_port = port;
815 get_online_cpus();
816 atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
0f1959f5 817 rc = stop_machine(etr_sync_clock, &etr_sync, cpu_online_mask);
750887de 818 put_online_cpus();
d54853ef
MS
819 return rc;
820}
821
822/*
823 * Handle the immediate effects of the different events.
824 * The port change event is used for online/offline changes.
825 */
826static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
827{
828 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
829 eacr.es = 0;
830 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
831 eacr.es = eacr.sl = 0;
832 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
833 etr_port0_uptodate = etr_port1_uptodate = 0;
834
835 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
836 if (eacr.e0)
837 /*
838 * Port change of an enabled port. We have to
839 * assume that this can have caused an stepping
840 * port switch.
841 */
842 etr_tolec = get_clock();
843 eacr.p0 = etr_port0_online;
844 if (!eacr.p0)
845 eacr.e0 = 0;
846 etr_port0_uptodate = 0;
847 }
848 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
849 if (eacr.e1)
850 /*
851 * Port change of an enabled port. We have to
852 * assume that this can have caused an stepping
853 * port switch.
854 */
855 etr_tolec = get_clock();
856 eacr.p1 = etr_port1_online;
857 if (!eacr.p1)
858 eacr.e1 = 0;
859 etr_port1_uptodate = 0;
860 }
861 clear_bit(ETR_EVENT_UPDATE, &etr_events);
862 return eacr;
863}
864
865/*
866 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
867 * one of the ports needs an update.
868 */
869static void etr_set_tolec_timeout(unsigned long long now)
870{
871 unsigned long micros;
872
873 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
874 (!etr_eacr.p1 || etr_port1_uptodate))
875 return;
876 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
877 micros = (micros > 1600000) ? 0 : 1600000 - micros;
878 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
879}
880
881/*
882 * Set up a time that expires after 1/2 second.
883 */
884static void etr_set_sync_timeout(void)
885{
886 mod_timer(&etr_timer, jiffies + HZ/2);
887}
888
889/*
890 * Update the aib information for one or both ports.
891 */
892static struct etr_eacr etr_handle_update(struct etr_aib *aib,
893 struct etr_eacr eacr)
894{
895 /* With both ports disabled the aib information is useless. */
896 if (!eacr.e0 && !eacr.e1)
897 return eacr;
898
ecdcc023 899 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
900 if (aib->esw.q == 0) {
901 /* Information for port 0 stored. */
902 if (eacr.p0 && !etr_port0_uptodate) {
903 etr_port0 = *aib;
904 if (etr_port0_online)
905 etr_port0_uptodate = 1;
906 }
907 } else {
908 /* Information for port 1 stored. */
909 if (eacr.p1 && !etr_port1_uptodate) {
910 etr_port1 = *aib;
911 if (etr_port0_online)
912 etr_port1_uptodate = 1;
913 }
914 }
915
916 /*
917 * Do not try to get the alternate port aib if the clock
918 * is not in sync yet.
919 */
33fea794 920 if (!eacr.es || !check_sync_clock())
d54853ef
MS
921 return eacr;
922
923 /*
924 * If steai is available we can get the information about
925 * the other port immediately. If only stetr is available the
926 * data-port bit toggle has to be used.
927 */
d2fec595 928 if (etr_steai_available) {
d54853ef
MS
929 if (eacr.p0 && !etr_port0_uptodate) {
930 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
931 etr_port0_uptodate = 1;
932 }
933 if (eacr.p1 && !etr_port1_uptodate) {
934 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
935 etr_port1_uptodate = 1;
936 }
937 } else {
938 /*
939 * One port was updated above, if the other
940 * port is not uptodate toggle dp bit.
941 */
942 if ((eacr.p0 && !etr_port0_uptodate) ||
943 (eacr.p1 && !etr_port1_uptodate))
944 eacr.dp ^= 1;
945 else
946 eacr.dp = 0;
947 }
948 return eacr;
949}
950
951/*
952 * Write new etr control register if it differs from the current one.
953 * Return 1 if etr_tolec has been updated as well.
954 */
955static void etr_update_eacr(struct etr_eacr eacr)
956{
957 int dp_changed;
958
959 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
960 /* No change, return. */
961 return;
962 /*
963 * The disable of an active port of the change of the data port
964 * bit can/will cause a change in the data port.
965 */
966 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
967 (etr_eacr.dp ^ eacr.dp) != 0;
968 etr_eacr = eacr;
969 etr_setr(&etr_eacr);
970 if (dp_changed)
971 etr_tolec = get_clock();
972}
973
974/*
750887de 975 * ETR work. In this function you'll find the main logic. In
d54853ef
MS
976 * particular this is the only function that calls etr_update_eacr(),
977 * it "controls" the etr control register.
978 */
ecdcc023 979static void etr_work_fn(struct work_struct *work)
d54853ef
MS
980{
981 unsigned long long now;
982 struct etr_eacr eacr;
983 struct etr_aib aib;
984 int sync_port;
985
0b3016b7
MS
986 /* prevent multiple execution. */
987 mutex_lock(&etr_work_mutex);
988
d54853ef
MS
989 /* Create working copy of etr_eacr. */
990 eacr = etr_eacr;
991
992 /* Check for the different events and their immediate effects. */
993 eacr = etr_handle_events(eacr);
994
995 /* Check if ETR is supposed to be active. */
996 eacr.ea = eacr.p0 || eacr.p1;
997 if (!eacr.ea) {
998 /* Both ports offline. Reset everything. */
999 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 1000 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
1001 del_timer_sync(&etr_timer);
1002 etr_update_eacr(eacr);
0b3016b7 1003 goto out_unlock;
d54853ef
MS
1004 }
1005
1006 /* Store aib to get the current ETR status word. */
1007 BUG_ON(etr_stetr(&aib) != 0);
1008 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
1009 now = get_clock();
1010
1011 /*
1012 * Update the port information if the last stepping port change
1013 * or data port change is older than 1.6 seconds.
1014 */
1015 if (now >= etr_tolec + (1600000 << 12))
1016 eacr = etr_handle_update(&aib, eacr);
1017
1018 /*
25985edc 1019 * Select ports to enable. The preferred synchronization mode is PPS.
d54853ef
MS
1020 * If a port can be enabled depends on a number of things:
1021 * 1) The port needs to be online and uptodate. A port is not
1022 * disabled just because it is not uptodate, but it is only
1023 * enabled if it is uptodate.
1024 * 2) The port needs to have the same mode (pps / etr).
1025 * 3) The port needs to be usable -> etr_port_valid() == 1
1026 * 4) To enable the second port the clock needs to be in sync.
1027 * 5) If both ports are useable and are ETR ports, the network id
1028 * has to be the same.
1029 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
1030 */
1031 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
1032 eacr.sl = 0;
1033 eacr.e0 = 1;
1034 if (!etr_mode_is_pps(etr_eacr))
1035 eacr.es = 0;
1036 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
1037 eacr.e1 = 0;
1038 // FIXME: uptodate checks ?
1039 else if (etr_port0_uptodate && etr_port1_uptodate)
1040 eacr.e1 = 1;
1041 sync_port = (etr_port0_uptodate &&
1042 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1043 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
1044 eacr.sl = 0;
1045 eacr.e0 = 0;
1046 eacr.e1 = 1;
1047 if (!etr_mode_is_pps(etr_eacr))
1048 eacr.es = 0;
1049 sync_port = (etr_port1_uptodate &&
1050 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1051 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
1052 eacr.sl = 1;
1053 eacr.e0 = 1;
1054 if (!etr_mode_is_etr(etr_eacr))
1055 eacr.es = 0;
1056 if (!eacr.es || !eacr.p1 ||
1057 aib.esw.psc1 != etr_lpsc_operational_alt)
1058 eacr.e1 = 0;
1059 else if (etr_port0_uptodate && etr_port1_uptodate &&
1060 etr_compare_network(&etr_port0, &etr_port1))
1061 eacr.e1 = 1;
1062 sync_port = (etr_port0_uptodate &&
1063 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1064 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
1065 eacr.sl = 1;
1066 eacr.e0 = 0;
1067 eacr.e1 = 1;
1068 if (!etr_mode_is_etr(etr_eacr))
1069 eacr.es = 0;
1070 sync_port = (etr_port1_uptodate &&
1071 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1072 } else {
1073 /* Both ports not usable. */
1074 eacr.es = eacr.sl = 0;
1075 sync_port = -1;
d54853ef
MS
1076 }
1077
1078 /*
1079 * If the clock is in sync just update the eacr and return.
1080 * If there is no valid sync port wait for a port update.
1081 */
33fea794 1082 if ((eacr.es && check_sync_clock()) || sync_port < 0) {
d54853ef
MS
1083 etr_update_eacr(eacr);
1084 etr_set_tolec_timeout(now);
0b3016b7 1085 goto out_unlock;
d54853ef
MS
1086 }
1087
1088 /*
1089 * Prepare control register for clock syncing
1090 * (reset data port bit, set sync check control.
1091 */
1092 eacr.dp = 0;
1093 eacr.es = 1;
1094
1095 /*
1096 * Update eacr and try to synchronize the clock. If the update
1097 * of eacr caused a stepping port switch (or if we have to
25985edc 1098 * assume that a stepping port switch has occurred) or the
d54853ef
MS
1099 * clock syncing failed, reset the sync check control bit
1100 * and set up a timer to try again after 0.5 seconds
1101 */
1102 etr_update_eacr(eacr);
1103 if (now < etr_tolec + (1600000 << 12) ||
750887de 1104 etr_sync_clock_stop(&aib, sync_port) != 0) {
d54853ef
MS
1105 /* Sync failed. Try again in 1/2 second. */
1106 eacr.es = 0;
1107 etr_update_eacr(eacr);
1108 etr_set_sync_timeout();
1109 } else
1110 etr_set_tolec_timeout(now);
0b3016b7
MS
1111out_unlock:
1112 mutex_unlock(&etr_work_mutex);
d54853ef
MS
1113}
1114
1115/*
1116 * Sysfs interface functions
1117 */
1118static struct sysdev_class etr_sysclass = {
af5ca3f4 1119 .name = "etr",
d54853ef
MS
1120};
1121
1122static struct sys_device etr_port0_dev = {
1123 .id = 0,
1124 .cls = &etr_sysclass,
1125};
1126
1127static struct sys_device etr_port1_dev = {
1128 .id = 1,
1129 .cls = &etr_sysclass,
1130};
1131
1132/*
1133 * ETR class attributes
1134 */
c9be0a36
AK
1135static ssize_t etr_stepping_port_show(struct sysdev_class *class,
1136 struct sysdev_class_attribute *attr,
1137 char *buf)
d54853ef
MS
1138{
1139 return sprintf(buf, "%i\n", etr_port0.esw.p);
1140}
1141
1142static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1143
c9be0a36
AK
1144static ssize_t etr_stepping_mode_show(struct sysdev_class *class,
1145 struct sysdev_class_attribute *attr,
1146 char *buf)
d54853ef
MS
1147{
1148 char *mode_str;
1149
1150 if (etr_mode_is_pps(etr_eacr))
1151 mode_str = "pps";
1152 else if (etr_mode_is_etr(etr_eacr))
1153 mode_str = "etr";
1154 else
1155 mode_str = "local";
1156 return sprintf(buf, "%s\n", mode_str);
1157}
1158
1159static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1160
1161/*
1162 * ETR port attributes
1163 */
1164static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1165{
1166 if (dev == &etr_port0_dev)
1167 return etr_port0_online ? &etr_port0 : NULL;
1168 else
1169 return etr_port1_online ? &etr_port1 : NULL;
1170}
1171
4a0b2b4d
AK
1172static ssize_t etr_online_show(struct sys_device *dev,
1173 struct sysdev_attribute *attr,
1174 char *buf)
d54853ef
MS
1175{
1176 unsigned int online;
1177
1178 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1179 return sprintf(buf, "%i\n", online);
1180}
1181
1182static ssize_t etr_online_store(struct sys_device *dev,
4a0b2b4d
AK
1183 struct sysdev_attribute *attr,
1184 const char *buf, size_t count)
d54853ef
MS
1185{
1186 unsigned int value;
1187
1188 value = simple_strtoul(buf, NULL, 0);
1189 if (value != 0 && value != 1)
1190 return -EINVAL;
d2fec595
MS
1191 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1192 return -EOPNOTSUPP;
8283cb43 1193 mutex_lock(&clock_sync_mutex);
d54853ef
MS
1194 if (dev == &etr_port0_dev) {
1195 if (etr_port0_online == value)
8283cb43 1196 goto out; /* Nothing to do. */
d54853ef 1197 etr_port0_online = value;
8283cb43
MS
1198 if (etr_port0_online && etr_port1_online)
1199 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1200 else
1201 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1202 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 1203 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
1204 } else {
1205 if (etr_port1_online == value)
8283cb43 1206 goto out; /* Nothing to do. */
d54853ef 1207 etr_port1_online = value;
8283cb43
MS
1208 if (etr_port0_online && etr_port1_online)
1209 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1210 else
1211 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1212 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 1213 queue_work(time_sync_wq, &etr_work);
d54853ef 1214 }
8283cb43
MS
1215out:
1216 mutex_unlock(&clock_sync_mutex);
d54853ef
MS
1217 return count;
1218}
1219
1220static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1221
4a0b2b4d
AK
1222static ssize_t etr_stepping_control_show(struct sys_device *dev,
1223 struct sysdev_attribute *attr,
1224 char *buf)
d54853ef
MS
1225{
1226 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1227 etr_eacr.e0 : etr_eacr.e1);
1228}
1229
1230static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1231
4a0b2b4d
AK
1232static ssize_t etr_mode_code_show(struct sys_device *dev,
1233 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1234{
1235 if (!etr_port0_online && !etr_port1_online)
1236 /* Status word is not uptodate if both ports are offline. */
1237 return -ENODATA;
1238 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1239 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1240}
1241
1242static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1243
4a0b2b4d
AK
1244static ssize_t etr_untuned_show(struct sys_device *dev,
1245 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1246{
1247 struct etr_aib *aib = etr_aib_from_dev(dev);
1248
1249 if (!aib || !aib->slsw.v1)
1250 return -ENODATA;
1251 return sprintf(buf, "%i\n", aib->edf1.u);
1252}
1253
1254static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1255
4a0b2b4d
AK
1256static ssize_t etr_network_id_show(struct sys_device *dev,
1257 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1258{
1259 struct etr_aib *aib = etr_aib_from_dev(dev);
1260
1261 if (!aib || !aib->slsw.v1)
1262 return -ENODATA;
1263 return sprintf(buf, "%i\n", aib->edf1.net_id);
1264}
1265
1266static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1267
4a0b2b4d
AK
1268static ssize_t etr_id_show(struct sys_device *dev,
1269 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1270{
1271 struct etr_aib *aib = etr_aib_from_dev(dev);
1272
1273 if (!aib || !aib->slsw.v1)
1274 return -ENODATA;
1275 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1276}
1277
1278static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1279
4a0b2b4d
AK
1280static ssize_t etr_port_number_show(struct sys_device *dev,
1281 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1282{
1283 struct etr_aib *aib = etr_aib_from_dev(dev);
1284
1285 if (!aib || !aib->slsw.v1)
1286 return -ENODATA;
1287 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1288}
1289
1290static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1291
4a0b2b4d
AK
1292static ssize_t etr_coupled_show(struct sys_device *dev,
1293 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1294{
1295 struct etr_aib *aib = etr_aib_from_dev(dev);
1296
1297 if (!aib || !aib->slsw.v3)
1298 return -ENODATA;
1299 return sprintf(buf, "%i\n", aib->edf3.c);
1300}
1301
1302static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1303
4a0b2b4d
AK
1304static ssize_t etr_local_time_show(struct sys_device *dev,
1305 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1306{
1307 struct etr_aib *aib = etr_aib_from_dev(dev);
1308
1309 if (!aib || !aib->slsw.v3)
1310 return -ENODATA;
1311 return sprintf(buf, "%i\n", aib->edf3.blto);
1312}
1313
1314static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1315
4a0b2b4d
AK
1316static ssize_t etr_utc_offset_show(struct sys_device *dev,
1317 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1318{
1319 struct etr_aib *aib = etr_aib_from_dev(dev);
1320
1321 if (!aib || !aib->slsw.v3)
1322 return -ENODATA;
1323 return sprintf(buf, "%i\n", aib->edf3.buo);
1324}
1325
1326static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1327
1328static struct sysdev_attribute *etr_port_attributes[] = {
1329 &attr_online,
1330 &attr_stepping_control,
1331 &attr_state_code,
1332 &attr_untuned,
1333 &attr_network,
1334 &attr_id,
1335 &attr_port,
1336 &attr_coupled,
1337 &attr_local_time,
1338 &attr_utc_offset,
1339 NULL
1340};
1341
1342static int __init etr_register_port(struct sys_device *dev)
1343{
1344 struct sysdev_attribute **attr;
1345 int rc;
1346
1347 rc = sysdev_register(dev);
1348 if (rc)
1349 goto out;
1350 for (attr = etr_port_attributes; *attr; attr++) {
1351 rc = sysdev_create_file(dev, *attr);
1352 if (rc)
1353 goto out_unreg;
1354 }
1355 return 0;
1356out_unreg:
1357 for (; attr >= etr_port_attributes; attr--)
1358 sysdev_remove_file(dev, *attr);
1359 sysdev_unregister(dev);
1360out:
1361 return rc;
1362}
1363
1364static void __init etr_unregister_port(struct sys_device *dev)
1365{
1366 struct sysdev_attribute **attr;
1367
1368 for (attr = etr_port_attributes; *attr; attr++)
1369 sysdev_remove_file(dev, *attr);
1370 sysdev_unregister(dev);
1371}
1372
1373static int __init etr_init_sysfs(void)
1374{
1375 int rc;
1376
1377 rc = sysdev_class_register(&etr_sysclass);
1378 if (rc)
1379 goto out;
1380 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1381 if (rc)
1382 goto out_unreg_class;
1383 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1384 if (rc)
1385 goto out_remove_stepping_port;
1386 rc = etr_register_port(&etr_port0_dev);
1387 if (rc)
1388 goto out_remove_stepping_mode;
1389 rc = etr_register_port(&etr_port1_dev);
1390 if (rc)
1391 goto out_remove_port0;
1392 return 0;
1393
1394out_remove_port0:
1395 etr_unregister_port(&etr_port0_dev);
1396out_remove_stepping_mode:
1397 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1398out_remove_stepping_port:
1399 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1400out_unreg_class:
1401 sysdev_class_unregister(&etr_sysclass);
1402out:
1403 return rc;
1da177e4
LT
1404}
1405
d54853ef 1406device_initcall(etr_init_sysfs);
d2fec595
MS
1407
1408/*
1409 * Server Time Protocol (STP) code.
1410 */
1411static int stp_online;
1412static struct stp_sstpi stp_info;
1413static void *stp_page;
1414
1415static void stp_work_fn(struct work_struct *work);
0b3016b7 1416static DEFINE_MUTEX(stp_work_mutex);
d2fec595 1417static DECLARE_WORK(stp_work, stp_work_fn);
04362301 1418static struct timer_list stp_timer;
d2fec595
MS
1419
1420static int __init early_parse_stp(char *p)
1421{
1422 if (strncmp(p, "off", 3) == 0)
1423 stp_online = 0;
1424 else if (strncmp(p, "on", 2) == 0)
1425 stp_online = 1;
1426 return 0;
1427}
1428early_param("stp", early_parse_stp);
1429
1430/*
1431 * Reset STP attachment.
1432 */
8f847003 1433static void __init stp_reset(void)
d2fec595
MS
1434{
1435 int rc;
1436
d7d1104f 1437 stp_page = (void *) get_zeroed_page(GFP_ATOMIC);
d2fec595 1438 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
4a672cfa 1439 if (rc == 0)
d2fec595
MS
1440 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1441 else if (stp_online) {
feab6501
MS
1442 pr_warning("The real or virtual hardware system does "
1443 "not provide an STP interface\n");
d7d1104f 1444 free_page((unsigned long) stp_page);
d2fec595
MS
1445 stp_page = NULL;
1446 stp_online = 0;
1447 }
1448}
1449
04362301
MS
1450static void stp_timeout(unsigned long dummy)
1451{
1452 queue_work(time_sync_wq, &stp_work);
1453}
1454
d2fec595
MS
1455static int __init stp_init(void)
1456{
750887de
HC
1457 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1458 return 0;
04362301 1459 setup_timer(&stp_timer, stp_timeout, 0UL);
750887de
HC
1460 time_init_wq();
1461 if (!stp_online)
1462 return 0;
1463 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1464 return 0;
1465}
1466
1467arch_initcall(stp_init);
1468
1469/*
1470 * STP timing alert. There are three causes:
1471 * 1) timing status change
1472 * 2) link availability change
1473 * 3) time control parameter change
1474 * In all three cases we are only interested in the clock source state.
1475 * If a STP clock source is now available use it.
1476 */
1477static void stp_timing_alert(struct stp_irq_parm *intparm)
1478{
1479 if (intparm->tsc || intparm->lac || intparm->tcpc)
750887de 1480 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1481}
1482
1483/*
1484 * STP sync check machine check. This is called when the timing state
1485 * changes from the synchronized state to the unsynchronized state.
1486 * After a STP sync check the clock is not in sync. The machine check
1487 * is broadcasted to all cpus at the same time.
1488 */
1489void stp_sync_check(void)
1490{
d2fec595 1491 disable_sync_clock(NULL);
750887de 1492 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1493}
1494
1495/*
1496 * STP island condition machine check. This is called when an attached
1497 * server attempts to communicate over an STP link and the servers
1498 * have matching CTN ids and have a valid stratum-1 configuration
1499 * but the configurations do not match.
1500 */
1501void stp_island_check(void)
1502{
d2fec595 1503 disable_sync_clock(NULL);
750887de 1504 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1505}
1506
750887de
HC
1507
1508static int stp_sync_clock(void *data)
d2fec595 1509{
750887de 1510 static int first;
d2fec595 1511 unsigned long long old_clock, delta;
750887de 1512 struct clock_sync_data *stp_sync;
d2fec595
MS
1513 int rc;
1514
750887de 1515 stp_sync = data;
d2fec595 1516
750887de
HC
1517 if (xchg(&first, 1) == 1) {
1518 /* Slave */
1519 clock_sync_cpu(stp_sync);
1520 return 0;
1521 }
d2fec595 1522
750887de
HC
1523 /* Wait until all other cpus entered the sync function. */
1524 while (atomic_read(&stp_sync->cpus) != 0)
1525 cpu_relax();
d2fec595 1526
d2fec595
MS
1527 enable_sync_clock();
1528
d2fec595
MS
1529 rc = 0;
1530 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1531 stp_info.todoff[2] || stp_info.todoff[3] ||
1532 stp_info.tmd != 2) {
1533 old_clock = get_clock();
1534 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1535 if (rc == 0) {
1536 delta = adjust_time(old_clock, get_clock(), 0);
1537 fixup_clock_comparator(delta);
1538 rc = chsc_sstpi(stp_page, &stp_info,
1539 sizeof(struct stp_sstpi));
1540 if (rc == 0 && stp_info.tmd != 2)
1541 rc = -EAGAIN;
1542 }
1543 }
1544 if (rc) {
1545 disable_sync_clock(NULL);
750887de 1546 stp_sync->in_sync = -EAGAIN;
d2fec595 1547 } else
750887de
HC
1548 stp_sync->in_sync = 1;
1549 xchg(&first, 0);
1550 return 0;
1551}
d2fec595 1552
750887de
HC
1553/*
1554 * STP work. Check for the STP state and take over the clock
1555 * synchronization if the STP clock source is usable.
1556 */
1557static void stp_work_fn(struct work_struct *work)
1558{
1559 struct clock_sync_data stp_sync;
1560 int rc;
1561
0b3016b7
MS
1562 /* prevent multiple execution. */
1563 mutex_lock(&stp_work_mutex);
1564
750887de
HC
1565 if (!stp_online) {
1566 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
04362301 1567 del_timer_sync(&stp_timer);
0b3016b7 1568 goto out_unlock;
750887de
HC
1569 }
1570
1571 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1572 if (rc)
0b3016b7 1573 goto out_unlock;
750887de
HC
1574
1575 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1576 if (rc || stp_info.c == 0)
0b3016b7 1577 goto out_unlock;
750887de 1578
8283cb43
MS
1579 /* Skip synchronization if the clock is already in sync. */
1580 if (check_sync_clock())
1581 goto out_unlock;
1582
750887de
HC
1583 memset(&stp_sync, 0, sizeof(stp_sync));
1584 get_online_cpus();
1585 atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
0f1959f5 1586 stop_machine(stp_sync_clock, &stp_sync, cpu_online_mask);
750887de 1587 put_online_cpus();
0b3016b7 1588
04362301
MS
1589 if (!check_sync_clock())
1590 /*
1591 * There is a usable clock but the synchonization failed.
1592 * Retry after a second.
1593 */
1594 mod_timer(&stp_timer, jiffies + HZ);
1595
0b3016b7
MS
1596out_unlock:
1597 mutex_unlock(&stp_work_mutex);
d2fec595
MS
1598}
1599
1600/*
1601 * STP class sysfs interface functions
1602 */
1603static struct sysdev_class stp_sysclass = {
1604 .name = "stp",
1605};
1606
c9be0a36
AK
1607static ssize_t stp_ctn_id_show(struct sysdev_class *class,
1608 struct sysdev_class_attribute *attr,
1609 char *buf)
d2fec595
MS
1610{
1611 if (!stp_online)
1612 return -ENODATA;
1613 return sprintf(buf, "%016llx\n",
1614 *(unsigned long long *) stp_info.ctnid);
1615}
1616
1617static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
1618
c9be0a36
AK
1619static ssize_t stp_ctn_type_show(struct sysdev_class *class,
1620 struct sysdev_class_attribute *attr,
1621 char *buf)
d2fec595
MS
1622{
1623 if (!stp_online)
1624 return -ENODATA;
1625 return sprintf(buf, "%i\n", stp_info.ctn);
1626}
1627
1628static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
1629
c9be0a36
AK
1630static ssize_t stp_dst_offset_show(struct sysdev_class *class,
1631 struct sysdev_class_attribute *attr,
1632 char *buf)
d2fec595
MS
1633{
1634 if (!stp_online || !(stp_info.vbits & 0x2000))
1635 return -ENODATA;
1636 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1637}
1638
1639static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
1640
c9be0a36
AK
1641static ssize_t stp_leap_seconds_show(struct sysdev_class *class,
1642 struct sysdev_class_attribute *attr,
1643 char *buf)
d2fec595
MS
1644{
1645 if (!stp_online || !(stp_info.vbits & 0x8000))
1646 return -ENODATA;
1647 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1648}
1649
1650static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
1651
c9be0a36
AK
1652static ssize_t stp_stratum_show(struct sysdev_class *class,
1653 struct sysdev_class_attribute *attr,
1654 char *buf)
d2fec595
MS
1655{
1656 if (!stp_online)
1657 return -ENODATA;
1658 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1659}
1660
1661static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
1662
c9be0a36
AK
1663static ssize_t stp_time_offset_show(struct sysdev_class *class,
1664 struct sysdev_class_attribute *attr,
1665 char *buf)
d2fec595
MS
1666{
1667 if (!stp_online || !(stp_info.vbits & 0x0800))
1668 return -ENODATA;
1669 return sprintf(buf, "%i\n", (int) stp_info.tto);
1670}
1671
1672static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
1673
c9be0a36
AK
1674static ssize_t stp_time_zone_offset_show(struct sysdev_class *class,
1675 struct sysdev_class_attribute *attr,
1676 char *buf)
d2fec595
MS
1677{
1678 if (!stp_online || !(stp_info.vbits & 0x4000))
1679 return -ENODATA;
1680 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1681}
1682
1683static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
1684 stp_time_zone_offset_show, NULL);
1685
c9be0a36
AK
1686static ssize_t stp_timing_mode_show(struct sysdev_class *class,
1687 struct sysdev_class_attribute *attr,
1688 char *buf)
d2fec595
MS
1689{
1690 if (!stp_online)
1691 return -ENODATA;
1692 return sprintf(buf, "%i\n", stp_info.tmd);
1693}
1694
1695static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
1696
c9be0a36
AK
1697static ssize_t stp_timing_state_show(struct sysdev_class *class,
1698 struct sysdev_class_attribute *attr,
1699 char *buf)
d2fec595
MS
1700{
1701 if (!stp_online)
1702 return -ENODATA;
1703 return sprintf(buf, "%i\n", stp_info.tst);
1704}
1705
1706static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
1707
c9be0a36
AK
1708static ssize_t stp_online_show(struct sysdev_class *class,
1709 struct sysdev_class_attribute *attr,
1710 char *buf)
d2fec595
MS
1711{
1712 return sprintf(buf, "%i\n", stp_online);
1713}
1714
1715static ssize_t stp_online_store(struct sysdev_class *class,
c9be0a36 1716 struct sysdev_class_attribute *attr,
d2fec595
MS
1717 const char *buf, size_t count)
1718{
1719 unsigned int value;
1720
1721 value = simple_strtoul(buf, NULL, 0);
1722 if (value != 0 && value != 1)
1723 return -EINVAL;
1724 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1725 return -EOPNOTSUPP;
8283cb43 1726 mutex_lock(&clock_sync_mutex);
d2fec595 1727 stp_online = value;
8283cb43
MS
1728 if (stp_online)
1729 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1730 else
1731 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
750887de 1732 queue_work(time_sync_wq, &stp_work);
8283cb43 1733 mutex_unlock(&clock_sync_mutex);
d2fec595
MS
1734 return count;
1735}
1736
1737/*
1738 * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
1739 * stp/online but attr_online already exists in this file ..
1740 */
1741static struct sysdev_class_attribute attr_stp_online = {
1742 .attr = { .name = "online", .mode = 0600 },
1743 .show = stp_online_show,
1744 .store = stp_online_store,
1745};
1746
1747static struct sysdev_class_attribute *stp_attributes[] = {
1748 &attr_ctn_id,
1749 &attr_ctn_type,
1750 &attr_dst_offset,
1751 &attr_leap_seconds,
1752 &attr_stp_online,
1753 &attr_stratum,
1754 &attr_time_offset,
1755 &attr_time_zone_offset,
1756 &attr_timing_mode,
1757 &attr_timing_state,
1758 NULL
1759};
1760
1761static int __init stp_init_sysfs(void)
1762{
1763 struct sysdev_class_attribute **attr;
1764 int rc;
1765
1766 rc = sysdev_class_register(&stp_sysclass);
1767 if (rc)
1768 goto out;
1769 for (attr = stp_attributes; *attr; attr++) {
1770 rc = sysdev_class_create_file(&stp_sysclass, *attr);
1771 if (rc)
1772 goto out_unreg;
1773 }
1774 return 0;
1775out_unreg:
1776 for (; attr >= stp_attributes; attr--)
1777 sysdev_class_remove_file(&stp_sysclass, *attr);
1778 sysdev_class_unregister(&stp_sysclass);
1779out:
1780 return rc;
1781}
1782
1783device_initcall(stp_init_sysfs);
This page took 0.600733 seconds and 5 git commands to generate.