[S390] correct ktime to tod clock comparator conversion
[deliverable/linux.git] / arch / s390 / kernel / time.c
CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
feab6501
MS
15#define KMSG_COMPONENT "time"
16#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
17
052ff461 18#include <linux/kernel_stat.h>
1da177e4
LT
19#include <linux/errno.h>
20#include <linux/module.h>
21#include <linux/sched.h>
22#include <linux/kernel.h>
23#include <linux/param.h>
24#include <linux/string.h>
25#include <linux/mm.h>
26#include <linux/interrupt.h>
750887de
HC
27#include <linux/cpu.h>
28#include <linux/stop_machine.h>
1da177e4 29#include <linux/time.h>
3fbacffb 30#include <linux/device.h>
1da177e4
LT
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/smp.h>
34#include <linux/types.h>
35#include <linux/profile.h>
36#include <linux/timex.h>
37#include <linux/notifier.h>
dc64bef5 38#include <linux/clocksource.h>
5a62b192 39#include <linux/clockchips.h>
5a0e3ad6 40#include <linux/gfp.h>
860dba45 41#include <linux/kprobes.h>
1da177e4
LT
42#include <asm/uaccess.h>
43#include <asm/delay.h>
1da177e4 44#include <asm/div64.h>
b020632e 45#include <asm/vdso.h>
1da177e4 46#include <asm/irq.h>
5a489b98 47#include <asm/irq_regs.h>
1da177e4 48#include <asm/timer.h>
d54853ef 49#include <asm/etr.h>
a806170e 50#include <asm/cio.h>
638ad34a 51#include "entry.h"
1da177e4
LT
52
53/* change this if you have some constant time drift */
54#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
55#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
56
b6112ccb 57u64 sched_clock_base_cc = -1; /* Force to data section. */
05e7ff7d 58EXPORT_SYMBOL_GPL(sched_clock_base_cc);
b6112ccb 59
5a62b192 60static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 61
1da177e4
LT
62/*
63 * Scheduler clock - returns current time in nanosec units.
64 */
860dba45 65unsigned long long notrace __kprobes sched_clock(void)
1da177e4 66{
05e7ff7d 67 return (get_clock_monotonic() * 125) >> 9;
1da177e4
LT
68}
69
32f65f27
JG
70/*
71 * Monotonic_clock - returns # of nanoseconds passed since time_init()
72 */
73unsigned long long monotonic_clock(void)
74{
75 return sched_clock();
76}
77EXPORT_SYMBOL(monotonic_clock);
78
b1e2ba8d 79void tod_to_timeval(__u64 todval, struct timespec *xt)
1da177e4
LT
80{
81 unsigned long long sec;
82
83 sec = todval >> 12;
84 do_div(sec, 1000000);
b1e2ba8d 85 xt->tv_sec = sec;
1da177e4 86 todval -= (sec * 1000000) << 12;
b1e2ba8d 87 xt->tv_nsec = ((todval * 1000) >> 12);
1da177e4 88}
b592e89a 89EXPORT_SYMBOL(tod_to_timeval);
1da177e4 90
5a62b192 91void clock_comparator_work(void)
1da177e4 92{
5a62b192 93 struct clock_event_device *cd;
1da177e4 94
5a62b192
HC
95 S390_lowcore.clock_comparator = -1ULL;
96 set_clock_comparator(S390_lowcore.clock_comparator);
97 cd = &__get_cpu_var(comparators);
98 cd->event_handler(cd);
1da177e4
LT
99}
100
1da177e4 101/*
5a62b192 102 * Fixup the clock comparator.
1da177e4 103 */
5a62b192 104static void fixup_clock_comparator(unsigned long long delta)
1da177e4 105{
5a62b192
HC
106 /* If nobody is waiting there's nothing to fix. */
107 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 108 return;
5a62b192
HC
109 S390_lowcore.clock_comparator += delta;
110 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
111}
112
4f37a68c 113static int s390_next_ktime(ktime_t expires,
5a62b192 114 struct clock_event_device *evt)
1da177e4 115{
cf1eb40f 116 struct timespec ts;
e35f95b3 117 u64 nsecs;
4f37a68c 118
cf1eb40f
MS
119 ts.tv_sec = ts.tv_nsec = 0;
120 monotonic_to_bootbased(&ts);
121 nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
4f37a68c 122 do_div(nsecs, 125);
cf1eb40f 123 S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
5a62b192
HC
124 set_clock_comparator(S390_lowcore.clock_comparator);
125 return 0;
1da177e4
LT
126}
127
5a62b192
HC
128static void s390_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
1da177e4 130{
d54853ef
MS
131}
132
133/*
134 * Set up lowcore and control register of the current cpu to
135 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
136 */
137void init_cpu_timer(void)
138{
5a62b192
HC
139 struct clock_event_device *cd;
140 int cpu;
141
142 S390_lowcore.clock_comparator = -1ULL;
143 set_clock_comparator(S390_lowcore.clock_comparator);
144
145 cpu = smp_processor_id();
146 cd = &per_cpu(comparators, cpu);
147 cd->name = "comparator";
4f37a68c
MS
148 cd->features = CLOCK_EVT_FEAT_ONESHOT |
149 CLOCK_EVT_FEAT_KTIME;
5a62b192
HC
150 cd->mult = 16777;
151 cd->shift = 12;
152 cd->min_delta_ns = 1;
153 cd->max_delta_ns = LONG_MAX;
154 cd->rating = 400;
320ab2b0 155 cd->cpumask = cpumask_of(cpu);
4f37a68c 156 cd->set_next_ktime = s390_next_ktime;
5a62b192
HC
157 cd->set_mode = s390_set_mode;
158
159 clockevents_register_device(cd);
d54853ef
MS
160
161 /* Enable clock comparator timer interrupt. */
162 __ctl_set_bit(0,11);
163
d2fec595 164 /* Always allow the timing alert external interrupt. */
d54853ef
MS
165 __ctl_set_bit(0, 4);
166}
167
f6649a7e
MS
168static void clock_comparator_interrupt(unsigned int ext_int_code,
169 unsigned int param32,
170 unsigned long param64)
d54853ef 171{
052ff461 172 kstat_cpu(smp_processor_id()).irqs[EXTINT_CLK]++;
d3d238c7
HC
173 if (S390_lowcore.clock_comparator == -1ULL)
174 set_clock_comparator(S390_lowcore.clock_comparator);
d54853ef
MS
175}
176
d2fec595
MS
177static void etr_timing_alert(struct etr_irq_parm *);
178static void stp_timing_alert(struct stp_irq_parm *);
179
f6649a7e
MS
180static void timing_alert_interrupt(unsigned int ext_int_code,
181 unsigned int param32, unsigned long param64)
d2fec595 182{
052ff461 183 kstat_cpu(smp_processor_id()).irqs[EXTINT_TLA]++;
f6649a7e
MS
184 if (param32 & 0x00c40000)
185 etr_timing_alert((struct etr_irq_parm *) &param32);
186 if (param32 & 0x00038000)
187 stp_timing_alert((struct stp_irq_parm *) &param32);
d2fec595
MS
188}
189
d54853ef 190static void etr_reset(void);
d2fec595 191static void stp_reset(void);
d54853ef 192
d4f587c6 193void read_persistent_clock(struct timespec *ts)
d54853ef 194{
d4f587c6 195 tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, ts);
1da177e4 196}
d54853ef 197
23970e38
MS
198void read_boot_clock(struct timespec *ts)
199{
200 tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts);
1da177e4
LT
201}
202
8e19608e 203static cycle_t read_tod_clock(struct clocksource *cs)
dc64bef5
MS
204{
205 return get_clock();
206}
207
208static struct clocksource clocksource_tod = {
209 .name = "tod",
d2cb0e6e 210 .rating = 400,
dc64bef5
MS
211 .read = read_tod_clock,
212 .mask = -1ULL,
213 .mult = 1000,
214 .shift = 12,
cc02d809 215 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
216};
217
f1b82746
MS
218struct clocksource * __init clocksource_default_clock(void)
219{
220 return &clocksource_tod;
221}
dc64bef5 222
7615856e
JS
223void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
224 struct clocksource *clock, u32 mult)
b020632e
MS
225{
226 if (clock != &clocksource_tod)
227 return;
228
229 /* Make userspace gettimeofday spin until we're done. */
230 ++vdso_data->tb_update_count;
231 smp_wmb();
232 vdso_data->xtime_tod_stamp = clock->cycle_last;
b1e2ba8d
JS
233 vdso_data->xtime_clock_sec = wall_time->tv_sec;
234 vdso_data->xtime_clock_nsec = wall_time->tv_nsec;
7615856e
JS
235 vdso_data->wtom_clock_sec = wtm->tv_sec;
236 vdso_data->wtom_clock_nsec = wtm->tv_nsec;
157a1a27 237 vdso_data->ntp_mult = mult;
b020632e
MS
238 smp_wmb();
239 ++vdso_data->tb_update_count;
240}
241
242extern struct timezone sys_tz;
243
244void update_vsyscall_tz(void)
245{
246 /* Make userspace gettimeofday spin until we're done. */
247 ++vdso_data->tb_update_count;
248 smp_wmb();
249 vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
250 vdso_data->tz_dsttime = sys_tz.tz_dsttime;
251 smp_wmb();
252 ++vdso_data->tb_update_count;
253}
254
1da177e4
LT
255/*
256 * Initialize the TOD clock and the CPU timer of
257 * the boot cpu.
258 */
259void __init time_init(void)
260{
b6112ccb
MS
261 /* Reset time synchronization interfaces. */
262 etr_reset();
263 stp_reset();
1da177e4 264
1da177e4 265 /* request the clock comparator external interrupt */
d7d1104f 266 if (register_external_interrupt(0x1004, clock_comparator_interrupt))
1da177e4
LT
267 panic("Couldn't request external interrupt 0x1004");
268
d2fec595 269 /* request the timing alert external interrupt */
d7d1104f 270 if (register_external_interrupt(0x1406, timing_alert_interrupt))
d54853ef
MS
271 panic("Couldn't request external interrupt 0x1406");
272
ab96e798
MS
273 if (clocksource_register(&clocksource_tod) != 0)
274 panic("Could not register TOD clock source");
275
d54853ef
MS
276 /* Enable TOD clock interrupts on the boot cpu. */
277 init_cpu_timer();
ab96e798 278
c185b783 279 /* Enable cpu timer interrupts on the boot cpu. */
1da177e4 280 vtime_init();
d54853ef
MS
281}
282
d2fec595
MS
283/*
284 * The time is "clock". old is what we think the time is.
285 * Adjust the value by a multiple of jiffies and add the delta to ntp.
286 * "delay" is an approximation how long the synchronization took. If
287 * the time correction is positive, then "delay" is subtracted from
288 * the time difference and only the remaining part is passed to ntp.
289 */
290static unsigned long long adjust_time(unsigned long long old,
291 unsigned long long clock,
292 unsigned long long delay)
293{
294 unsigned long long delta, ticks;
295 struct timex adjust;
296
297 if (clock > old) {
298 /* It is later than we thought. */
299 delta = ticks = clock - old;
300 delta = ticks = (delta < delay) ? 0 : delta - delay;
301 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
302 adjust.offset = ticks * (1000000 / HZ);
303 } else {
304 /* It is earlier than we thought. */
305 delta = ticks = old - clock;
306 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
307 delta = -delta;
308 adjust.offset = -ticks * (1000000 / HZ);
309 }
8107d829 310 sched_clock_base_cc += delta;
d2fec595 311 if (adjust.offset != 0) {
feab6501
MS
312 pr_notice("The ETR interface has adjusted the clock "
313 "by %li microseconds\n", adjust.offset);
d2fec595
MS
314 adjust.modes = ADJ_OFFSET_SINGLESHOT;
315 do_adjtimex(&adjust);
316 }
317 return delta;
318}
319
320static DEFINE_PER_CPU(atomic_t, clock_sync_word);
8283cb43 321static DEFINE_MUTEX(clock_sync_mutex);
d2fec595
MS
322static unsigned long clock_sync_flags;
323
324#define CLOCK_SYNC_HAS_ETR 0
325#define CLOCK_SYNC_HAS_STP 1
326#define CLOCK_SYNC_ETR 2
327#define CLOCK_SYNC_STP 3
328
329/*
330 * The synchronous get_clock function. It will write the current clock
331 * value to the clock pointer and return 0 if the clock is in sync with
332 * the external time source. If the clock mode is local it will return
333 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
334 * reference.
335 */
336int get_sync_clock(unsigned long long *clock)
337{
338 atomic_t *sw_ptr;
339 unsigned int sw0, sw1;
340
341 sw_ptr = &get_cpu_var(clock_sync_word);
342 sw0 = atomic_read(sw_ptr);
343 *clock = get_clock();
344 sw1 = atomic_read(sw_ptr);
bd119ee2 345 put_cpu_var(clock_sync_word);
d2fec595
MS
346 if (sw0 == sw1 && (sw0 & 0x80000000U))
347 /* Success: time is in sync. */
348 return 0;
349 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
350 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
351 return -ENOSYS;
352 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
353 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
354 return -EACCES;
355 return -EAGAIN;
356}
357EXPORT_SYMBOL(get_sync_clock);
358
359/*
360 * Make get_sync_clock return -EAGAIN.
361 */
362static void disable_sync_clock(void *dummy)
363{
364 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
365 /*
366 * Clear the in-sync bit 2^31. All get_sync_clock calls will
367 * fail until the sync bit is turned back on. In addition
368 * increase the "sequence" counter to avoid the race of an
369 * etr event and the complete recovery against get_sync_clock.
370 */
371 atomic_clear_mask(0x80000000, sw_ptr);
372 atomic_inc(sw_ptr);
373}
374
375/*
376 * Make get_sync_clock return 0 again.
377 * Needs to be called from a context disabled for preemption.
378 */
379static void enable_sync_clock(void)
380{
381 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
382 atomic_set_mask(0x80000000, sw_ptr);
383}
384
8283cb43
MS
385/*
386 * Function to check if the clock is in sync.
387 */
388static inline int check_sync_clock(void)
389{
390 atomic_t *sw_ptr;
391 int rc;
392
393 sw_ptr = &get_cpu_var(clock_sync_word);
394 rc = (atomic_read(sw_ptr) & 0x80000000U) != 0;
bd119ee2 395 put_cpu_var(clock_sync_word);
8283cb43
MS
396 return rc;
397}
398
750887de
HC
399/* Single threaded workqueue used for etr and stp sync events */
400static struct workqueue_struct *time_sync_wq;
401
402static void __init time_init_wq(void)
403{
179cb81a
HC
404 if (time_sync_wq)
405 return;
406 time_sync_wq = create_singlethread_workqueue("timesync");
750887de
HC
407}
408
d54853ef
MS
409/*
410 * External Time Reference (ETR) code.
411 */
412static int etr_port0_online;
413static int etr_port1_online;
d2fec595 414static int etr_steai_available;
d54853ef
MS
415
416static int __init early_parse_etr(char *p)
417{
418 if (strncmp(p, "off", 3) == 0)
419 etr_port0_online = etr_port1_online = 0;
420 else if (strncmp(p, "port0", 5) == 0)
421 etr_port0_online = 1;
422 else if (strncmp(p, "port1", 5) == 0)
423 etr_port1_online = 1;
424 else if (strncmp(p, "on", 2) == 0)
425 etr_port0_online = etr_port1_online = 1;
426 return 0;
427}
428early_param("etr", early_parse_etr);
429
430enum etr_event {
431 ETR_EVENT_PORT0_CHANGE,
432 ETR_EVENT_PORT1_CHANGE,
433 ETR_EVENT_PORT_ALERT,
434 ETR_EVENT_SYNC_CHECK,
435 ETR_EVENT_SWITCH_LOCAL,
436 ETR_EVENT_UPDATE,
437};
438
d54853ef
MS
439/*
440 * Valid bit combinations of the eacr register are (x = don't care):
441 * e0 e1 dp p0 p1 ea es sl
442 * 0 0 x 0 0 0 0 0 initial, disabled state
443 * 0 0 x 0 1 1 0 0 port 1 online
444 * 0 0 x 1 0 1 0 0 port 0 online
445 * 0 0 x 1 1 1 0 0 both ports online
446 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
447 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
448 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
449 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
450 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
451 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
452 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
453 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
454 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
455 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
456 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
457 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
458 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
459 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
460 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
461 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
462 */
463static struct etr_eacr etr_eacr;
464static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
465static struct etr_aib etr_port0;
466static int etr_port0_uptodate;
467static struct etr_aib etr_port1;
468static int etr_port1_uptodate;
469static unsigned long etr_events;
470static struct timer_list etr_timer;
d54853ef
MS
471
472static void etr_timeout(unsigned long dummy);
ecdcc023 473static void etr_work_fn(struct work_struct *work);
0b3016b7 474static DEFINE_MUTEX(etr_work_mutex);
ecdcc023 475static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 476
d54853ef
MS
477/*
478 * Reset ETR attachment.
479 */
480static void etr_reset(void)
481{
482 etr_eacr = (struct etr_eacr) {
483 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
484 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
485 .es = 0, .sl = 0 };
d2fec595 486 if (etr_setr(&etr_eacr) == 0) {
d54853ef 487 etr_tolec = get_clock();
d2fec595 488 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
8283cb43
MS
489 if (etr_port0_online && etr_port1_online)
490 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d2fec595 491 } else if (etr_port0_online || etr_port1_online) {
feab6501
MS
492 pr_warning("The real or virtual hardware system does "
493 "not provide an ETR interface\n");
d2fec595 494 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
495 }
496}
497
ecdcc023 498static int __init etr_init(void)
d54853ef
MS
499{
500 struct etr_aib aib;
501
d2fec595 502 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 503 return 0;
750887de 504 time_init_wq();
d54853ef
MS
505 /* Check if this machine has the steai instruction. */
506 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 507 etr_steai_available = 1;
d54853ef 508 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
509 if (etr_port0_online) {
510 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 511 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
512 }
513 if (etr_port1_online) {
514 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 515 queue_work(time_sync_wq, &etr_work);
d54853ef 516 }
ecdcc023 517 return 0;
d54853ef
MS
518}
519
ecdcc023
MS
520arch_initcall(etr_init);
521
d54853ef
MS
522/*
523 * Two sorts of ETR machine checks. The architecture reads:
524 * "When a machine-check niterruption occurs and if a switch-to-local or
525 * ETR-sync-check interrupt request is pending but disabled, this pending
526 * disabled interruption request is indicated and is cleared".
527 * Which means that we can get etr_switch_to_local events from the machine
528 * check handler although the interruption condition is disabled. Lovely..
529 */
530
531/*
532 * Switch to local machine check. This is called when the last usable
533 * ETR port goes inactive. After switch to local the clock is not in sync.
534 */
535void etr_switch_to_local(void)
536{
537 if (!etr_eacr.sl)
538 return;
8283cb43 539 disable_sync_clock(NULL);
33fea794
MS
540 if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) {
541 etr_eacr.es = etr_eacr.sl = 0;
542 etr_setr(&etr_eacr);
543 queue_work(time_sync_wq, &etr_work);
544 }
d54853ef
MS
545}
546
547/*
548 * ETR sync check machine check. This is called when the ETR OTE and the
549 * local clock OTE are farther apart than the ETR sync check tolerance.
550 * After a ETR sync check the clock is not in sync. The machine check
551 * is broadcasted to all cpus at the same time.
552 */
553void etr_sync_check(void)
554{
555 if (!etr_eacr.es)
556 return;
8283cb43 557 disable_sync_clock(NULL);
33fea794
MS
558 if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) {
559 etr_eacr.es = 0;
560 etr_setr(&etr_eacr);
561 queue_work(time_sync_wq, &etr_work);
562 }
d54853ef
MS
563}
564
565/*
d2fec595 566 * ETR timing alert. There are two causes:
d54853ef
MS
567 * 1) port state change, check the usability of the port
568 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
569 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
570 * or ETR-data word 4 (edf4) has changed.
571 */
d2fec595 572static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 573{
d54853ef
MS
574 if (intparm->pc0)
575 /* ETR port 0 state change. */
576 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
577 if (intparm->pc1)
578 /* ETR port 1 state change. */
579 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
580 if (intparm->eai)
581 /*
582 * ETR port alert on either port 0, 1 or both.
583 * Both ports are not up-to-date now.
584 */
585 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
750887de 586 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
587}
588
589static void etr_timeout(unsigned long dummy)
590{
591 set_bit(ETR_EVENT_UPDATE, &etr_events);
750887de 592 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
593}
594
595/*
596 * Check if the etr mode is pss.
597 */
598static inline int etr_mode_is_pps(struct etr_eacr eacr)
599{
600 return eacr.es && !eacr.sl;
601}
602
603/*
604 * Check if the etr mode is etr.
605 */
606static inline int etr_mode_is_etr(struct etr_eacr eacr)
607{
608 return eacr.es && eacr.sl;
609}
610
611/*
612 * Check if the port can be used for TOD synchronization.
613 * For PPS mode the port has to receive OTEs. For ETR mode
614 * the port has to receive OTEs, the ETR stepping bit has to
615 * be zero and the validity bits for data frame 1, 2, and 3
616 * have to be 1.
617 */
618static int etr_port_valid(struct etr_aib *aib, int port)
619{
620 unsigned int psc;
621
622 /* Check that this port is receiving OTEs. */
623 if (aib->tsp == 0)
624 return 0;
625
626 psc = port ? aib->esw.psc1 : aib->esw.psc0;
627 if (psc == etr_lpsc_pps_mode)
628 return 1;
629 if (psc == etr_lpsc_operational_step)
630 return !aib->esw.y && aib->slsw.v1 &&
631 aib->slsw.v2 && aib->slsw.v3;
632 return 0;
633}
634
635/*
636 * Check if two ports are on the same network.
637 */
638static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
639{
640 // FIXME: any other fields we have to compare?
641 return aib1->edf1.net_id == aib2->edf1.net_id;
642}
643
644/*
645 * Wrapper for etr_stei that converts physical port states
646 * to logical port states to be consistent with the output
647 * of stetr (see etr_psc vs. etr_lpsc).
648 */
649static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
650{
651 BUG_ON(etr_steai(aib, func) != 0);
652 /* Convert port state to logical port state. */
653 if (aib->esw.psc0 == 1)
654 aib->esw.psc0 = 2;
655 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
656 aib->esw.psc0 = 1;
657 if (aib->esw.psc1 == 1)
658 aib->esw.psc1 = 2;
659 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
660 aib->esw.psc1 = 1;
661}
662
663/*
664 * Check if the aib a2 is still connected to the same attachment as
665 * aib a1, the etv values differ by one and a2 is valid.
666 */
667static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
668{
669 int state_a1, state_a2;
670
671 /* Paranoia check: e0/e1 should better be the same. */
672 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
673 a1->esw.eacr.e1 != a2->esw.eacr.e1)
674 return 0;
675
676 /* Still connected to the same etr ? */
677 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
678 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
679 if (state_a1 == etr_lpsc_operational_step) {
680 if (state_a2 != etr_lpsc_operational_step ||
681 a1->edf1.net_id != a2->edf1.net_id ||
682 a1->edf1.etr_id != a2->edf1.etr_id ||
683 a1->edf1.etr_pn != a2->edf1.etr_pn)
684 return 0;
685 } else if (state_a2 != etr_lpsc_pps_mode)
686 return 0;
687
688 /* The ETV value of a2 needs to be ETV of a1 + 1. */
689 if (a1->edf2.etv + 1 != a2->edf2.etv)
690 return 0;
691
692 if (!etr_port_valid(a2, p))
693 return 0;
694
695 return 1;
696}
697
d2fec595 698struct clock_sync_data {
750887de 699 atomic_t cpus;
5a62b192
HC
700 int in_sync;
701 unsigned long long fixup_cc;
750887de
HC
702 int etr_port;
703 struct etr_aib *etr_aib;
d2fec595 704};
5a62b192 705
750887de 706static void clock_sync_cpu(struct clock_sync_data *sync)
d54853ef 707{
750887de 708 atomic_dec(&sync->cpus);
d2fec595 709 enable_sync_clock();
d54853ef
MS
710 /*
711 * This looks like a busy wait loop but it isn't. etr_sync_cpus
712 * is called on all other cpus while the TOD clocks is stopped.
713 * __udelay will stop the cpu on an enabled wait psw until the
714 * TOD is running again.
715 */
d2fec595 716 while (sync->in_sync == 0) {
d54853ef 717 __udelay(1);
6c732de2
HC
718 /*
719 * A different cpu changes *in_sync. Therefore use
720 * barrier() to force memory access.
721 */
722 barrier();
723 }
d2fec595 724 if (sync->in_sync != 1)
d54853ef 725 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 726 disable_sync_clock(NULL);
d54853ef
MS
727 /*
728 * This round of TOD syncing is done. Set the clock comparator
729 * to the next tick and let the processor continue.
730 */
d2fec595 731 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
732}
733
d54853ef 734/*
25985edc 735 * Sync the TOD clock using the port referred to by aibp. This port
d54853ef
MS
736 * has to be enabled and the other port has to be disabled. The
737 * last eacr update has to be more than 1.6 seconds in the past.
738 */
750887de 739static int etr_sync_clock(void *data)
d54853ef 740{
750887de 741 static int first;
5a62b192 742 unsigned long long clock, old_clock, delay, delta;
750887de
HC
743 struct clock_sync_data *etr_sync;
744 struct etr_aib *sync_port, *aib;
745 int port;
d54853ef
MS
746 int rc;
747
750887de 748 etr_sync = data;
d54853ef 749
750887de
HC
750 if (xchg(&first, 1) == 1) {
751 /* Slave */
752 clock_sync_cpu(etr_sync);
753 return 0;
754 }
755
756 /* Wait until all other cpus entered the sync function. */
757 while (atomic_read(&etr_sync->cpus) != 0)
758 cpu_relax();
759
760 port = etr_sync->etr_port;
761 aib = etr_sync->etr_aib;
762 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
d2fec595 763 enable_sync_clock();
d54853ef
MS
764
765 /* Set clock to next OTE. */
766 __ctl_set_bit(14, 21);
767 __ctl_set_bit(0, 29);
768 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 769 old_clock = get_clock();
d54853ef
MS
770 if (set_clock(clock) == 0) {
771 __udelay(1); /* Wait for the clock to start. */
772 __ctl_clear_bit(0, 29);
773 __ctl_clear_bit(14, 21);
774 etr_stetr(aib);
775 /* Adjust Linux timing variables. */
776 delay = (unsigned long long)
777 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 778 delta = adjust_time(old_clock, clock, delay);
750887de 779 etr_sync->fixup_cc = delta;
5a62b192 780 fixup_clock_comparator(delta);
d54853ef
MS
781 /* Verify that the clock is properly set. */
782 if (!etr_aib_follows(sync_port, aib, port)) {
783 /* Didn't work. */
d2fec595 784 disable_sync_clock(NULL);
750887de 785 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
786 rc = -EAGAIN;
787 } else {
750887de 788 etr_sync->in_sync = 1;
d54853ef
MS
789 rc = 0;
790 }
791 } else {
792 /* Could not set the clock ?!? */
793 __ctl_clear_bit(0, 29);
794 __ctl_clear_bit(14, 21);
d2fec595 795 disable_sync_clock(NULL);
750887de 796 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
797 rc = -EAGAIN;
798 }
750887de
HC
799 xchg(&first, 0);
800 return rc;
801}
802
803static int etr_sync_clock_stop(struct etr_aib *aib, int port)
804{
805 struct clock_sync_data etr_sync;
806 struct etr_aib *sync_port;
807 int follows;
808 int rc;
809
810 /* Check if the current aib is adjacent to the sync port aib. */
811 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
812 follows = etr_aib_follows(sync_port, aib, port);
813 memcpy(sync_port, aib, sizeof(*aib));
814 if (!follows)
815 return -EAGAIN;
816 memset(&etr_sync, 0, sizeof(etr_sync));
817 etr_sync.etr_aib = aib;
818 etr_sync.etr_port = port;
819 get_online_cpus();
820 atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
0f1959f5 821 rc = stop_machine(etr_sync_clock, &etr_sync, cpu_online_mask);
750887de 822 put_online_cpus();
d54853ef
MS
823 return rc;
824}
825
826/*
827 * Handle the immediate effects of the different events.
828 * The port change event is used for online/offline changes.
829 */
830static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
831{
832 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
833 eacr.es = 0;
834 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
835 eacr.es = eacr.sl = 0;
836 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
837 etr_port0_uptodate = etr_port1_uptodate = 0;
838
839 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
840 if (eacr.e0)
841 /*
842 * Port change of an enabled port. We have to
843 * assume that this can have caused an stepping
844 * port switch.
845 */
846 etr_tolec = get_clock();
847 eacr.p0 = etr_port0_online;
848 if (!eacr.p0)
849 eacr.e0 = 0;
850 etr_port0_uptodate = 0;
851 }
852 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
853 if (eacr.e1)
854 /*
855 * Port change of an enabled port. We have to
856 * assume that this can have caused an stepping
857 * port switch.
858 */
859 etr_tolec = get_clock();
860 eacr.p1 = etr_port1_online;
861 if (!eacr.p1)
862 eacr.e1 = 0;
863 etr_port1_uptodate = 0;
864 }
865 clear_bit(ETR_EVENT_UPDATE, &etr_events);
866 return eacr;
867}
868
869/*
870 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
871 * one of the ports needs an update.
872 */
873static void etr_set_tolec_timeout(unsigned long long now)
874{
875 unsigned long micros;
876
877 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
878 (!etr_eacr.p1 || etr_port1_uptodate))
879 return;
880 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
881 micros = (micros > 1600000) ? 0 : 1600000 - micros;
882 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
883}
884
885/*
886 * Set up a time that expires after 1/2 second.
887 */
888static void etr_set_sync_timeout(void)
889{
890 mod_timer(&etr_timer, jiffies + HZ/2);
891}
892
893/*
894 * Update the aib information for one or both ports.
895 */
896static struct etr_eacr etr_handle_update(struct etr_aib *aib,
897 struct etr_eacr eacr)
898{
899 /* With both ports disabled the aib information is useless. */
900 if (!eacr.e0 && !eacr.e1)
901 return eacr;
902
ecdcc023 903 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
904 if (aib->esw.q == 0) {
905 /* Information for port 0 stored. */
906 if (eacr.p0 && !etr_port0_uptodate) {
907 etr_port0 = *aib;
908 if (etr_port0_online)
909 etr_port0_uptodate = 1;
910 }
911 } else {
912 /* Information for port 1 stored. */
913 if (eacr.p1 && !etr_port1_uptodate) {
914 etr_port1 = *aib;
915 if (etr_port0_online)
916 etr_port1_uptodate = 1;
917 }
918 }
919
920 /*
921 * Do not try to get the alternate port aib if the clock
922 * is not in sync yet.
923 */
33fea794 924 if (!eacr.es || !check_sync_clock())
d54853ef
MS
925 return eacr;
926
927 /*
928 * If steai is available we can get the information about
929 * the other port immediately. If only stetr is available the
930 * data-port bit toggle has to be used.
931 */
d2fec595 932 if (etr_steai_available) {
d54853ef
MS
933 if (eacr.p0 && !etr_port0_uptodate) {
934 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
935 etr_port0_uptodate = 1;
936 }
937 if (eacr.p1 && !etr_port1_uptodate) {
938 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
939 etr_port1_uptodate = 1;
940 }
941 } else {
942 /*
943 * One port was updated above, if the other
944 * port is not uptodate toggle dp bit.
945 */
946 if ((eacr.p0 && !etr_port0_uptodate) ||
947 (eacr.p1 && !etr_port1_uptodate))
948 eacr.dp ^= 1;
949 else
950 eacr.dp = 0;
951 }
952 return eacr;
953}
954
955/*
956 * Write new etr control register if it differs from the current one.
957 * Return 1 if etr_tolec has been updated as well.
958 */
959static void etr_update_eacr(struct etr_eacr eacr)
960{
961 int dp_changed;
962
963 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
964 /* No change, return. */
965 return;
966 /*
967 * The disable of an active port of the change of the data port
968 * bit can/will cause a change in the data port.
969 */
970 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
971 (etr_eacr.dp ^ eacr.dp) != 0;
972 etr_eacr = eacr;
973 etr_setr(&etr_eacr);
974 if (dp_changed)
975 etr_tolec = get_clock();
976}
977
978/*
750887de 979 * ETR work. In this function you'll find the main logic. In
d54853ef
MS
980 * particular this is the only function that calls etr_update_eacr(),
981 * it "controls" the etr control register.
982 */
ecdcc023 983static void etr_work_fn(struct work_struct *work)
d54853ef
MS
984{
985 unsigned long long now;
986 struct etr_eacr eacr;
987 struct etr_aib aib;
988 int sync_port;
989
0b3016b7
MS
990 /* prevent multiple execution. */
991 mutex_lock(&etr_work_mutex);
992
d54853ef
MS
993 /* Create working copy of etr_eacr. */
994 eacr = etr_eacr;
995
996 /* Check for the different events and their immediate effects. */
997 eacr = etr_handle_events(eacr);
998
999 /* Check if ETR is supposed to be active. */
1000 eacr.ea = eacr.p0 || eacr.p1;
1001 if (!eacr.ea) {
1002 /* Both ports offline. Reset everything. */
1003 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 1004 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
1005 del_timer_sync(&etr_timer);
1006 etr_update_eacr(eacr);
0b3016b7 1007 goto out_unlock;
d54853ef
MS
1008 }
1009
1010 /* Store aib to get the current ETR status word. */
1011 BUG_ON(etr_stetr(&aib) != 0);
1012 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
1013 now = get_clock();
1014
1015 /*
1016 * Update the port information if the last stepping port change
1017 * or data port change is older than 1.6 seconds.
1018 */
1019 if (now >= etr_tolec + (1600000 << 12))
1020 eacr = etr_handle_update(&aib, eacr);
1021
1022 /*
25985edc 1023 * Select ports to enable. The preferred synchronization mode is PPS.
d54853ef
MS
1024 * If a port can be enabled depends on a number of things:
1025 * 1) The port needs to be online and uptodate. A port is not
1026 * disabled just because it is not uptodate, but it is only
1027 * enabled if it is uptodate.
1028 * 2) The port needs to have the same mode (pps / etr).
1029 * 3) The port needs to be usable -> etr_port_valid() == 1
1030 * 4) To enable the second port the clock needs to be in sync.
1031 * 5) If both ports are useable and are ETR ports, the network id
1032 * has to be the same.
1033 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
1034 */
1035 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
1036 eacr.sl = 0;
1037 eacr.e0 = 1;
1038 if (!etr_mode_is_pps(etr_eacr))
1039 eacr.es = 0;
1040 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
1041 eacr.e1 = 0;
1042 // FIXME: uptodate checks ?
1043 else if (etr_port0_uptodate && etr_port1_uptodate)
1044 eacr.e1 = 1;
1045 sync_port = (etr_port0_uptodate &&
1046 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1047 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
1048 eacr.sl = 0;
1049 eacr.e0 = 0;
1050 eacr.e1 = 1;
1051 if (!etr_mode_is_pps(etr_eacr))
1052 eacr.es = 0;
1053 sync_port = (etr_port1_uptodate &&
1054 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1055 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
1056 eacr.sl = 1;
1057 eacr.e0 = 1;
1058 if (!etr_mode_is_etr(etr_eacr))
1059 eacr.es = 0;
1060 if (!eacr.es || !eacr.p1 ||
1061 aib.esw.psc1 != etr_lpsc_operational_alt)
1062 eacr.e1 = 0;
1063 else if (etr_port0_uptodate && etr_port1_uptodate &&
1064 etr_compare_network(&etr_port0, &etr_port1))
1065 eacr.e1 = 1;
1066 sync_port = (etr_port0_uptodate &&
1067 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1068 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
1069 eacr.sl = 1;
1070 eacr.e0 = 0;
1071 eacr.e1 = 1;
1072 if (!etr_mode_is_etr(etr_eacr))
1073 eacr.es = 0;
1074 sync_port = (etr_port1_uptodate &&
1075 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1076 } else {
1077 /* Both ports not usable. */
1078 eacr.es = eacr.sl = 0;
1079 sync_port = -1;
d54853ef
MS
1080 }
1081
1082 /*
1083 * If the clock is in sync just update the eacr and return.
1084 * If there is no valid sync port wait for a port update.
1085 */
33fea794 1086 if ((eacr.es && check_sync_clock()) || sync_port < 0) {
d54853ef
MS
1087 etr_update_eacr(eacr);
1088 etr_set_tolec_timeout(now);
0b3016b7 1089 goto out_unlock;
d54853ef
MS
1090 }
1091
1092 /*
1093 * Prepare control register for clock syncing
1094 * (reset data port bit, set sync check control.
1095 */
1096 eacr.dp = 0;
1097 eacr.es = 1;
1098
1099 /*
1100 * Update eacr and try to synchronize the clock. If the update
1101 * of eacr caused a stepping port switch (or if we have to
25985edc 1102 * assume that a stepping port switch has occurred) or the
d54853ef
MS
1103 * clock syncing failed, reset the sync check control bit
1104 * and set up a timer to try again after 0.5 seconds
1105 */
1106 etr_update_eacr(eacr);
1107 if (now < etr_tolec + (1600000 << 12) ||
750887de 1108 etr_sync_clock_stop(&aib, sync_port) != 0) {
d54853ef
MS
1109 /* Sync failed. Try again in 1/2 second. */
1110 eacr.es = 0;
1111 etr_update_eacr(eacr);
1112 etr_set_sync_timeout();
1113 } else
1114 etr_set_tolec_timeout(now);
0b3016b7
MS
1115out_unlock:
1116 mutex_unlock(&etr_work_mutex);
d54853ef
MS
1117}
1118
1119/*
1120 * Sysfs interface functions
1121 */
3fbacffb
KS
1122static struct bus_type etr_subsys = {
1123 .name = "etr",
1124 .dev_name = "etr",
d54853ef
MS
1125};
1126
3fbacffb 1127static struct device etr_port0_dev = {
d54853ef 1128 .id = 0,
3fbacffb 1129 .bus = &etr_subsys,
d54853ef
MS
1130};
1131
3fbacffb 1132static struct device etr_port1_dev = {
d54853ef 1133 .id = 1,
3fbacffb 1134 .bus = &etr_subsys,
d54853ef
MS
1135};
1136
1137/*
3fbacffb 1138 * ETR subsys attributes
d54853ef 1139 */
3fbacffb
KS
1140static ssize_t etr_stepping_port_show(struct device *dev,
1141 struct device_attribute *attr,
c9be0a36 1142 char *buf)
d54853ef
MS
1143{
1144 return sprintf(buf, "%i\n", etr_port0.esw.p);
1145}
1146
3fbacffb 1147static DEVICE_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
d54853ef 1148
3fbacffb
KS
1149static ssize_t etr_stepping_mode_show(struct device *dev,
1150 struct device_attribute *attr,
c9be0a36 1151 char *buf)
d54853ef
MS
1152{
1153 char *mode_str;
1154
1155 if (etr_mode_is_pps(etr_eacr))
1156 mode_str = "pps";
1157 else if (etr_mode_is_etr(etr_eacr))
1158 mode_str = "etr";
1159 else
1160 mode_str = "local";
1161 return sprintf(buf, "%s\n", mode_str);
1162}
1163
3fbacffb 1164static DEVICE_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
d54853ef
MS
1165
1166/*
1167 * ETR port attributes
1168 */
3fbacffb 1169static inline struct etr_aib *etr_aib_from_dev(struct device *dev)
d54853ef
MS
1170{
1171 if (dev == &etr_port0_dev)
1172 return etr_port0_online ? &etr_port0 : NULL;
1173 else
1174 return etr_port1_online ? &etr_port1 : NULL;
1175}
1176
3fbacffb
KS
1177static ssize_t etr_online_show(struct device *dev,
1178 struct device_attribute *attr,
4a0b2b4d 1179 char *buf)
d54853ef
MS
1180{
1181 unsigned int online;
1182
1183 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1184 return sprintf(buf, "%i\n", online);
1185}
1186
3fbacffb
KS
1187static ssize_t etr_online_store(struct device *dev,
1188 struct device_attribute *attr,
4a0b2b4d 1189 const char *buf, size_t count)
d54853ef
MS
1190{
1191 unsigned int value;
1192
1193 value = simple_strtoul(buf, NULL, 0);
1194 if (value != 0 && value != 1)
1195 return -EINVAL;
d2fec595
MS
1196 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1197 return -EOPNOTSUPP;
8283cb43 1198 mutex_lock(&clock_sync_mutex);
d54853ef
MS
1199 if (dev == &etr_port0_dev) {
1200 if (etr_port0_online == value)
8283cb43 1201 goto out; /* Nothing to do. */
d54853ef 1202 etr_port0_online = value;
8283cb43
MS
1203 if (etr_port0_online && etr_port1_online)
1204 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1205 else
1206 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1207 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 1208 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
1209 } else {
1210 if (etr_port1_online == value)
8283cb43 1211 goto out; /* Nothing to do. */
d54853ef 1212 etr_port1_online = value;
8283cb43
MS
1213 if (etr_port0_online && etr_port1_online)
1214 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1215 else
1216 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1217 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 1218 queue_work(time_sync_wq, &etr_work);
d54853ef 1219 }
8283cb43
MS
1220out:
1221 mutex_unlock(&clock_sync_mutex);
d54853ef
MS
1222 return count;
1223}
1224
3fbacffb 1225static DEVICE_ATTR(online, 0600, etr_online_show, etr_online_store);
d54853ef 1226
3fbacffb
KS
1227static ssize_t etr_stepping_control_show(struct device *dev,
1228 struct device_attribute *attr,
4a0b2b4d 1229 char *buf)
d54853ef
MS
1230{
1231 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1232 etr_eacr.e0 : etr_eacr.e1);
1233}
1234
3fbacffb 1235static DEVICE_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
d54853ef 1236
3fbacffb
KS
1237static ssize_t etr_mode_code_show(struct device *dev,
1238 struct device_attribute *attr, char *buf)
d54853ef
MS
1239{
1240 if (!etr_port0_online && !etr_port1_online)
1241 /* Status word is not uptodate if both ports are offline. */
1242 return -ENODATA;
1243 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1244 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1245}
1246
3fbacffb 1247static DEVICE_ATTR(state_code, 0400, etr_mode_code_show, NULL);
d54853ef 1248
3fbacffb
KS
1249static ssize_t etr_untuned_show(struct device *dev,
1250 struct device_attribute *attr, char *buf)
d54853ef
MS
1251{
1252 struct etr_aib *aib = etr_aib_from_dev(dev);
1253
1254 if (!aib || !aib->slsw.v1)
1255 return -ENODATA;
1256 return sprintf(buf, "%i\n", aib->edf1.u);
1257}
1258
3fbacffb 1259static DEVICE_ATTR(untuned, 0400, etr_untuned_show, NULL);
d54853ef 1260
3fbacffb
KS
1261static ssize_t etr_network_id_show(struct device *dev,
1262 struct device_attribute *attr, char *buf)
d54853ef
MS
1263{
1264 struct etr_aib *aib = etr_aib_from_dev(dev);
1265
1266 if (!aib || !aib->slsw.v1)
1267 return -ENODATA;
1268 return sprintf(buf, "%i\n", aib->edf1.net_id);
1269}
1270
3fbacffb 1271static DEVICE_ATTR(network, 0400, etr_network_id_show, NULL);
d54853ef 1272
3fbacffb
KS
1273static ssize_t etr_id_show(struct device *dev,
1274 struct device_attribute *attr, char *buf)
d54853ef
MS
1275{
1276 struct etr_aib *aib = etr_aib_from_dev(dev);
1277
1278 if (!aib || !aib->slsw.v1)
1279 return -ENODATA;
1280 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1281}
1282
3fbacffb 1283static DEVICE_ATTR(id, 0400, etr_id_show, NULL);
d54853ef 1284
3fbacffb
KS
1285static ssize_t etr_port_number_show(struct device *dev,
1286 struct device_attribute *attr, char *buf)
d54853ef
MS
1287{
1288 struct etr_aib *aib = etr_aib_from_dev(dev);
1289
1290 if (!aib || !aib->slsw.v1)
1291 return -ENODATA;
1292 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1293}
1294
3fbacffb 1295static DEVICE_ATTR(port, 0400, etr_port_number_show, NULL);
d54853ef 1296
3fbacffb
KS
1297static ssize_t etr_coupled_show(struct device *dev,
1298 struct device_attribute *attr, char *buf)
d54853ef
MS
1299{
1300 struct etr_aib *aib = etr_aib_from_dev(dev);
1301
1302 if (!aib || !aib->slsw.v3)
1303 return -ENODATA;
1304 return sprintf(buf, "%i\n", aib->edf3.c);
1305}
1306
3fbacffb 1307static DEVICE_ATTR(coupled, 0400, etr_coupled_show, NULL);
d54853ef 1308
3fbacffb
KS
1309static ssize_t etr_local_time_show(struct device *dev,
1310 struct device_attribute *attr, char *buf)
d54853ef
MS
1311{
1312 struct etr_aib *aib = etr_aib_from_dev(dev);
1313
1314 if (!aib || !aib->slsw.v3)
1315 return -ENODATA;
1316 return sprintf(buf, "%i\n", aib->edf3.blto);
1317}
1318
3fbacffb 1319static DEVICE_ATTR(local_time, 0400, etr_local_time_show, NULL);
d54853ef 1320
3fbacffb
KS
1321static ssize_t etr_utc_offset_show(struct device *dev,
1322 struct device_attribute *attr, char *buf)
d54853ef
MS
1323{
1324 struct etr_aib *aib = etr_aib_from_dev(dev);
1325
1326 if (!aib || !aib->slsw.v3)
1327 return -ENODATA;
1328 return sprintf(buf, "%i\n", aib->edf3.buo);
1329}
1330
3fbacffb 1331static DEVICE_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
d54853ef 1332
3fbacffb
KS
1333static struct device_attribute *etr_port_attributes[] = {
1334 &dev_attr_online,
1335 &dev_attr_stepping_control,
1336 &dev_attr_state_code,
1337 &dev_attr_untuned,
1338 &dev_attr_network,
1339 &dev_attr_id,
1340 &dev_attr_port,
1341 &dev_attr_coupled,
1342 &dev_attr_local_time,
1343 &dev_attr_utc_offset,
d54853ef
MS
1344 NULL
1345};
1346
3fbacffb 1347static int __init etr_register_port(struct device *dev)
d54853ef 1348{
3fbacffb 1349 struct device_attribute **attr;
d54853ef
MS
1350 int rc;
1351
3fbacffb 1352 rc = device_register(dev);
d54853ef
MS
1353 if (rc)
1354 goto out;
1355 for (attr = etr_port_attributes; *attr; attr++) {
3fbacffb 1356 rc = device_create_file(dev, *attr);
d54853ef
MS
1357 if (rc)
1358 goto out_unreg;
1359 }
1360 return 0;
1361out_unreg:
1362 for (; attr >= etr_port_attributes; attr--)
3fbacffb
KS
1363 device_remove_file(dev, *attr);
1364 device_unregister(dev);
d54853ef
MS
1365out:
1366 return rc;
1367}
1368
3fbacffb 1369static void __init etr_unregister_port(struct device *dev)
d54853ef 1370{
3fbacffb 1371 struct device_attribute **attr;
d54853ef
MS
1372
1373 for (attr = etr_port_attributes; *attr; attr++)
3fbacffb
KS
1374 device_remove_file(dev, *attr);
1375 device_unregister(dev);
d54853ef
MS
1376}
1377
1378static int __init etr_init_sysfs(void)
1379{
1380 int rc;
1381
3fbacffb 1382 rc = subsys_system_register(&etr_subsys, NULL);
d54853ef
MS
1383 if (rc)
1384 goto out;
3fbacffb 1385 rc = device_create_file(etr_subsys.dev_root, &dev_attr_stepping_port);
d54853ef 1386 if (rc)
3fbacffb
KS
1387 goto out_unreg_subsys;
1388 rc = device_create_file(etr_subsys.dev_root, &dev_attr_stepping_mode);
d54853ef
MS
1389 if (rc)
1390 goto out_remove_stepping_port;
1391 rc = etr_register_port(&etr_port0_dev);
1392 if (rc)
1393 goto out_remove_stepping_mode;
1394 rc = etr_register_port(&etr_port1_dev);
1395 if (rc)
1396 goto out_remove_port0;
1397 return 0;
1398
1399out_remove_port0:
1400 etr_unregister_port(&etr_port0_dev);
1401out_remove_stepping_mode:
3fbacffb 1402 device_remove_file(etr_subsys.dev_root, &dev_attr_stepping_mode);
d54853ef 1403out_remove_stepping_port:
3fbacffb
KS
1404 device_remove_file(etr_subsys.dev_root, &dev_attr_stepping_port);
1405out_unreg_subsys:
1406 bus_unregister(&etr_subsys);
d54853ef
MS
1407out:
1408 return rc;
1da177e4
LT
1409}
1410
d54853ef 1411device_initcall(etr_init_sysfs);
d2fec595
MS
1412
1413/*
1414 * Server Time Protocol (STP) code.
1415 */
1416static int stp_online;
1417static struct stp_sstpi stp_info;
1418static void *stp_page;
1419
1420static void stp_work_fn(struct work_struct *work);
0b3016b7 1421static DEFINE_MUTEX(stp_work_mutex);
d2fec595 1422static DECLARE_WORK(stp_work, stp_work_fn);
04362301 1423static struct timer_list stp_timer;
d2fec595
MS
1424
1425static int __init early_parse_stp(char *p)
1426{
1427 if (strncmp(p, "off", 3) == 0)
1428 stp_online = 0;
1429 else if (strncmp(p, "on", 2) == 0)
1430 stp_online = 1;
1431 return 0;
1432}
1433early_param("stp", early_parse_stp);
1434
1435/*
1436 * Reset STP attachment.
1437 */
8f847003 1438static void __init stp_reset(void)
d2fec595
MS
1439{
1440 int rc;
1441
d7d1104f 1442 stp_page = (void *) get_zeroed_page(GFP_ATOMIC);
d2fec595 1443 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
4a672cfa 1444 if (rc == 0)
d2fec595
MS
1445 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1446 else if (stp_online) {
feab6501
MS
1447 pr_warning("The real or virtual hardware system does "
1448 "not provide an STP interface\n");
d7d1104f 1449 free_page((unsigned long) stp_page);
d2fec595
MS
1450 stp_page = NULL;
1451 stp_online = 0;
1452 }
1453}
1454
04362301
MS
1455static void stp_timeout(unsigned long dummy)
1456{
1457 queue_work(time_sync_wq, &stp_work);
1458}
1459
d2fec595
MS
1460static int __init stp_init(void)
1461{
750887de
HC
1462 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1463 return 0;
04362301 1464 setup_timer(&stp_timer, stp_timeout, 0UL);
750887de
HC
1465 time_init_wq();
1466 if (!stp_online)
1467 return 0;
1468 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1469 return 0;
1470}
1471
1472arch_initcall(stp_init);
1473
1474/*
1475 * STP timing alert. There are three causes:
1476 * 1) timing status change
1477 * 2) link availability change
1478 * 3) time control parameter change
1479 * In all three cases we are only interested in the clock source state.
1480 * If a STP clock source is now available use it.
1481 */
1482static void stp_timing_alert(struct stp_irq_parm *intparm)
1483{
1484 if (intparm->tsc || intparm->lac || intparm->tcpc)
750887de 1485 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1486}
1487
1488/*
1489 * STP sync check machine check. This is called when the timing state
1490 * changes from the synchronized state to the unsynchronized state.
1491 * After a STP sync check the clock is not in sync. The machine check
1492 * is broadcasted to all cpus at the same time.
1493 */
1494void stp_sync_check(void)
1495{
d2fec595 1496 disable_sync_clock(NULL);
750887de 1497 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1498}
1499
1500/*
1501 * STP island condition machine check. This is called when an attached
1502 * server attempts to communicate over an STP link and the servers
1503 * have matching CTN ids and have a valid stratum-1 configuration
1504 * but the configurations do not match.
1505 */
1506void stp_island_check(void)
1507{
d2fec595 1508 disable_sync_clock(NULL);
750887de 1509 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1510}
1511
750887de
HC
1512
1513static int stp_sync_clock(void *data)
d2fec595 1514{
750887de 1515 static int first;
d2fec595 1516 unsigned long long old_clock, delta;
750887de 1517 struct clock_sync_data *stp_sync;
d2fec595
MS
1518 int rc;
1519
750887de 1520 stp_sync = data;
d2fec595 1521
750887de
HC
1522 if (xchg(&first, 1) == 1) {
1523 /* Slave */
1524 clock_sync_cpu(stp_sync);
1525 return 0;
1526 }
d2fec595 1527
750887de
HC
1528 /* Wait until all other cpus entered the sync function. */
1529 while (atomic_read(&stp_sync->cpus) != 0)
1530 cpu_relax();
d2fec595 1531
d2fec595
MS
1532 enable_sync_clock();
1533
d2fec595
MS
1534 rc = 0;
1535 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1536 stp_info.todoff[2] || stp_info.todoff[3] ||
1537 stp_info.tmd != 2) {
1538 old_clock = get_clock();
1539 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1540 if (rc == 0) {
1541 delta = adjust_time(old_clock, get_clock(), 0);
1542 fixup_clock_comparator(delta);
1543 rc = chsc_sstpi(stp_page, &stp_info,
1544 sizeof(struct stp_sstpi));
1545 if (rc == 0 && stp_info.tmd != 2)
1546 rc = -EAGAIN;
1547 }
1548 }
1549 if (rc) {
1550 disable_sync_clock(NULL);
750887de 1551 stp_sync->in_sync = -EAGAIN;
d2fec595 1552 } else
750887de
HC
1553 stp_sync->in_sync = 1;
1554 xchg(&first, 0);
1555 return 0;
1556}
d2fec595 1557
750887de
HC
1558/*
1559 * STP work. Check for the STP state and take over the clock
1560 * synchronization if the STP clock source is usable.
1561 */
1562static void stp_work_fn(struct work_struct *work)
1563{
1564 struct clock_sync_data stp_sync;
1565 int rc;
1566
0b3016b7
MS
1567 /* prevent multiple execution. */
1568 mutex_lock(&stp_work_mutex);
1569
750887de
HC
1570 if (!stp_online) {
1571 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
04362301 1572 del_timer_sync(&stp_timer);
0b3016b7 1573 goto out_unlock;
750887de
HC
1574 }
1575
1576 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1577 if (rc)
0b3016b7 1578 goto out_unlock;
750887de
HC
1579
1580 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1581 if (rc || stp_info.c == 0)
0b3016b7 1582 goto out_unlock;
750887de 1583
8283cb43
MS
1584 /* Skip synchronization if the clock is already in sync. */
1585 if (check_sync_clock())
1586 goto out_unlock;
1587
750887de
HC
1588 memset(&stp_sync, 0, sizeof(stp_sync));
1589 get_online_cpus();
1590 atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
0f1959f5 1591 stop_machine(stp_sync_clock, &stp_sync, cpu_online_mask);
750887de 1592 put_online_cpus();
0b3016b7 1593
04362301
MS
1594 if (!check_sync_clock())
1595 /*
1596 * There is a usable clock but the synchonization failed.
1597 * Retry after a second.
1598 */
1599 mod_timer(&stp_timer, jiffies + HZ);
1600
0b3016b7
MS
1601out_unlock:
1602 mutex_unlock(&stp_work_mutex);
d2fec595
MS
1603}
1604
1605/*
3fbacffb 1606 * STP subsys sysfs interface functions
d2fec595 1607 */
3fbacffb
KS
1608static struct bus_type stp_subsys = {
1609 .name = "stp",
1610 .dev_name = "stp",
d2fec595
MS
1611};
1612
3fbacffb
KS
1613static ssize_t stp_ctn_id_show(struct device *dev,
1614 struct device_attribute *attr,
c9be0a36 1615 char *buf)
d2fec595
MS
1616{
1617 if (!stp_online)
1618 return -ENODATA;
1619 return sprintf(buf, "%016llx\n",
1620 *(unsigned long long *) stp_info.ctnid);
1621}
1622
3fbacffb 1623static DEVICE_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
d2fec595 1624
3fbacffb
KS
1625static ssize_t stp_ctn_type_show(struct device *dev,
1626 struct device_attribute *attr,
c9be0a36 1627 char *buf)
d2fec595
MS
1628{
1629 if (!stp_online)
1630 return -ENODATA;
1631 return sprintf(buf, "%i\n", stp_info.ctn);
1632}
1633
3fbacffb 1634static DEVICE_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
d2fec595 1635
3fbacffb
KS
1636static ssize_t stp_dst_offset_show(struct device *dev,
1637 struct device_attribute *attr,
c9be0a36 1638 char *buf)
d2fec595
MS
1639{
1640 if (!stp_online || !(stp_info.vbits & 0x2000))
1641 return -ENODATA;
1642 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1643}
1644
3fbacffb 1645static DEVICE_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
d2fec595 1646
3fbacffb
KS
1647static ssize_t stp_leap_seconds_show(struct device *dev,
1648 struct device_attribute *attr,
c9be0a36 1649 char *buf)
d2fec595
MS
1650{
1651 if (!stp_online || !(stp_info.vbits & 0x8000))
1652 return -ENODATA;
1653 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1654}
1655
3fbacffb 1656static DEVICE_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
d2fec595 1657
3fbacffb
KS
1658static ssize_t stp_stratum_show(struct device *dev,
1659 struct device_attribute *attr,
c9be0a36 1660 char *buf)
d2fec595
MS
1661{
1662 if (!stp_online)
1663 return -ENODATA;
1664 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1665}
1666
3fbacffb 1667static DEVICE_ATTR(stratum, 0400, stp_stratum_show, NULL);
d2fec595 1668
3fbacffb
KS
1669static ssize_t stp_time_offset_show(struct device *dev,
1670 struct device_attribute *attr,
c9be0a36 1671 char *buf)
d2fec595
MS
1672{
1673 if (!stp_online || !(stp_info.vbits & 0x0800))
1674 return -ENODATA;
1675 return sprintf(buf, "%i\n", (int) stp_info.tto);
1676}
1677
3fbacffb 1678static DEVICE_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
d2fec595 1679
3fbacffb
KS
1680static ssize_t stp_time_zone_offset_show(struct device *dev,
1681 struct device_attribute *attr,
c9be0a36 1682 char *buf)
d2fec595
MS
1683{
1684 if (!stp_online || !(stp_info.vbits & 0x4000))
1685 return -ENODATA;
1686 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1687}
1688
3fbacffb 1689static DEVICE_ATTR(time_zone_offset, 0400,
d2fec595
MS
1690 stp_time_zone_offset_show, NULL);
1691
3fbacffb
KS
1692static ssize_t stp_timing_mode_show(struct device *dev,
1693 struct device_attribute *attr,
c9be0a36 1694 char *buf)
d2fec595
MS
1695{
1696 if (!stp_online)
1697 return -ENODATA;
1698 return sprintf(buf, "%i\n", stp_info.tmd);
1699}
1700
3fbacffb 1701static DEVICE_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
d2fec595 1702
3fbacffb
KS
1703static ssize_t stp_timing_state_show(struct device *dev,
1704 struct device_attribute *attr,
c9be0a36 1705 char *buf)
d2fec595
MS
1706{
1707 if (!stp_online)
1708 return -ENODATA;
1709 return sprintf(buf, "%i\n", stp_info.tst);
1710}
1711
3fbacffb 1712static DEVICE_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
d2fec595 1713
3fbacffb
KS
1714static ssize_t stp_online_show(struct device *dev,
1715 struct device_attribute *attr,
c9be0a36 1716 char *buf)
d2fec595
MS
1717{
1718 return sprintf(buf, "%i\n", stp_online);
1719}
1720
3fbacffb
KS
1721static ssize_t stp_online_store(struct device *dev,
1722 struct device_attribute *attr,
d2fec595
MS
1723 const char *buf, size_t count)
1724{
1725 unsigned int value;
1726
1727 value = simple_strtoul(buf, NULL, 0);
1728 if (value != 0 && value != 1)
1729 return -EINVAL;
1730 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1731 return -EOPNOTSUPP;
8283cb43 1732 mutex_lock(&clock_sync_mutex);
d2fec595 1733 stp_online = value;
8283cb43
MS
1734 if (stp_online)
1735 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1736 else
1737 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
750887de 1738 queue_work(time_sync_wq, &stp_work);
8283cb43 1739 mutex_unlock(&clock_sync_mutex);
d2fec595
MS
1740 return count;
1741}
1742
1743/*
3fbacffb
KS
1744 * Can't use DEVICE_ATTR because the attribute should be named
1745 * stp/online but dev_attr_online already exists in this file ..
d2fec595 1746 */
3fbacffb 1747static struct device_attribute dev_attr_stp_online = {
d2fec595
MS
1748 .attr = { .name = "online", .mode = 0600 },
1749 .show = stp_online_show,
1750 .store = stp_online_store,
1751};
1752
3fbacffb
KS
1753static struct device_attribute *stp_attributes[] = {
1754 &dev_attr_ctn_id,
1755 &dev_attr_ctn_type,
1756 &dev_attr_dst_offset,
1757 &dev_attr_leap_seconds,
1758 &dev_attr_stp_online,
1759 &dev_attr_stratum,
1760 &dev_attr_time_offset,
1761 &dev_attr_time_zone_offset,
1762 &dev_attr_timing_mode,
1763 &dev_attr_timing_state,
d2fec595
MS
1764 NULL
1765};
1766
1767static int __init stp_init_sysfs(void)
1768{
3fbacffb 1769 struct device_attribute **attr;
d2fec595
MS
1770 int rc;
1771
3fbacffb 1772 rc = subsys_system_register(&stp_subsys, NULL);
d2fec595
MS
1773 if (rc)
1774 goto out;
1775 for (attr = stp_attributes; *attr; attr++) {
3fbacffb 1776 rc = device_create_file(stp_subsys.dev_root, *attr);
d2fec595
MS
1777 if (rc)
1778 goto out_unreg;
1779 }
1780 return 0;
1781out_unreg:
1782 for (; attr >= stp_attributes; attr--)
3fbacffb
KS
1783 device_remove_file(stp_subsys.dev_root, *attr);
1784 bus_unregister(&stp_subsys);
d2fec595
MS
1785out:
1786 return rc;
1787}
1788
1789device_initcall(stp_init_sysfs);
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