Commit | Line | Data |
---|---|---|
bc8fb5d0 | 1 | /* |
197b58e6 | 2 | * Hitachi UL SolutionEngine 7343 FPGA IRQ Support. |
bc8fb5d0 | 3 | * |
cafd63b0 | 4 | * Copyright (C) 2008 Yoshihiro Shimoda |
197b58e6 | 5 | * Copyright (C) 2012 Paul Mundt |
cafd63b0 | 6 | * |
197b58e6 | 7 | * Based on linux/arch/sh/boards/se/7343/irq.c |
cafd63b0 YS |
8 | * Copyright (C) 2007 Nobuhiro Iwamatsu |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file "COPYING" in the main directory of this archive | |
12 | * for more details. | |
bc8fb5d0 | 13 | */ |
197b58e6 PM |
14 | #define DRV_NAME "SE7343-FPGA" |
15 | #define pr_fmt(fmt) DRV_NAME ": " fmt | |
16 | ||
bc8fb5d0 | 17 | #include <linux/init.h> |
bc8fb5d0 | 18 | #include <linux/irq.h> |
cafd63b0 | 19 | #include <linux/interrupt.h> |
197b58e6 | 20 | #include <linux/irqdomain.h> |
939a24a6 | 21 | #include <linux/io.h> |
197b58e6 | 22 | #include <asm/sizes.h> |
939a24a6 | 23 | #include <mach-se/mach/se7343.h> |
bc8fb5d0 | 24 | |
197b58e6 PM |
25 | #define PA_CPLD_BASE_ADDR 0x11400000 |
26 | #define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */ | |
27 | #define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */ | |
53e6d8e0 | 28 | |
197b58e6 PM |
29 | static void __iomem *se7343_irq_regs; |
30 | struct irq_domain *se7343_irq_domain; | |
bc8fb5d0 | 31 | |
197b58e6 | 32 | static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc) |
bc8fb5d0 | 33 | { |
8228a048 | 34 | struct irq_data *data = irq_desc_get_irq_data(desc); |
197b58e6 PM |
35 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
36 | unsigned long mask; | |
37 | int bit; | |
bc8fb5d0 | 38 | |
197b58e6 | 39 | chip->irq_mask_ack(data); |
bc8fb5d0 | 40 | |
197b58e6 PM |
41 | mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG); |
42 | ||
43 | for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR) | |
44 | generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit)); | |
45 | ||
46 | chip->irq_unmask(data); | |
47 | } | |
48 | ||
49 | static void __init se7343_domain_init(void) | |
bc8fb5d0 | 50 | { |
197b58e6 | 51 | int i; |
cafd63b0 | 52 | |
197b58e6 PM |
53 | se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR, |
54 | &irq_domain_simple_ops, NULL); | |
55 | if (unlikely(!se7343_irq_domain)) { | |
56 | printk("Failed to get IRQ domain\n"); | |
57 | return; | |
58 | } | |
cafd63b0 | 59 | |
197b58e6 PM |
60 | for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) { |
61 | int irq = irq_create_mapping(se7343_irq_domain, i); | |
53e6d8e0 | 62 | |
197b58e6 PM |
63 | if (unlikely(irq == 0)) { |
64 | printk("Failed to allocate IRQ %d\n", i); | |
65 | return; | |
66 | } | |
bc8fb5d0 | 67 | } |
bc8fb5d0 PM |
68 | } |
69 | ||
197b58e6 | 70 | static void __init se7343_gc_init(void) |
bc8fb5d0 | 71 | { |
197b58e6 PM |
72 | struct irq_chip_generic *gc; |
73 | struct irq_chip_type *ct; | |
74 | unsigned int irq_base; | |
cafd63b0 | 75 | |
197b58e6 | 76 | irq_base = irq_linear_revmap(se7343_irq_domain, 0); |
cafd63b0 | 77 | |
197b58e6 PM |
78 | gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs, |
79 | handle_level_irq); | |
80 | if (unlikely(!gc)) | |
81 | return; | |
53e6d8e0 | 82 | |
197b58e6 PM |
83 | ct = gc->chip_types; |
84 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
85 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
cafd63b0 | 86 | |
197b58e6 PM |
87 | ct->regs.mask = PA_CPLD_IMSK_REG; |
88 | ||
89 | irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR), | |
90 | IRQ_GC_INIT_MASK_CACHE, | |
91 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
53e6d8e0 | 92 | |
fcb8918f TG |
93 | irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux); |
94 | irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); | |
197b58e6 | 95 | |
fcb8918f TG |
96 | irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux); |
97 | irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); | |
197b58e6 | 98 | |
fcb8918f TG |
99 | irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux); |
100 | irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); | |
197b58e6 | 101 | |
fcb8918f TG |
102 | irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux); |
103 | irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); | |
bc8fb5d0 | 104 | } |
197b58e6 PM |
105 | |
106 | /* | |
107 | * Initialize IRQ setting | |
108 | */ | |
109 | void __init init_7343se_IRQ(void) | |
110 | { | |
111 | se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16); | |
112 | if (unlikely(!se7343_irq_regs)) { | |
113 | pr_err("Failed to remap CPLD\n"); | |
114 | return; | |
115 | } | |
116 | ||
117 | /* | |
118 | * All FPGA IRQs disabled by default | |
119 | */ | |
120 | iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG); | |
121 | ||
122 | __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ | |
123 | ||
124 | se7343_domain_init(); | |
125 | se7343_gc_init(); | |
126 | } |