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959f85f8 PM |
1 | #ifndef __PCI_SH4_H |
2 | #define __PCI_SH4_H | |
3 | ||
7d740a06 YS |
4 | #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
5 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | |
6 | defined(CONFIG_CPU_SUBTYPE_SH7763) | |
959f85f8 PM |
7 | #include "pci-sh7780.h" |
8 | #else | |
9 | #include "pci-sh7751.h" | |
10 | #endif | |
11 | ||
12 | #include <asm/io.h> | |
13 | ||
14 | /* startup values */ | |
15 | #define PCI_PROBE_BIOS 1 | |
16 | #define PCI_PROBE_CONF1 2 | |
17 | #define PCI_PROBE_CONF2 4 | |
959f85f8 PM |
18 | #define PCI_NO_CHECKS 0x400 |
19 | #define PCI_ASSIGN_ROMS 0x1000 | |
20 | #define PCI_BIOS_IRQ_SCAN 0x2000 | |
21 | ||
22 | #define SH4_PCICR 0x100 /* PCI Control Register */ | |
23 | #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */ | |
24 | #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */ | |
25 | #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */ | |
26 | #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */ | |
27 | #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */ | |
28 | #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */ | |
29 | #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */ | |
30 | #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */ | |
31 | #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */ | |
32 | #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */ | |
33 | #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */ | |
34 | #define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */ | |
35 | #define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */ | |
36 | #define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */ | |
37 | #define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */ | |
38 | #define SH4_PCIINT 0x114 /* PCI Interrupt Register */ | |
39 | #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */ | |
40 | #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */ | |
41 | #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */ | |
42 | #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */ | |
43 | #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */ | |
44 | #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */ | |
45 | #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */ | |
46 | #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */ | |
47 | #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */ | |
48 | #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */ | |
49 | #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */ | |
50 | #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */ | |
51 | #define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */ | |
a45635df PM |
52 | #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */ |
53 | #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */ | |
54 | #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */ | |
55 | #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */ | |
56 | #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */ | |
57 | #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */ | |
58 | #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */ | |
59 | #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */ | |
60 | #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */ | |
61 | #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */ | |
62 | #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */ | |
959f85f8 PM |
63 | #define SH4_PCIALR 0x11C /* Error Address Register */ |
64 | #define SH4_PCICLR 0x120 /* Error Command/Data */ | |
65 | #define SH4_PCICLR_MPIO 0x80000000 | |
66 | #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */ | |
67 | #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */ | |
68 | #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */ | |
69 | #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */ | |
70 | #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */ | |
71 | #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */ | |
72 | #define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */ | |
73 | #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */ | |
74 | #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */ | |
a45635df | 75 | #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */ |
959f85f8 PM |
76 | #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */ |
77 | #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */ | |
78 | #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */ | |
79 | #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */ | |
80 | #define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ | |
81 | #define SH4_PCIBMLR 0x138 /* Error Bus Master Register */ | |
82 | #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */ | |
83 | #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */ | |
84 | #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */ | |
85 | #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */ | |
86 | #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */ | |
87 | #define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ | |
88 | #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */ | |
89 | #define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */ | |
90 | #define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */ | |
91 | #define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */ | |
92 | #define SH4_PCIDCR0 0x18C /* DMA0 Control Register */ | |
93 | #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */ | |
94 | #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */ | |
95 | #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/ | |
96 | #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */ | |
97 | #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */ | |
98 | #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/ | |
99 | #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */ | |
100 | #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */ | |
101 | #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */ | |
102 | #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */ | |
103 | #define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */ | |
104 | #define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */ | |
105 | #define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */ | |
106 | #define SH4_PCIDCR1 0x19C /* DMA1 Control Register */ | |
107 | #define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */ | |
108 | #define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */ | |
109 | #define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */ | |
110 | #define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */ | |
111 | #define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */ | |
112 | #define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */ | |
113 | #define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */ | |
114 | #define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */ | |
115 | #define SH4_PCIPAR 0x1C0 /* PIO Address Register */ | |
116 | #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */ | |
117 | #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */ | |
118 | #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */ | |
119 | #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */ | |
120 | #define SH4_PCIMBR 0x1C4 /* Memory Base Address */ | |
121 | #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */ | |
122 | #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */ | |
123 | #define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */ | |
124 | #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */ | |
125 | #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */ | |
126 | #define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ | |
127 | #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */ | |
128 | #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */ | |
129 | #define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ | |
130 | #define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */ | |
131 | #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */ | |
132 | #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */ | |
133 | /* For definitions of BCR, MCR see ... */ | |
134 | #define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */ | |
135 | #define SH4_PCIMBR0 SH4_PCIBCR1 | |
136 | #define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */ | |
137 | #define SH4_PCIMBMR0 SH4_PCIBCR2 | |
138 | #define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */ | |
139 | #define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */ | |
140 | #define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */ | |
141 | #define SH4_PCIMBR2 SH4_PCIWCR3 | |
142 | #define SH4_PCIMCR 0x1F4 /* Memory Control Register */ | |
143 | #define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */ | |
144 | #define SH4_PCIPCTR 0x200 /* Port Control Register */ | |
145 | #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */ | |
146 | #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */ | |
147 | #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */ | |
148 | #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */ | |
149 | #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */ | |
150 | #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */ | |
151 | #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */ | |
152 | #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */ | |
153 | #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */ | |
154 | #define SH4_PCIPDTR 0x204 /* Port Data Register */ | |
155 | #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */ | |
156 | #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */ | |
157 | #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */ | |
158 | #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */ | |
159 | #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */ | |
160 | #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ | |
161 | #define SH4_PCIPDR 0x220 /* Port IO Data Register */ | |
162 | ||
959f85f8 PM |
163 | /* arch/sh/kernel/drivers/pci/ops-sh4.c */ |
164 | extern struct pci_ops sh4_pci_ops; | |
b8b47bfb | 165 | int pci_fixup_pcic(struct pci_channel *chan); |
959f85f8 PM |
166 | |
167 | struct sh4_pci_address_space { | |
168 | unsigned long base; | |
169 | unsigned long size; | |
170 | }; | |
171 | ||
172 | struct sh4_pci_address_map { | |
173 | struct sh4_pci_address_space window0; | |
174 | struct sh4_pci_address_space window1; | |
959f85f8 PM |
175 | }; |
176 | ||
b8b47bfb MD |
177 | static inline void pci_write_reg(struct pci_channel *chan, |
178 | unsigned long val, unsigned long reg) | |
959f85f8 | 179 | { |
9d56dd3b | 180 | __raw_writel(val, chan->reg_base + reg); |
959f85f8 PM |
181 | } |
182 | ||
b8b47bfb MD |
183 | static inline unsigned long pci_read_reg(struct pci_channel *chan, |
184 | unsigned long reg) | |
959f85f8 | 185 | { |
9d56dd3b | 186 | return __raw_readl(chan->reg_base + reg); |
959f85f8 | 187 | } |
b8b47bfb | 188 | |
959f85f8 | 189 | #endif /* __PCI_SH4_H */ |