[deliverable/linux.git] / arch / sh / drivers / pci / pci.c

/*
 * arch/sh/drivers/pci/pci.c
 *
 * Copyright (c) 2002 M. R. Brown  <mrbrown@linux-sh.org>
 * Copyright (c) 2004 - 2006 Paul Mundt  <lethal@linux-sh.org>
 *
 * These functions are collected here to reduce duplication of common
 * code amongst the many platform-specific PCI support code files.
 *
 * These routines require the following board-specific routines:
 * void pcibios_fixup_irqs();
 *
 * See include/asm-sh/pci.h for more information.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/io.h>

static int __init pcibios_init(void)
{
	struct pci_channel *p;
	struct pci_bus *bus;
	int busno;

#ifdef CONFIG_PCI_AUTO
	/* assign resources */
	busno = 0;
	for (p = board_pci_channels; p->pci_ops != NULL; p++)
		busno = pciauto_assign_resources(busno, p) + 1;
#endif

	/* scan the buses */
	busno = 0;
	for (p= board_pci_channels; p->pci_ops != NULL; p++) {
		bus = pci_scan_bus(busno, p->pci_ops, p);
		busno = bus->subordinate+1;
	}

	/* board-specific fixups */
	pcibios_fixup_irqs();

	return 0;
}

subsys_initcall(pcibios_init);

void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
			struct resource *res, int resource)
{
	u32 new, check;
	int reg;

	new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
	if (resource < 6) {
		reg = PCI_BASE_ADDRESS_0 + 4*resource;
	} else if (resource == PCI_ROM_RESOURCE) {
		res->flags |= IORESOURCE_ROM_ENABLE;
		new |= PCI_ROM_ADDRESS_ENABLE;
		reg = dev->rom_base_reg;
	} else {
		/*
		 * Somebody might have asked allocation of a non-standard
		 * resource
		 */
		return;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);
	if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ?
		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
		printk(KERN_ERR "PCI: Error while updating region "
		       "%s/%d (%08x != %08x)\n", pci_name(dev), resource,
		       new, check);
	}
}

void pcibios_align_resource(void *data, struct resource *res,
			    resource_size_t size, resource_size_t align)
			    __attribute__ ((weak));

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 */
void pcibios_align_resource(void *data, struct resource *res,
			    resource_size_t size, resource_size_t align)
{
	if (res->flags & IORESOURCE_IO) {
		resource_size_t start = res->start;

		if (start & 0x300) {
			start = (start + 0x3ff) & ~0x3ff;
			res->start = start;
		}
	}
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for(idx=0; idx<6; idx++) {
		if (!(mask & (1 << idx)))
			continue;
		r = &dev->resource[idx];
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available because "
			       "of resource collisions\n", pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (dev->resource[PCI_ROM_RESOURCE].start)
		cmd |= PCI_COMMAND_MEMORY;
	if (cmd != old_cmd) {
		printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

/*
 *  If we set up a device for bus mastering, we need to check and set
 *  the latency timer as it may not be properly set.
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
	unsigned long start = pci_resource_start(dev, bar);
	unsigned long len = pci_resource_len(dev, bar);
	unsigned long flags = pci_resource_flags(dev, bar);

	if (!len || !start)
		return NULL;
	if (maxlen && len > maxlen)
		len = maxlen;

	/*
	 * Presently the IORESOURCE_MEM case is a bit special, most
	 * SH7751 style PCI controllers have PCI memory at a fixed
	 * location in the address space where no remapping is desired
	 * (traditionally at 0xfd000000). Once this changes, the
	 * IORESOURCE_MEM case will have to switch to using ioremap() and
	 * more care will have to be taken to inhibit page table mapping
	 * for legacy cores.
	 *
	 * For now everything wraps to ioport_map(), since boards that
	 * have PCI will be able to check the address range properly on
	 * their own.
	 *			-- PFM.
	 */
	if (flags & (IORESOURCE_IO | IORESOURCE_MEM))
		return ioport_map(start, len);

	return NULL;
}

void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
{
	iounmap(addr);
}

EXPORT_SYMBOL(pci_iomap);
EXPORT_SYMBOL(pci_iounmap);
Commit	Line	Data
a09749dd JL	1	/*
a09749dd JL	2	* arch/sh/drivers/pci/pci.c
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org>
d7cdc9e8	5	* Copyright (c) 2004 - 2006 Paul Mundt <lethal@linux-sh.org>
a09749dd	6	*
1da177e4 LT	7	* These functions are collected here to reduce duplication of common
1da177e4 LT	8	* code amongst the many platform-specific PCI support code files.
a09749dd	9	*
1da177e4 LT	10	* These routines require the following board-specific routines:
	11	* void pcibios_fixup_irqs();
	12	*
	13	* See include/asm-sh/pci.h for more information.
a09749dd JL	14	*
	15	* This file is subject to the terms and conditions of the GNU General Public
	16	* License. See the file "COPYING" in the main directory of this archive
	17	* for more details.
1da177e4	18	*/
1da177e4 LT	19	#include <linux/kernel.h>
	20	#include <linux/pci.h>
	21	#include <linux/init.h>
a09749dd	22	#include <asm/io.h>
1da177e4 LT	23
	24	static int __init pcibios_init(void)
	25	{
	26	struct pci_channel *p;
	27	struct pci_bus *bus;
	28	int busno;
	29
	30	#ifdef CONFIG_PCI_AUTO
	31	/* assign resources */
	32	busno = 0;
a09749dd	33	for (p = board_pci_channels; p->pci_ops != NULL; p++)
1da177e4	34	busno = pciauto_assign_resources(busno, p) + 1;
1da177e4 LT	35	#endif
	36
	37	/* scan the buses */
	38	busno = 0;
	39	for (p= board_pci_channels; p->pci_ops != NULL; p++) {
	40	bus = pci_scan_bus(busno, p->pci_ops, p);
	41	busno = bus->subordinate+1;
	42	}
	43
	44	/* board-specific fixups */
	45	pcibios_fixup_irqs();
	46
	47	return 0;
	48	}
	49
	50	subsys_initcall(pcibios_init);
	51
	52	void
	53	pcibios_update_resource(struct pci_dev dev, struct resource root,
	54	struct resource *res, int resource)
	55	{
	56	u32 new, check;
	57	int reg;
	58
	59	new = res->start \| (res->flags & PCI_REGION_FLAG_MASK);
	60	if (resource < 6) {
	61	reg = PCI_BASE_ADDRESS_0 + 4*resource;
	62	} else if (resource == PCI_ROM_RESOURCE) {
	63	res->flags \|= IORESOURCE_ROM_ENABLE;
	64	new \|= PCI_ROM_ADDRESS_ENABLE;
	65	reg = dev->rom_base_reg;
	66	} else {
a09749dd JL	67	/*
	68	* Somebody might have asked allocation of a non-standard
	69	* resource
	70	*/
1da177e4 LT	71	return;
1da177e4 LT	72	}
a09749dd	73
1da177e4 LT	74	pci_write_config_dword(dev, reg, new);
1da177e4 LT	75	pci_read_config_dword(dev, reg, &check);
a09749dd JL	76	if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ?
a09749dd JL	77	PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
1da177e4 LT	78	printk(KERN_ERR "PCI: Error while updating region "
	79	"%s/%d (%08x != %08x)\n", pci_name(dev), resource,
	80	new, check);
	81	}
	82	}
	83
	84	void pcibios_align_resource(void data, struct resource res,
e31dd6e4	85	resource_size_t size, resource_size_t align)
1da177e4 LT	86	__attribute__ ((weak));
	87
	88	/*
	89	* We need to avoid collisions with `mirrored' VGA ports
	90	* and other strange ISA hardware, so we always want the
	91	* addresses to be allocated in the 0x000-0x0ff region
	92	* modulo 0x400.
	93	*/
	94	void pcibios_align_resource(void data, struct resource res,
e31dd6e4	95	resource_size_t size, resource_size_t align)
1da177e4 LT	96	{
1da177e4 LT	97	if (res->flags & IORESOURCE_IO) {
e31dd6e4	98	resource_size_t start = res->start;
1da177e4 LT	99
	100	if (start & 0x300) {
	101	start = (start + 0x3ff) & ~0x3ff;
	102	res->start = start;
	103	}
	104	}
	105	}
	106
	107	int pcibios_enable_device(struct pci_dev *dev, int mask)
	108	{
	109	u16 cmd, old_cmd;
	110	int idx;
	111	struct resource *r;
	112
	113	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	114	old_cmd = cmd;
	115	for(idx=0; idx<6; idx++) {
	116	if (!(mask & (1 << idx)))
	117	continue;
	118	r = &dev->resource[idx];
	119	if (!r->start && r->end) {
	120	printk(KERN_ERR "PCI: Device %s not available because "
	121	"of resource collisions\n", pci_name(dev));
	122	return -EINVAL;
	123	}
	124	if (r->flags & IORESOURCE_IO)
	125	cmd \|= PCI_COMMAND_IO;
	126	if (r->flags & IORESOURCE_MEM)
	127	cmd \|= PCI_COMMAND_MEMORY;
	128	}
	129	if (dev->resource[PCI_ROM_RESOURCE].start)
	130	cmd \|= PCI_COMMAND_MEMORY;
	131	if (cmd != old_cmd) {
	132	printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
	133	pci_name(dev), old_cmd, cmd);
	134	pci_write_config_word(dev, PCI_COMMAND, cmd);
	135	}
	136	return 0;
	137	}
	138
	139	/*
	140	* If we set up a device for bus mastering, we need to check and set
	141	* the latency timer as it may not be properly set.
	142	*/
	143	unsigned int pcibios_max_latency = 255;
	144
	145	void pcibios_set_master(struct pci_dev *dev)
	146	{
	147	u8 lat;
	148	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	149	if (lat < 16)
	150	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	151	else if (lat > pcibios_max_latency)
	152	lat = pcibios_max_latency;
	153	else
	154	return;
a09749dd JL	155	printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
a09749dd JL	156	pci_name(dev), lat);
1da177e4 LT	157	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	158	}
	159
	160	void __init pcibios_update_irq(struct pci_dev *dev, int irq)
	161	{
	162	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	163	}
a09749dd JL	164
	165	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen)
	166	{
	167	unsigned long start = pci_resource_start(dev, bar);
	168	unsigned long len = pci_resource_len(dev, bar);
	169	unsigned long flags = pci_resource_flags(dev, bar);
	170
	171	if (!len \|\| !start)
	172	return NULL;
	173	if (maxlen && len > maxlen)
	174	len = maxlen;
d7cdc9e8 PM	175
	176	/*
	177	* Presently the IORESOURCE_MEM case is a bit special, most
	178	* SH7751 style PCI controllers have PCI memory at a fixed
	179	* location in the address space where no remapping is desired
	180	* (traditionally at 0xfd000000). Once this changes, the
	181	* IORESOURCE_MEM case will have to switch to using ioremap() and
	182	* more care will have to be taken to inhibit page table mapping
	183	* for legacy cores.
	184	*
	185	* For now everything wraps to ioport_map(), since boards that
	186	* have PCI will be able to check the address range properly on
	187	* their own.
	188	* -- PFM.
	189	*/
	190	if (flags & (IORESOURCE_IO \| IORESOURCE_MEM))
a09749dd	191	return ioport_map(start, len);
a09749dd JL	192
	193	return NULL;
	194	}
	195
	196	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	197	{
	198	iounmap(addr);
	199	}
	200
	201	EXPORT_SYMBOL(pci_iomap);
	202	EXPORT_SYMBOL(pci_iounmap);