Commit | Line | Data |
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36ddf31b PM |
1 | #ifndef __ASM_SH_CLOCK_H |
2 | #define __ASM_SH_CLOCK_H | |
3 | ||
36ddf31b PM |
4 | #include <linux/list.h> |
5 | #include <linux/seq_file.h> | |
a1153e27 | 6 | #include <linux/cpufreq.h> |
1d118562 | 7 | #include <linux/clk.h> |
de925426 | 8 | #include <linux/err.h> |
36ddf31b PM |
9 | |
10 | struct clk; | |
11 | ||
12 | struct clk_ops { | |
13 | void (*init)(struct clk *clk); | |
ae891a42 | 14 | int (*enable)(struct clk *clk); |
36ddf31b | 15 | void (*disable)(struct clk *clk); |
b68d8201 | 16 | unsigned long (*recalc)(struct clk *clk); |
1929cb34 | 17 | int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); |
d680c76e | 18 | int (*set_parent)(struct clk *clk, struct clk *parent); |
f6991b04 | 19 | long (*round_rate)(struct clk *clk, unsigned long rate); |
36ddf31b PM |
20 | }; |
21 | ||
22 | struct clk { | |
23 | struct list_head node; | |
24 | const char *name; | |
1d118562 | 25 | int id; |
36ddf31b PM |
26 | struct module *owner; |
27 | ||
28 | struct clk *parent; | |
29 | struct clk_ops *ops; | |
30 | ||
b1f6cfe4 PM |
31 | struct list_head children; |
32 | struct list_head sibling; /* node for children */ | |
33 | ||
4f5ecaa0 | 34 | int usecount; |
36ddf31b PM |
35 | |
36 | unsigned long rate; | |
37 | unsigned long flags; | |
a77b5ac0 | 38 | |
549b5e35 PM |
39 | void __iomem *enable_reg; |
40 | unsigned int enable_bit; | |
41 | ||
5c8f9d94 | 42 | unsigned long arch_flags; |
a77b5ac0 | 43 | void *priv; |
cedcf336 | 44 | struct dentry *dentry; |
a1153e27 | 45 | struct cpufreq_frequency_table *freq_table; |
36ddf31b PM |
46 | }; |
47 | ||
0dae8957 PM |
48 | struct clk_lookup { |
49 | struct list_head node; | |
50 | const char *dev_id; | |
51 | const char *con_id; | |
52 | struct clk *clk; | |
53 | }; | |
54 | ||
4ff29ff8 | 55 | #define CLK_ENABLE_ON_INIT (1 << 0) |
36ddf31b PM |
56 | |
57 | /* Should be defined by processor-specific code */ | |
253b0887 | 58 | void __deprecated arch_init_clk_ops(struct clk_ops **, int type); |
fa43972f | 59 | int __init arch_clk_init(void); |
36ddf31b PM |
60 | |
61 | /* arch/sh/kernel/cpu/clock.c */ | |
62 | int clk_init(void); | |
b1f6cfe4 PM |
63 | unsigned long followparent_recalc(struct clk *); |
64 | void recalculate_root_clocks(void); | |
65 | void propagate_rate(struct clk *); | |
aa87aa34 | 66 | int clk_reparent(struct clk *child, struct clk *parent); |
36ddf31b PM |
67 | int clk_register(struct clk *); |
68 | void clk_unregister(struct clk *); | |
69 | ||
253b0887 PM |
70 | /* arch/sh/kernel/cpu/clock-cpg.c */ |
71 | int __init __deprecated cpg_clk_init(void); | |
72 | ||
1929cb34 | 73 | /* the exported API, in addition to clk_set_rate */ |
74 | /** | |
75 | * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter | |
76 | * @clk: clock source | |
77 | * @rate: desired clock rate in Hz | |
78 | * @algo_id: algorithm id to be passed down to ops->set_rate | |
79 | * | |
80 | * Returns success (0) or negative errno. | |
81 | */ | |
82 | int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); | |
83 | ||
84 | enum clk_sh_algo_id { | |
85 | NO_CHANGE = 0, | |
86 | ||
87 | IUS_N1_N1, | |
88 | IUS_322, | |
89 | IUS_522, | |
90 | IUS_N11, | |
91 | ||
92 | SB_N1, | |
93 | ||
94 | SB3_N1, | |
95 | SB3_32, | |
96 | SB3_43, | |
97 | SB3_54, | |
98 | ||
99 | BP_N1, | |
100 | ||
101 | IP_N1, | |
102 | }; | |
b68d8201 | 103 | |
c94a8574 MD |
104 | struct clk_div_mult_table { |
105 | unsigned int *divisors; | |
106 | unsigned int nr_divisors; | |
107 | unsigned int *multipliers; | |
108 | unsigned int nr_multipliers; | |
109 | }; | |
110 | ||
111 | struct cpufreq_frequency_table; | |
112 | void clk_rate_table_build(struct clk *clk, | |
113 | struct cpufreq_frequency_table *freq_table, | |
114 | int nr_freqs, | |
115 | struct clk_div_mult_table *src_table, | |
116 | unsigned long *bitmap); | |
117 | ||
118 | long clk_rate_table_round(struct clk *clk, | |
119 | struct cpufreq_frequency_table *freq_table, | |
120 | unsigned long rate); | |
121 | ||
098dee99 MD |
122 | int clk_rate_table_find(struct clk *clk, |
123 | struct cpufreq_frequency_table *freq_table, | |
124 | unsigned long rate); | |
125 | ||
6881e8bf MD |
126 | #define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \ |
127 | _enable_bit, _flags) \ | |
128 | { \ | |
129 | .name = _name, \ | |
130 | .id = _id, \ | |
131 | .parent = _parent, \ | |
132 | .enable_reg = (void __iomem *)_enable_reg, \ | |
133 | .enable_bit = _enable_bit, \ | |
134 | .flags = _flags, \ | |
135 | } | |
136 | ||
137 | int sh_clk_mstp32_register(struct clk *clks, int nr); | |
138 | ||
a1153e27 MD |
139 | #define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \ |
140 | { \ | |
141 | .name = _name, \ | |
142 | .parent = _parent, \ | |
143 | .enable_reg = (void __iomem *)_reg, \ | |
144 | .enable_bit = _shift, \ | |
145 | .arch_flags = _div_bitmap, \ | |
146 | .flags = _flags, \ | |
147 | } | |
148 | ||
149 | int sh_clk_div4_register(struct clk *clks, int nr, | |
150 | struct clk_div_mult_table *table); | |
31c3af50 GL |
151 | int sh_clk_div4_enable_register(struct clk *clks, int nr, |
152 | struct clk_div_mult_table *table); | |
153 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, | |
154 | struct clk_div_mult_table *table); | |
a1153e27 | 155 | |
2693e274 MD |
156 | #define SH_CLK_DIV6(_name, _parent, _reg, _flags) \ |
157 | { \ | |
158 | .name = _name, \ | |
159 | .parent = _parent, \ | |
160 | .enable_reg = (void __iomem *)_reg, \ | |
161 | .flags = _flags, \ | |
162 | } | |
163 | ||
164 | int sh_clk_div6_register(struct clk *clks, int nr); | |
165 | ||
36ddf31b | 166 | #endif /* __ASM_SH_CLOCK_H */ |