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1da177e4 LT |
1 | #ifndef __ASM_SH_IO_H |
2 | #define __ASM_SH_IO_H | |
3 | ||
4 | /* | |
5 | * Convention: | |
6 | * read{b,w,l}/write{b,w,l} are for PCI, | |
7 | * while in{b,w,l}/out{b,w,l} are for ISA | |
8 | * These may (will) be platform specific function. | |
9 | * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p | |
10 | * and 'string' versions: ins{b,w,l}/outs{b,w,l} | |
11 | * For read{b,w,l} and write{b,w,l} there are also __raw versions, which | |
12 | * do not have a memory barrier after them. | |
13 | * | |
b66c1a39 | 14 | * In addition, we have |
1da177e4 LT |
15 | * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O. |
16 | * which are processor specific. | |
17 | */ | |
18 | ||
19 | /* | |
20 | * We follow the Alpha convention here: | |
21 | * __inb expands to an inline function call (which calls via the mv) | |
22 | * _inb is a real function call (note ___raw fns are _ version of __raw) | |
23 | * inb by default expands to _inb, but the machine specific code may | |
24 | * define it to __inb if it chooses. | |
25 | */ | |
1da177e4 LT |
26 | #include <asm/cache.h> |
27 | #include <asm/system.h> | |
28 | #include <asm/addrspace.h> | |
29 | #include <asm/machvec.h> | |
b66c1a39 PM |
30 | #include <asm/pgtable.h> |
31 | #include <asm-generic/iomap.h> | |
32 | ||
33 | #ifdef __KERNEL__ | |
1da177e4 LT |
34 | |
35 | /* | |
36 | * Depending on which platform we are running on, we need different | |
37 | * I/O functions. | |
38 | */ | |
b66c1a39 PM |
39 | #define __IO_PREFIX generic |
40 | #include <asm/io_generic.h> | |
e7cc9a73 | 41 | #include <asm/io_trapped.h> |
b66c1a39 PM |
42 | |
43 | #define maybebadio(port) \ | |
44 | printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \ | |
45 | __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0)) | |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* |
48 | * Since boards are able to define their own set of I/O routines through | |
49 | * their respective machine vector, we always wrap through the mv. | |
50 | * | |
51 | * Also, in the event that a board hasn't provided its own definition for | |
52 | * a given routine, it will be wrapped to generic code at run-time. | |
53 | */ | |
54 | ||
b66c1a39 PM |
55 | #define __inb(p) sh_mv.mv_inb((p)) |
56 | #define __inw(p) sh_mv.mv_inw((p)) | |
57 | #define __inl(p) sh_mv.mv_inl((p)) | |
58 | #define __outb(x,p) sh_mv.mv_outb((x),(p)) | |
59 | #define __outw(x,p) sh_mv.mv_outw((x),(p)) | |
60 | #define __outl(x,p) sh_mv.mv_outl((x),(p)) | |
61 | ||
62 | #define __inb_p(p) sh_mv.mv_inb_p((p)) | |
63 | #define __inw_p(p) sh_mv.mv_inw_p((p)) | |
64 | #define __inl_p(p) sh_mv.mv_inl_p((p)) | |
65 | #define __outb_p(x,p) sh_mv.mv_outb_p((x),(p)) | |
66 | #define __outw_p(x,p) sh_mv.mv_outw_p((x),(p)) | |
67 | #define __outl_p(x,p) sh_mv.mv_outl_p((x),(p)) | |
68 | ||
69 | #define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) | |
70 | #define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) | |
71 | #define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) | |
72 | #define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) | |
73 | #define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) | |
74 | #define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) | |
75 | ||
76 | #define __readb(a) sh_mv.mv_readb((a)) | |
77 | #define __readw(a) sh_mv.mv_readw((a)) | |
78 | #define __readl(a) sh_mv.mv_readl((a)) | |
79 | #define __writeb(v,a) sh_mv.mv_writeb((v),(a)) | |
80 | #define __writew(v,a) sh_mv.mv_writew((v),(a)) | |
81 | #define __writel(v,a) sh_mv.mv_writel((v),(a)) | |
82 | ||
83 | #define inb __inb | |
84 | #define inw __inw | |
85 | #define inl __inl | |
86 | #define outb __outb | |
87 | #define outw __outw | |
88 | #define outl __outl | |
89 | ||
90 | #define inb_p __inb_p | |
91 | #define inw_p __inw_p | |
92 | #define inl_p __inl_p | |
93 | #define outb_p __outb_p | |
94 | #define outw_p __outw_p | |
95 | #define outl_p __outl_p | |
96 | ||
97 | #define insb __insb | |
98 | #define insw __insw | |
99 | #define insl __insl | |
100 | #define outsb __outsb | |
101 | #define outsw __outsw | |
102 | #define outsl __outsl | |
103 | ||
64c9627c PM |
104 | #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) |
105 | #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) | |
106 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v)) | |
1da177e4 | 107 | |
64c9627c PM |
108 | #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) |
109 | #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) | |
110 | #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) | |
111 | ||
112 | void __raw_writesl(void __iomem *addr, const void *data, int longlen); | |
113 | void __raw_readsl(const void __iomem *addr, void *data, int longlen); | |
05ae9158 | 114 | |
1da177e4 LT |
115 | /* |
116 | * The platform header files may define some of these macros to use | |
117 | * the inlined versions where appropriate. These macros may also be | |
118 | * redefined by userlevel programs. | |
119 | */ | |
64c9627c PM |
120 | #define readb(a) ({ unsigned int r_ = __readb(a); mb(); r_; }) |
121 | #define readw(a) ({ unsigned int r_ = __readw(a); mb(); r_; }) | |
122 | #define readl(a) ({ unsigned int r_ = __readl(a); mb(); r_; }) | |
123 | ||
124 | #define writeb(v,a) ({ __writeb((v),(a)); mb(); }) | |
125 | #define writew(v,a) ({ __writew((v),(a)); mb(); }) | |
126 | #define writel(v,a) ({ __writel((v),(a)); mb(); }) | |
1da177e4 | 127 | |
da6b003a MD |
128 | #define __BUILD_MEMORY_STRING(bwlq, type) \ |
129 | \ | |
64c9627c | 130 | static inline void __raw_writes##bwlq(volatile void __iomem *mem, \ |
da6b003a MD |
131 | const void *addr, unsigned int count) \ |
132 | { \ | |
133 | const volatile type *__addr = addr; \ | |
134 | \ | |
135 | while (count--) { \ | |
136 | __raw_write##bwlq(*__addr, mem); \ | |
137 | __addr++; \ | |
138 | } \ | |
139 | } \ | |
140 | \ | |
64c9627c PM |
141 | static inline void __raw_reads##bwlq(volatile void __iomem *mem, \ |
142 | void *addr, unsigned int count) \ | |
da6b003a MD |
143 | { \ |
144 | volatile type *__addr = addr; \ | |
145 | \ | |
146 | while (count--) { \ | |
147 | *__addr = __raw_read##bwlq(mem); \ | |
148 | __addr++; \ | |
149 | } \ | |
150 | } | |
151 | ||
152 | __BUILD_MEMORY_STRING(b, u8) | |
153 | __BUILD_MEMORY_STRING(w, u16) | |
64c9627c PM |
154 | |
155 | #define writesb __raw_writesb | |
156 | #define writesw __raw_writesw | |
05ae9158 | 157 | #define writesl __raw_writesl |
64c9627c PM |
158 | |
159 | #define readsb __raw_readsb | |
160 | #define readsw __raw_readsw | |
05ae9158 PM |
161 | #define readsl __raw_readsl |
162 | ||
1da177e4 LT |
163 | #define readb_relaxed(a) readb(a) |
164 | #define readw_relaxed(a) readw(a) | |
165 | #define readl_relaxed(a) readl(a) | |
166 | ||
b66c1a39 | 167 | /* Simple MMIO */ |
64c9627c PM |
168 | #define ioread8(a) __raw_readb(a) |
169 | #define ioread16(a) __raw_readw(a) | |
b66c1a39 | 170 | #define ioread16be(a) be16_to_cpu(__raw_readw((a))) |
64c9627c | 171 | #define ioread32(a) __raw_readl(a) |
b66c1a39 | 172 | #define ioread32be(a) be32_to_cpu(__raw_readl((a))) |
1da177e4 | 173 | |
64c9627c PM |
174 | #define iowrite8(v,a) __raw_writeb((v),(a)) |
175 | #define iowrite16(v,a) __raw_writew((v),(a)) | |
b66c1a39 | 176 | #define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a)) |
64c9627c | 177 | #define iowrite32(v,a) __raw_writel((v),(a)) |
b66c1a39 PM |
178 | #define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a)) |
179 | ||
64c9627c PM |
180 | #define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c)) |
181 | #define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c)) | |
182 | #define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c)) | |
b66c1a39 | 183 | |
64c9627c PM |
184 | #define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c)) |
185 | #define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c)) | |
186 | #define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c)) | |
b66c1a39 PM |
187 | |
188 | #define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */ | |
1da177e4 | 189 | |
0f2c15ce PM |
190 | #define IO_SPACE_LIMIT 0xffffffff |
191 | ||
fa43972f PM |
192 | extern unsigned long generic_io_base; |
193 | ||
1da177e4 LT |
194 | /* |
195 | * This function provides a method for the generic case where a board-specific | |
b66c1a39 | 196 | * ioport_map simply needs to return the port + some arbitrary port base. |
1da177e4 LT |
197 | * |
198 | * We use this at board setup time to implicitly set the port base, and | |
b66c1a39 | 199 | * as a result, we can use the generic ioport_map. |
1da177e4 LT |
200 | */ |
201 | static inline void __set_io_port_base(unsigned long pbase) | |
202 | { | |
1da177e4 LT |
203 | generic_io_base = pbase; |
204 | } | |
205 | ||
e7cc9a73 MD |
206 | #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n)) |
207 | ||
1da177e4 | 208 | /* We really want to try and get these to memcpy etc */ |
b66c1a39 PM |
209 | extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long); |
210 | extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long); | |
211 | extern void memset_io(volatile void __iomem *, int, unsigned long); | |
1da177e4 LT |
212 | |
213 | /* SuperH on-chip I/O functions */ | |
b66c1a39 | 214 | static inline unsigned char ctrl_inb(unsigned long addr) |
1da177e4 LT |
215 | { |
216 | return *(volatile unsigned char*)addr; | |
217 | } | |
218 | ||
b66c1a39 | 219 | static inline unsigned short ctrl_inw(unsigned long addr) |
1da177e4 LT |
220 | { |
221 | return *(volatile unsigned short*)addr; | |
222 | } | |
223 | ||
b66c1a39 | 224 | static inline unsigned int ctrl_inl(unsigned long addr) |
1da177e4 LT |
225 | { |
226 | return *(volatile unsigned long*)addr; | |
227 | } | |
228 | ||
0f2c15ce PM |
229 | static inline unsigned long long ctrl_inq(unsigned long addr) |
230 | { | |
231 | return *(volatile unsigned long long*)addr; | |
232 | } | |
233 | ||
b66c1a39 | 234 | static inline void ctrl_outb(unsigned char b, unsigned long addr) |
1da177e4 LT |
235 | { |
236 | *(volatile unsigned char*)addr = b; | |
237 | } | |
238 | ||
b66c1a39 | 239 | static inline void ctrl_outw(unsigned short b, unsigned long addr) |
1da177e4 LT |
240 | { |
241 | *(volatile unsigned short*)addr = b; | |
242 | } | |
243 | ||
b66c1a39 | 244 | static inline void ctrl_outl(unsigned int b, unsigned long addr) |
1da177e4 LT |
245 | { |
246 | *(volatile unsigned long*)addr = b; | |
247 | } | |
248 | ||
0f2c15ce PM |
249 | static inline void ctrl_outq(unsigned long long b, unsigned long addr) |
250 | { | |
251 | *(volatile unsigned long long*)addr = b; | |
252 | } | |
253 | ||
959f85f8 PM |
254 | static inline void ctrl_delay(void) |
255 | { | |
da06b8d0 | 256 | #ifdef P2SEG |
959f85f8 | 257 | ctrl_inw(P2SEG); |
da06b8d0 | 258 | #endif |
959f85f8 PM |
259 | } |
260 | ||
ac490a48 PM |
261 | /* Quad-word real-mode I/O, don't ask.. */ |
262 | unsigned long long peek_real_address_q(unsigned long long addr); | |
263 | unsigned long long poke_real_address_q(unsigned long long addr, | |
264 | unsigned long long val); | |
265 | ||
da06b8d0 PM |
266 | #if !defined(CONFIG_MMU) |
267 | #define virt_to_phys(address) ((unsigned long)(address)) | |
268 | #define phys_to_virt(address) ((void *)(address)) | |
d02b08f6 | 269 | #else |
da06b8d0 PM |
270 | #define virt_to_phys(address) (__pa(address)) |
271 | #define phys_to_virt(address) (__va(address)) | |
a2d1a5fa | 272 | #endif |
1da177e4 | 273 | |
1da177e4 | 274 | /* |
da06b8d0 PM |
275 | * On 32-bit SH, we traditionally have the whole physical address space |
276 | * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do | |
277 | * not need to do anything but place the address in the proper segment. | |
278 | * This is true for P1 and P2 addresses, as well as some P3 ones. | |
279 | * However, most of the P3 addresses and newer cores using extended | |
280 | * addressing need to map through page tables, so the ioremap() | |
281 | * implementation becomes a bit more complicated. | |
1da177e4 | 282 | * |
da06b8d0 | 283 | * See arch/sh/mm/ioremap.c for additional notes on this. |
1da177e4 LT |
284 | * |
285 | * We cheat a bit and always return uncachable areas until we've fixed | |
b66c1a39 | 286 | * the drivers to handle caching properly. |
da06b8d0 PM |
287 | * |
288 | * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply | |
289 | * doesn't exist, so everything must go through page tables. | |
1da177e4 | 290 | */ |
b66c1a39 PM |
291 | #ifdef CONFIG_MMU |
292 | void __iomem *__ioremap(unsigned long offset, unsigned long size, | |
293 | unsigned long flags); | |
294 | void __iounmap(void __iomem *addr); | |
ccd80587 PM |
295 | |
296 | /* arch/sh/mm/ioremap_64.c */ | |
297 | unsigned long onchip_remap(unsigned long addr, unsigned long size, | |
298 | const char *name); | |
299 | extern void onchip_unmap(unsigned long vaddr); | |
b66c1a39 PM |
300 | #else |
301 | #define __ioremap(offset, size, flags) ((void __iomem *)(offset)) | |
302 | #define __iounmap(addr) do { } while (0) | |
ccd80587 PM |
303 | #define onchip_remap(addr, size, name) (addr) |
304 | #define onchip_unmap(addr) do { } while (0) | |
b66c1a39 PM |
305 | #endif /* CONFIG_MMU */ |
306 | ||
307 | static inline void __iomem * | |
308 | __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) | |
1da177e4 | 309 | { |
da06b8d0 | 310 | #ifdef CONFIG_SUPERH32 |
b66c1a39 | 311 | unsigned long last_addr = offset + size - 1; |
e7cc9a73 MD |
312 | #endif |
313 | void __iomem *ret; | |
b66c1a39 | 314 | |
e7cc9a73 MD |
315 | ret = __ioremap_trapped(offset, size); |
316 | if (ret) | |
317 | return ret; | |
318 | ||
319 | #ifdef CONFIG_SUPERH32 | |
b66c1a39 PM |
320 | /* |
321 | * For P1 and P2 space this is trivial, as everything is already | |
322 | * mapped. Uncached access for P1 addresses are done through P2. | |
323 | * In the P3 case or for addresses outside of the 29-bit space, | |
324 | * mapping must be done by the PMB or by using page tables. | |
325 | */ | |
326 | if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { | |
327 | if (unlikely(flags & _PAGE_CACHABLE)) | |
328 | return (void __iomem *)P1SEGADDR(offset); | |
329 | ||
330 | return (void __iomem *)P2SEGADDR(offset); | |
331 | } | |
da06b8d0 | 332 | #endif |
b66c1a39 PM |
333 | |
334 | return __ioremap(offset, size, flags); | |
1da177e4 LT |
335 | } |
336 | ||
b66c1a39 PM |
337 | #define ioremap(offset, size) \ |
338 | __ioremap_mode((offset), (size), 0) | |
339 | #define ioremap_nocache(offset, size) \ | |
340 | __ioremap_mode((offset), (size), 0) | |
341 | #define ioremap_cache(offset, size) \ | |
342 | __ioremap_mode((offset), (size), _PAGE_CACHABLE) | |
343 | #define p3_ioremap(offset, size, flags) \ | |
344 | __ioremap((offset), (size), (flags)) | |
cb700aa4 PM |
345 | #define ioremap_prot(offset, size, flags) \ |
346 | __ioremap_mode((offset), (size), (flags)) | |
b66c1a39 PM |
347 | #define iounmap(addr) \ |
348 | __iounmap((addr)) | |
349 | ||
1da177e4 LT |
350 | /* |
351 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
352 | * access | |
353 | */ | |
354 | #define xlate_dev_mem_ptr(p) __va(p) | |
355 | ||
356 | /* | |
357 | * Convert a virtual cached pointer to an uncached pointer | |
358 | */ | |
359 | #define xlate_dev_kmem_ptr(p) p | |
360 | ||
361 | #endif /* __KERNEL__ */ | |
362 | ||
363 | #endif /* __ASM_SH_IO_H */ |