Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef __ASM_SH_PROCESSOR_H |
2 | #define __ASM_SH_PROCESSOR_H | |
1da177e4 | 3 | |
76168c21 | 4 | #include <asm/cpu-features.h> |
02f7e627 | 5 | #include <asm/segment.h> |
81b66995 | 6 | #include <asm/cache.h> |
76168c21 | 7 | |
343ac722 | 8 | #ifndef __ASSEMBLY__ |
1da177e4 LT |
9 | /* |
10 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
11 | * | |
12 | * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry | |
de02797a | 13 | * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c |
1da177e4 LT |
14 | * for parsing the subtype in get_cpu_subtype(). |
15 | */ | |
16 | enum cpu_type { | |
17 | /* SH-2 types */ | |
b9601c5e | 18 | CPU_SH7619, |
b229632a YS |
19 | |
20 | /* SH-2A types */ | |
2825999e | 21 | CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG, |
1da177e4 LT |
22 | |
23 | /* SH-3 types */ | |
e5723e0e PM |
24 | CPU_SH7705, CPU_SH7706, CPU_SH7707, |
25 | CPU_SH7708, CPU_SH7708S, CPU_SH7708R, | |
9465a54f | 26 | CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, |
31a49c4b | 27 | CPU_SH7720, CPU_SH7721, CPU_SH7729, |
1da177e4 LT |
28 | |
29 | /* SH-4 types */ | |
30 | CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, | |
f9669187 | 31 | CPU_SH7760, CPU_SH4_202, CPU_SH4_501, |
b552c7e8 PM |
32 | |
33 | /* SH-4A types */ | |
55ba99eb | 34 | CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, |
c01f0f1a | 35 | CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, |
41504c39 PM |
36 | |
37 | /* SH4AL-DSP types */ | |
9109a30e | 38 | CPU_SH7343, CPU_SH7722, CPU_SH7366, |
1da177e4 | 39 | |
af3c7dfe PM |
40 | /* SH-5 types */ |
41 | CPU_SH5_101, CPU_SH5_103, | |
42 | ||
1da177e4 LT |
43 | /* Unknown subtype */ |
44 | CPU_SH_NONE | |
45 | }; | |
46 | ||
e82da214 PM |
47 | enum cpu_family { |
48 | CPU_FAMILY_SH2, | |
49 | CPU_FAMILY_SH2A, | |
50 | CPU_FAMILY_SH3, | |
51 | CPU_FAMILY_SH4, | |
52 | CPU_FAMILY_SH4A, | |
53 | CPU_FAMILY_SH4AL_DSP, | |
54 | CPU_FAMILY_SH5, | |
55 | CPU_FAMILY_UNKNOWN, | |
56 | }; | |
57 | ||
81b66995 PM |
58 | /* |
59 | * TLB information structure | |
60 | * | |
61 | * Defined for both I and D tlb, per-processor. | |
62 | */ | |
63 | struct tlb_info { | |
64 | unsigned long long next; | |
65 | unsigned long long first; | |
66 | unsigned long long last; | |
67 | ||
68 | unsigned int entries; | |
69 | unsigned int step; | |
70 | ||
71 | unsigned long flags; | |
72 | }; | |
73 | ||
74 | struct sh_cpuinfo { | |
e82da214 | 75 | unsigned int type, family; |
81b66995 PM |
76 | int cut_major, cut_minor; |
77 | unsigned long loops_per_jiffy; | |
78 | unsigned long asid_cache; | |
79 | ||
80 | struct cache_info icache; /* Primary I-cache */ | |
81 | struct cache_info dcache; /* Primary D-cache */ | |
82 | struct cache_info scache; /* Secondary cache */ | |
83 | ||
84 | /* TLB info */ | |
85 | struct tlb_info itlb; | |
86 | struct tlb_info dtlb; | |
87 | ||
88 | unsigned long flags; | |
89 | } __attribute__ ((aligned(L1_CACHE_BYTES))); | |
90 | ||
91 | extern struct sh_cpuinfo cpu_data[]; | |
92 | #define boot_cpu_data cpu_data[0] | |
93 | #define current_cpu_data cpu_data[smp_processor_id()] | |
94 | #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] | |
95 | ||
eb67cf14 PM |
96 | #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") |
97 | #define cpu_relax() barrier() | |
98 | ||
343ac722 | 99 | /* Forward decl */ |
fa43972f | 100 | struct seq_operations; |
3ef2932b | 101 | struct task_struct; |
fa43972f PM |
102 | |
103 | extern struct pt_regs fake_swapper_regs; | |
19f9a34f | 104 | |
3ef2932b PM |
105 | /* arch/sh/kernel/process.c */ |
106 | extern unsigned int xstate_size; | |
107 | extern void free_thread_xstate(struct task_struct *); | |
108 | extern struct kmem_cache *task_xstate_cachep; | |
109 | ||
d9b9487a PM |
110 | /* arch/sh/mm/init.c */ |
111 | extern unsigned int mem_init_done; | |
112 | ||
11c19656 PM |
113 | /* arch/sh/kernel/setup.c */ |
114 | const char *get_cpu_subtype(struct sh_cpuinfo *c); | |
fa43972f | 115 | extern const struct seq_operations cpuinfo_op; |
11c19656 | 116 | |
eb9b9b56 | 117 | /* processor boot mode configuration */ |
0d4fdbb6 MD |
118 | #define MODE_PIN0 (1 << 0) |
119 | #define MODE_PIN1 (1 << 1) | |
120 | #define MODE_PIN2 (1 << 2) | |
121 | #define MODE_PIN3 (1 << 3) | |
122 | #define MODE_PIN4 (1 << 4) | |
123 | #define MODE_PIN5 (1 << 5) | |
124 | #define MODE_PIN6 (1 << 6) | |
125 | #define MODE_PIN7 (1 << 7) | |
126 | #define MODE_PIN8 (1 << 8) | |
127 | #define MODE_PIN9 (1 << 9) | |
128 | #define MODE_PIN10 (1 << 10) | |
129 | #define MODE_PIN11 (1 << 11) | |
130 | #define MODE_PIN12 (1 << 12) | |
131 | #define MODE_PIN13 (1 << 13) | |
132 | #define MODE_PIN14 (1 << 14) | |
133 | #define MODE_PIN15 (1 << 15) | |
134 | ||
eb9b9b56 MD |
135 | int generic_mode_pins(void); |
136 | int test_mode_pin(int pin); | |
137 | ||
acb499f0 PM |
138 | #ifdef CONFIG_VSYSCALL |
139 | int vsyscall_init(void); | |
140 | #else | |
141 | #define vsyscall_init() do { } while (0) | |
142 | #endif | |
143 | ||
343ac722 PM |
144 | #endif /* __ASSEMBLY__ */ |
145 | ||
146 | #ifdef CONFIG_SUPERH32 | |
147 | # include "processor_32.h" | |
148 | #else | |
149 | # include "processor_64.h" | |
150 | #endif | |
151 | ||
1da177e4 | 152 | #endif /* __ASM_SH_PROCESSOR_H */ |