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1da177e4 LT |
1 | /* |
2 | * include/asm-sh/cpu-sh4/mmu_context.h | |
3 | * | |
4 | * Copyright (C) 1999 Niibe Yutaka | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H | |
11 | #define __ASM_CPU_SH4_MMU_CONTEXT_H | |
12 | ||
13 | #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ | |
14 | #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ | |
15 | #define MMU_TTB 0xFF000008 /* Translation table base register */ | |
16 | #define MMU_TEA 0xFF00000C /* TLB Exception Address */ | |
8263a67e PM |
17 | #define MMU_PTEA 0xFF000034 /* PTE assistance register */ |
18 | #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ | |
1da177e4 LT |
19 | |
20 | #define MMUCR 0xFF000010 /* MMU Control Register */ | |
21 | ||
1da177e4 | 22 | #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 |
8263a67e | 23 | #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 |
1da177e4 LT |
24 | #define MMU_PAGE_ASSOC_BIT 0x80 |
25 | ||
eddeeb32 SM |
26 | #define MMUCR_TI (1<<2) |
27 | ||
8eda5514 MF |
28 | #define MMUCR_URB 0x00FC0000 |
29 | #define MMUCR_URB_SHIFT 18 | |
30 | #define MMUCR_URB_NENTRIES 64 | |
31 | ||
d02b08f6 SM |
32 | #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) |
33 | #define MMUCR_SE (1 << 4) | |
34 | #else | |
35 | #define MMUCR_SE (0) | |
36 | #endif | |
37 | ||
8263a67e PM |
38 | #ifdef CONFIG_CPU_HAS_PTEAEX |
39 | #define MMUCR_AEX (1 << 6) | |
40 | #else | |
41 | #define MMUCR_AEX (0) | |
42 | #endif | |
43 | ||
44 | #ifdef CONFIG_X2TLB | |
45 | #define MMUCR_ME (1 << 7) | |
46 | #else | |
47 | #define MMUCR_ME (0) | |
48 | #endif | |
49 | ||
091904ae | 50 | #ifdef CONFIG_SH_STORE_QUEUES |
d04a0f79 | 51 | #define MMUCR_SQMD (1 << 9) |
091904ae | 52 | #else |
d04a0f79 | 53 | #define MMUCR_SQMD (0) |
091904ae | 54 | #endif |
1da177e4 | 55 | |
d04a0f79 | 56 | #define MMU_NTLB_ENTRIES 64 |
8263a67e | 57 | #define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX) |
1da177e4 | 58 | |
091904ae PM |
59 | #define TRA 0xff000020 |
60 | #define EXPEVT 0xff000024 | |
61 | #define INTEVT 0xff000028 | |
62 | ||
1da177e4 LT |
63 | #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ |
64 |