[deliverable/linux.git] / arch / sh / kernel / cpu / irq / intc-sh5.c

/*
 * arch/sh/kernel/cpu/irq/intc-sh5.c
 *
 * Interrupt Controller support for SH5 INTC.
 *
 * Copyright (C) 2000, 2001  Paolo Alberelli
 * Copyright (C) 2003  Paul Mundt
 *
 * Per-interrupt selective. IRLM=0 (Fixed priority) is not
 * supported being useless without a cascaded interrupt
 * controller.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <cpu/irq.h>
#include <asm/page.h>

/*
 * Maybe the generic Peripheral block could move to a more
 * generic include file. INTC Block will be defined here
 * and only here to make INTC self-contained in a single
 * file.
 */
#define	INTC_BLOCK_OFFSET	0x01000000

/* Base */
#define INTC_BASE		PHYS_PERIPHERAL_BLOCK + \
				INTC_BLOCK_OFFSET

/* Address */
#define INTC_ICR_SET		(intc_virt + 0x0)
#define INTC_ICR_CLEAR		(intc_virt + 0x8)
#define INTC_INTPRI_0		(intc_virt + 0x10)
#define INTC_INTSRC_0		(intc_virt + 0x50)
#define INTC_INTSRC_1		(intc_virt + 0x58)
#define INTC_INTREQ_0		(intc_virt + 0x60)
#define INTC_INTREQ_1		(intc_virt + 0x68)
#define INTC_INTENB_0		(intc_virt + 0x70)
#define INTC_INTENB_1		(intc_virt + 0x78)
#define INTC_INTDSB_0		(intc_virt + 0x80)
#define INTC_INTDSB_1		(intc_virt + 0x88)

#define INTC_ICR_IRLM		0x1
#define	INTC_INTPRI_PREGS	8		/* 8 Priority Registers */
#define	INTC_INTPRI_PPREG	8		/* 8 Priorities per Register */


/*
 * Mapper between the vector ordinal and the IRQ number
 * passed to kernel/device drivers.
 */
int intc_evt_to_irq[(0xE20/0x20)+1] = {
	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0x000 - 0x0E0 */
	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0x100 - 0x1E0 */
	 0,  0,  0,  0,  0,  1,  0,  0,	/* 0x200 - 0x2E0 */
	 2,  0,  0,  3,  0,  0,  0, -1,	/* 0x300 - 0x3E0 */
	32, 33, 34, 35, 36, 37, 38, -1,	/* 0x400 - 0x4E0 */
	-1, -1, -1, 63, -1, -1, -1, -1,	/* 0x500 - 0x5E0 */
	-1, -1, 18, 19, 20, 21, 22, -1,	/* 0x600 - 0x6E0 */
	39, 40, 41, 42, -1, -1, -1, -1,	/* 0x700 - 0x7E0 */
	 4,  5,  6,  7, -1, -1, -1, -1,	/* 0x800 - 0x8E0 */
	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0x900 - 0x9E0 */
	12, 13, 14, 15, 16, 17, -1, -1,	/* 0xA00 - 0xAE0 */
	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0xB00 - 0xBE0 */
	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0xC00 - 0xCE0 */
	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0xD00 - 0xDE0 */
	-1, -1				/* 0xE00 - 0xE20 */
};

static unsigned long intc_virt;

static unsigned int startup_intc_irq(unsigned int irq);
static void shutdown_intc_irq(unsigned int irq);
static void enable_intc_irq(unsigned int irq);
static void disable_intc_irq(unsigned int irq);
static void mask_and_ack_intc(unsigned int);
static void end_intc_irq(unsigned int irq);

static struct irq_chip intc_irq_type = {
	.name = "INTC",
	.startup = startup_intc_irq,
	.shutdown = shutdown_intc_irq,
	.enable = enable_intc_irq,
	.disable = disable_intc_irq,
	.ack = mask_and_ack_intc,
	.end = end_intc_irq
};

static int irlm;		/* IRL mode */

static unsigned int startup_intc_irq(unsigned int irq)
{
	enable_intc_irq(irq);
	return 0; /* never anything pending */
}

static void shutdown_intc_irq(unsigned int irq)
{
	disable_intc_irq(irq);
}

static void enable_intc_irq(unsigned int irq)
{
	unsigned long reg;
	unsigned long bitmask;

	if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
		printk("Trying to use straight IRL0-3 with an encoding platform.\n");

	if (irq < 32) {
		reg = INTC_INTENB_0;
		bitmask = 1 << irq;
	} else {
		reg = INTC_INTENB_1;
		bitmask = 1 << (irq - 32);
	}

	__raw_writel(bitmask, reg);
}

static void disable_intc_irq(unsigned int irq)
{
	unsigned long reg;
	unsigned long bitmask;

	if (irq < 32) {
		reg = INTC_INTDSB_0;
		bitmask = 1 << irq;
	} else {
		reg = INTC_INTDSB_1;
		bitmask = 1 << (irq - 32);
	}

	__raw_writel(bitmask, reg);
}

static void mask_and_ack_intc(unsigned int irq)
{
	disable_intc_irq(irq);
}

static void end_intc_irq(unsigned int irq)
{
	enable_intc_irq(irq);
}

void __init plat_irq_setup(void)
{
	unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
	unsigned long reg;
	int i;

	intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
	if (!intc_virt) {
		panic("Unable to remap INTC\n");
	}


	/* Set default: per-line enable/disable, priority driven ack/eoi */
	for (i = 0; i < NR_INTC_IRQS; i++)
		set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);


	/* Disable all interrupts and set all priorities to 0 to avoid trouble */
	__raw_writel(-1, INTC_INTDSB_0);
	__raw_writel(-1, INTC_INTDSB_1);

	for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
		__raw_writel( NO_PRIORITY, reg);


#ifdef CONFIG_SH_CAYMAN
	{
		unsigned long data;

		/* Set IRLM */
		/* If all the priorities are set to 'no priority', then
		 * assume we are using encoded mode.
		 */
		irlm = platform_int_priority[IRQ_IRL0] +
		       platform_int_priority[IRQ_IRL1] +
		       platform_int_priority[IRQ_IRL2] +
		       platform_int_priority[IRQ_IRL3];
		if (irlm == NO_PRIORITY) {
			/* IRLM = 0 */
			reg = INTC_ICR_CLEAR;
			i = IRQ_INTA;
			printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
		} else {
			/* IRLM = 1 */
			reg = INTC_ICR_SET;
			i = IRQ_IRL0;
		}
		__raw_writel(INTC_ICR_IRLM, reg);

		/* Set interrupt priorities according to platform description */
		for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
			data |= platform_int_priority[i] <<
				((i % INTC_INTPRI_PPREG) * 4);
			if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
				/* Upon the 7th, set Priority Register */
				__raw_writel(data, reg);
				data = 0;
				reg += 8;
			}
		}
	}
#endif

	/*
	 * And now let interrupts come in.
	 * sti() is not enough, we need to
	 * lower priority, too.
	 */
        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
                             "and       %0, %1, %0\n\t"
                             "putcon    %0, " __SR "\n\t"
                             : "=&r" (__dummy0)
                             : "r" (__dummy1));
}
Commit	Line	Data
1da177e4	1	/*
a23ba435	2	* arch/sh/kernel/cpu/irq/intc-sh5.c
1da177e4	3	*
a23ba435	4	* Interrupt Controller support for SH5 INTC.
1da177e4 LT	5	*
	6	* Copyright (C) 2000, 2001 Paolo Alberelli
	7	* Copyright (C) 2003 Paul Mundt
	8	*
1da177e4 LT	9	* Per-interrupt selective. IRLM=0 (Fixed priority) is not
	10	* supported being useless without a cascaded interrupt
	11	* controller.
	12	*
a23ba435 PM	13	* This file is subject to the terms and conditions of the GNU General Public
	14	* License. See the file "COPYING" in the main directory of this archive
	15	* for more details.
1da177e4	16	*/
1da177e4	17	#include <linux/init.h>
da9d5108	18	#include <linux/interrupt.h>
1da177e4	19	#include <linux/irq.h>
18bc8131	20	#include <linux/io.h>
1da177e4	21	#include <linux/kernel.h>
18bc8131	22	#include <linux/bitops.h>
f15cbe6f	23	#include <cpu/irq.h>
1da177e4	24	#include <asm/page.h>
1da177e4 LT	25
	26	/*
	27	* Maybe the generic Peripheral block could move to a more
	28	* generic include file. INTC Block will be defined here
	29	* and only here to make INTC self-contained in a single
	30	* file.
	31	*/
	32	#define INTC_BLOCK_OFFSET 0x01000000
	33
	34	/* Base */
	35	#define INTC_BASE PHYS_PERIPHERAL_BLOCK + \
	36	INTC_BLOCK_OFFSET
	37
	38	/* Address */
	39	#define INTC_ICR_SET (intc_virt + 0x0)
	40	#define INTC_ICR_CLEAR (intc_virt + 0x8)
	41	#define INTC_INTPRI_0 (intc_virt + 0x10)
	42	#define INTC_INTSRC_0 (intc_virt + 0x50)
	43	#define INTC_INTSRC_1 (intc_virt + 0x58)
	44	#define INTC_INTREQ_0 (intc_virt + 0x60)
	45	#define INTC_INTREQ_1 (intc_virt + 0x68)
	46	#define INTC_INTENB_0 (intc_virt + 0x70)
	47	#define INTC_INTENB_1 (intc_virt + 0x78)
	48	#define INTC_INTDSB_0 (intc_virt + 0x80)
	49	#define INTC_INTDSB_1 (intc_virt + 0x88)
	50
	51	#define INTC_ICR_IRLM 0x1
	52	#define INTC_INTPRI_PREGS 8 /* 8 Priority Registers */
	53	#define INTC_INTPRI_PPREG 8 /* 8 Priorities per Register */
	54
	55
	56	/*
	57	* Mapper between the vector ordinal and the IRQ number
	58	* passed to kernel/device drivers.
	59	*/
	60	int intc_evt_to_irq[(0xE20/0x20)+1] = {
	61	-1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */
	62	-1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */
	63	0, 0, 0, 0, 0, 1, 0, 0, /* 0x200 - 0x2E0 */
	64	2, 0, 0, 3, 0, 0, 0, -1, /* 0x300 - 0x3E0 */
	65	32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */
	66	-1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */
	67	-1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */
	68	39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */
	69	4, 5, 6, 7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */
	70	-1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */
	71	12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */
	72	-1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */
	73	-1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */
	74	-1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */
	75	-1, -1 /* 0xE00 - 0xE20 */
	76	};
	77
1da177e4 LT	78	static unsigned long intc_virt;
	79
	80	static unsigned int startup_intc_irq(unsigned int irq);
	81	static void shutdown_intc_irq(unsigned int irq);
	82	static void enable_intc_irq(unsigned int irq);
	83	static void disable_intc_irq(unsigned int irq);
	84	static void mask_and_ack_intc(unsigned int);
	85	static void end_intc_irq(unsigned int irq);
	86
d8049839	87	static struct irq_chip intc_irq_type = {
648f1534	88	.name = "INTC",
c05e0664 TG	89	.startup = startup_intc_irq,
	90	.shutdown = shutdown_intc_irq,
	91	.enable = enable_intc_irq,
	92	.disable = disable_intc_irq,
	93	.ack = mask_and_ack_intc,
	94	.end = end_intc_irq
1da177e4 LT	95	};
	96
	97	static int irlm; /* IRL mode */
	98
	99	static unsigned int startup_intc_irq(unsigned int irq)
	100	{
	101	enable_intc_irq(irq);
	102	return 0; /* never anything pending */
	103	}
	104
	105	static void shutdown_intc_irq(unsigned int irq)
	106	{
	107	disable_intc_irq(irq);
	108	}
	109
	110	static void enable_intc_irq(unsigned int irq)
	111	{
	112	unsigned long reg;
	113	unsigned long bitmask;
	114
	115	if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
	116	printk("Trying to use straight IRL0-3 with an encoding platform.\n");
	117
	118	if (irq < 32) {
	119	reg = INTC_INTENB_0;
	120	bitmask = 1 << irq;
	121	} else {
	122	reg = INTC_INTENB_1;
	123	bitmask = 1 << (irq - 32);
	124	}
	125
9d56dd3b	126	__raw_writel(bitmask, reg);
1da177e4 LT	127	}
	128
	129	static void disable_intc_irq(unsigned int irq)
	130	{
	131	unsigned long reg;
	132	unsigned long bitmask;
	133
	134	if (irq < 32) {
	135	reg = INTC_INTDSB_0;
	136	bitmask = 1 << irq;
	137	} else {
	138	reg = INTC_INTDSB_1;
	139	bitmask = 1 << (irq - 32);
	140	}
	141
9d56dd3b	142	__raw_writel(bitmask, reg);
1da177e4 LT	143	}
	144
	145	static void mask_and_ack_intc(unsigned int irq)
	146	{
	147	disable_intc_irq(irq);
	148	}
	149
	150	static void end_intc_irq(unsigned int irq)
	151	{
	152	enable_intc_irq(irq);
	153	}
	154
18bc8131	155	void __init plat_irq_setup(void)
1da177e4	156	{
a1dc4b59	157	unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
1da177e4	158	unsigned long reg;
1da177e4 LT	159	int i;
1da177e4 LT	160
0fb849b9	161	intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
1da177e4 LT	162	if (!intc_virt) {
	163	panic("Unable to remap INTC\n");
	164	}
	165
	166
	167	/* Set default: per-line enable/disable, priority driven ack/eoi */
a1dc4b59	168	for (i = 0; i < NR_INTC_IRQS; i++)
fa1d43ab	169	set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
1da177e4 LT	170
	171
	172	/* Disable all interrupts and set all priorities to 0 to avoid trouble */
9d56dd3b PM	173	__raw_writel(-1, INTC_INTDSB_0);
9d56dd3b PM	174	__raw_writel(-1, INTC_INTDSB_1);
1da177e4 LT	175
1da177e4 LT	176	for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
9d56dd3b	177	__raw_writel( NO_PRIORITY, reg);
1da177e4 LT	178
1da177e4 LT	179
a1dc4b59 PM	180	#ifdef CONFIG_SH_CAYMAN
	181	{
	182	unsigned long data;
	183
	184	/* Set IRLM */
	185	/* If all the priorities are set to 'no priority', then
	186	* assume we are using encoded mode.
	187	*/
	188	irlm = platform_int_priority[IRQ_IRL0] +
	189	platform_int_priority[IRQ_IRL1] +
	190	platform_int_priority[IRQ_IRL2] +
	191	platform_int_priority[IRQ_IRL3];
	192	if (irlm == NO_PRIORITY) {
	193	/* IRLM = 0 */
	194	reg = INTC_ICR_CLEAR;
	195	i = IRQ_INTA;
	196	printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
	197	} else {
	198	/* IRLM = 1 */
	199	reg = INTC_ICR_SET;
	200	i = IRQ_IRL0;
1da177e4	201	}
9d56dd3b	202	__raw_writel(INTC_ICR_IRLM, reg);
a1dc4b59 PM	203
	204	/* Set interrupt priorities according to platform description */
	205	for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
	206	data \|= platform_int_priority[i] <<
	207	((i % INTC_INTPRI_PPREG) * 4);
	208	if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
	209	/* Upon the 7th, set Priority Register */
9d56dd3b	210	__raw_writel(data, reg);
a1dc4b59 PM	211	data = 0;
	212	reg += 8;
	213	}
	214	}
2beb0e28	215	}
a1dc4b59	216	#endif
1da177e4	217
1da177e4 LT	218	/*
	219	* And now let interrupts come in.
	220	* sti() is not enough, we need to
	221	* lower priority, too.
	222	*/
	223	__asm__ __volatile__("getcon " __SR ", %0\n\t"
	224	"and %0, %1, %0\n\t"
	225	"putcon %0, " __SR "\n\t"
	226	: "=&r" (__dummy0)
	227	: "r" (__dummy1));
	228	}