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6d01f510 | 1 | /* |
a8f67f4b | 2 | * SH7203 and SH7263 Setup |
6d01f510 | 3 | * |
bb943a28 | 4 | * Copyright (C) 2007 - 2009 Paul Mundt |
6d01f510 PM |
5 | * |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/serial.h> | |
96de1a8f | 13 | #include <linux/serial_sci.h> |
46a12f74 | 14 | #include <linux/sh_timer.h> |
698aa99d | 15 | #include <linux/io.h> |
6d01f510 PM |
16 | |
17 | enum { | |
18 | UNUSED = 0, | |
19 | ||
20 | /* interrupt sources */ | |
21 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
22 | PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, | |
bb943a28 | 23 | DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, |
6d01f510 | 24 | USB, LCDC, CMT0, CMT1, BSC, WDT, |
bb943a28 PM |
25 | |
26 | MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, | |
27 | MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V, | |
28 | ||
6d01f510 | 29 | ADC_ADI, |
bb943a28 PM |
30 | |
31 | IIC30, IIC31, IIC32, IIC33, | |
32 | SCIF0, SCIF1, SCIF2, SCIF3, | |
33 | ||
34 | SSU0, SSU1, | |
35 | ||
6d01f510 | 36 | SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, |
a8f67f4b PM |
37 | |
38 | /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ | |
e45efe68 PM |
39 | ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1, |
40 | SRC, IEBI, | |
a8f67f4b | 41 | |
6d01f510 | 42 | /* interrupt groups */ |
e45efe68 | 43 | PINT, |
6d01f510 PM |
44 | }; |
45 | ||
46 | static struct intc_vect vectors[] __initdata = { | |
47 | INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), | |
48 | INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), | |
49 | INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), | |
50 | INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), | |
51 | INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), | |
52 | INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), | |
53 | INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), | |
54 | INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), | |
bb943a28 PM |
55 | INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), |
56 | INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), | |
57 | INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), | |
58 | INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), | |
59 | INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), | |
60 | INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), | |
61 | INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), | |
62 | INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), | |
6d01f510 PM |
63 | INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), |
64 | INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), | |
65 | INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), | |
bb943a28 PM |
66 | INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147), |
67 | INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149), | |
68 | INTC_IRQ(MTU0_VEF, 150), | |
69 | INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152), | |
70 | INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154), | |
71 | INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156), | |
72 | INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158), | |
73 | INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160), | |
74 | INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162), | |
75 | INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164), | |
6d01f510 | 76 | INTC_IRQ(MTU2_TCI3V, 165), |
bb943a28 PM |
77 | INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167), |
78 | INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169), | |
6d01f510 PM |
79 | INTC_IRQ(MTU2_TCI4V, 170), |
80 | INTC_IRQ(ADC_ADI, 171), | |
bb943a28 PM |
81 | INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173), |
82 | INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175), | |
83 | INTC_IRQ(IIC30, 176), | |
84 | INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178), | |
85 | INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180), | |
86 | INTC_IRQ(IIC31, 181), | |
87 | INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183), | |
88 | INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185), | |
89 | INTC_IRQ(IIC32, 186), | |
90 | INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188), | |
91 | INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190), | |
92 | INTC_IRQ(IIC33, 191), | |
93 | INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193), | |
94 | INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195), | |
95 | INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197), | |
96 | INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199), | |
97 | INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201), | |
98 | INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203), | |
99 | INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205), | |
100 | INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207), | |
101 | INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209), | |
102 | INTC_IRQ(SSU0, 210), | |
103 | INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212), | |
104 | INTC_IRQ(SSU1, 213), | |
6d01f510 PM |
105 | INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), |
106 | INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), | |
bb943a28 PM |
107 | INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225), |
108 | INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227), | |
109 | INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232), | |
110 | INTC_IRQ(RTC, 233), | |
111 | INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235), | |
112 | INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237), | |
113 | INTC_IRQ(RCAN0, 238), | |
114 | INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240), | |
115 | INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242), | |
116 | INTC_IRQ(RCAN1, 243), | |
a8f67f4b PM |
117 | |
118 | /* SH7263-specific trash */ | |
119 | #ifdef CONFIG_CPU_SUBTYPE_SH7263 | |
e45efe68 PM |
120 | INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219), |
121 | INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221), | |
122 | INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223), | |
a8f67f4b | 123 | |
e45efe68 PM |
124 | INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229), |
125 | INTC_IRQ(SDHI, 230), | |
a8f67f4b | 126 | |
e45efe68 PM |
127 | INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245), |
128 | INTC_IRQ(SRC, 246), | |
a8f67f4b PM |
129 | |
130 | INTC_IRQ(IEBI, 247), | |
131 | #endif | |
6d01f510 PM |
132 | }; |
133 | ||
134 | static struct intc_group groups[] __initdata = { | |
135 | INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, | |
136 | PINT4, PINT5, PINT6, PINT7), | |
6d01f510 PM |
137 | }; |
138 | ||
139 | static struct intc_prio_reg prio_registers[] __initdata = { | |
140 | { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | |
141 | { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
142 | { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, | |
143 | { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, | |
144 | { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, | |
145 | { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } }, | |
146 | { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } }, | |
147 | { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB, | |
148 | MTU2_VU } }, | |
149 | { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD, | |
150 | MTU2_TCI4V } }, | |
151 | { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } }, | |
152 | { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } }, | |
153 | { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } }, | |
a8f67f4b | 154 | #ifdef CONFIG_CPU_SUBTYPE_SH7203 |
6d01f510 PM |
155 | { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, |
156 | SSI3_SSII, 0 } }, | |
157 | { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } }, | |
158 | { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } }, | |
a8f67f4b PM |
159 | #else |
160 | { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, | |
161 | SSI3_SSII, ROMDEC } }, | |
162 | { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } }, | |
163 | { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } }, | |
164 | #endif | |
6d01f510 PM |
165 | }; |
166 | ||
167 | static struct intc_mask_reg mask_registers[] __initdata = { | |
168 | { 0xfffe0808, 0, 16, /* PINTER */ | |
169 | { 0, 0, 0, 0, 0, 0, 0, 0, | |
170 | PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, | |
171 | }; | |
172 | ||
173 | static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, | |
7f3edee8 | 174 | mask_registers, prio_registers, NULL); |
6d01f510 PM |
175 | |
176 | static struct plat_sci_port sci_platform_data[] = { | |
177 | { | |
178 | .mapbase = 0xfffe8000, | |
179 | .flags = UPF_BOOT_AUTOCONF, | |
00b9de9c | 180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
26c92f37 | 181 | .scbrr_algo_id = SCBRR_ALGO_2, |
6d01f510 | 182 | .type = PORT_SCIF, |
bb943a28 | 183 | .irqs = { 192, 192, 192, 192 }, |
6d01f510 PM |
184 | }, { |
185 | .mapbase = 0xfffe8800, | |
186 | .flags = UPF_BOOT_AUTOCONF, | |
00b9de9c | 187 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
26c92f37 | 188 | .scbrr_algo_id = SCBRR_ALGO_2, |
6d01f510 | 189 | .type = PORT_SCIF, |
bb943a28 | 190 | .irqs = { 196, 196, 196, 196 }, |
6d01f510 PM |
191 | }, { |
192 | .mapbase = 0xfffe9000, | |
193 | .flags = UPF_BOOT_AUTOCONF, | |
00b9de9c | 194 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
26c92f37 | 195 | .scbrr_algo_id = SCBRR_ALGO_2, |
6d01f510 | 196 | .type = PORT_SCIF, |
bb943a28 | 197 | .irqs = { 200, 200, 200, 200 }, |
6d01f510 PM |
198 | }, { |
199 | .mapbase = 0xfffe9800, | |
200 | .flags = UPF_BOOT_AUTOCONF, | |
00b9de9c | 201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
26c92f37 | 202 | .scbrr_algo_id = SCBRR_ALGO_2, |
6d01f510 | 203 | .type = PORT_SCIF, |
bb943a28 | 204 | .irqs = { 204, 204, 204, 204 }, |
6d01f510 PM |
205 | }, { |
206 | .flags = 0, | |
207 | } | |
208 | }; | |
209 | ||
210 | static struct platform_device sci_device = { | |
211 | .name = "sh-sci", | |
212 | .id = -1, | |
213 | .dev = { | |
214 | .platform_data = sci_platform_data, | |
215 | }, | |
216 | }; | |
217 | ||
46a12f74 | 218 | static struct sh_timer_config cmt0_platform_data = { |
698aa99d MD |
219 | .name = "CMT0", |
220 | .channel_offset = 0x02, | |
221 | .timer_bit = 0, | |
af777ce4 | 222 | .clk = "peripheral_clk", |
698aa99d MD |
223 | .clockevent_rating = 125, |
224 | .clocksource_rating = 0, /* disabled due to code generation issues */ | |
225 | }; | |
226 | ||
227 | static struct resource cmt0_resources[] = { | |
228 | [0] = { | |
229 | .name = "CMT0", | |
230 | .start = 0xfffec002, | |
231 | .end = 0xfffec007, | |
232 | .flags = IORESOURCE_MEM, | |
233 | }, | |
234 | [1] = { | |
235 | .start = 142, | |
236 | .flags = IORESOURCE_IRQ, | |
237 | }, | |
238 | }; | |
239 | ||
240 | static struct platform_device cmt0_device = { | |
241 | .name = "sh_cmt", | |
242 | .id = 0, | |
243 | .dev = { | |
244 | .platform_data = &cmt0_platform_data, | |
245 | }, | |
246 | .resource = cmt0_resources, | |
247 | .num_resources = ARRAY_SIZE(cmt0_resources), | |
248 | }; | |
249 | ||
46a12f74 | 250 | static struct sh_timer_config cmt1_platform_data = { |
698aa99d MD |
251 | .name = "CMT1", |
252 | .channel_offset = 0x08, | |
253 | .timer_bit = 1, | |
af777ce4 | 254 | .clk = "peripheral_clk", |
698aa99d MD |
255 | .clockevent_rating = 125, |
256 | .clocksource_rating = 0, /* disabled due to code generation issues */ | |
257 | }; | |
258 | ||
259 | static struct resource cmt1_resources[] = { | |
260 | [0] = { | |
261 | .name = "CMT1", | |
262 | .start = 0xfffec008, | |
263 | .end = 0xfffec00d, | |
264 | .flags = IORESOURCE_MEM, | |
265 | }, | |
266 | [1] = { | |
267 | .start = 143, | |
268 | .flags = IORESOURCE_IRQ, | |
269 | }, | |
270 | }; | |
271 | ||
272 | static struct platform_device cmt1_device = { | |
273 | .name = "sh_cmt", | |
274 | .id = 1, | |
275 | .dev = { | |
276 | .platform_data = &cmt1_platform_data, | |
277 | }, | |
278 | .resource = cmt1_resources, | |
279 | .num_resources = ARRAY_SIZE(cmt1_resources), | |
280 | }; | |
281 | ||
46a12f74 | 282 | static struct sh_timer_config mtu2_0_platform_data = { |
da107c6e MD |
283 | .name = "MTU2_0", |
284 | .channel_offset = -0x80, | |
285 | .timer_bit = 0, | |
af777ce4 | 286 | .clk = "peripheral_clk", |
da107c6e MD |
287 | .clockevent_rating = 200, |
288 | }; | |
289 | ||
290 | static struct resource mtu2_0_resources[] = { | |
291 | [0] = { | |
292 | .name = "MTU2_0", | |
293 | .start = 0xfffe4300, | |
294 | .end = 0xfffe4326, | |
295 | .flags = IORESOURCE_MEM, | |
296 | }, | |
297 | [1] = { | |
298 | .start = 146, | |
299 | .flags = IORESOURCE_IRQ, | |
300 | }, | |
301 | }; | |
302 | ||
303 | static struct platform_device mtu2_0_device = { | |
304 | .name = "sh_mtu2", | |
305 | .id = 0, | |
306 | .dev = { | |
307 | .platform_data = &mtu2_0_platform_data, | |
308 | }, | |
309 | .resource = mtu2_0_resources, | |
310 | .num_resources = ARRAY_SIZE(mtu2_0_resources), | |
311 | }; | |
312 | ||
46a12f74 | 313 | static struct sh_timer_config mtu2_1_platform_data = { |
da107c6e MD |
314 | .name = "MTU2_1", |
315 | .channel_offset = -0x100, | |
316 | .timer_bit = 1, | |
af777ce4 | 317 | .clk = "peripheral_clk", |
da107c6e MD |
318 | .clockevent_rating = 200, |
319 | }; | |
320 | ||
321 | static struct resource mtu2_1_resources[] = { | |
322 | [0] = { | |
323 | .name = "MTU2_1", | |
324 | .start = 0xfffe4380, | |
325 | .end = 0xfffe4390, | |
326 | .flags = IORESOURCE_MEM, | |
327 | }, | |
328 | [1] = { | |
329 | .start = 153, | |
330 | .flags = IORESOURCE_IRQ, | |
331 | }, | |
332 | }; | |
333 | ||
334 | static struct platform_device mtu2_1_device = { | |
335 | .name = "sh_mtu2", | |
336 | .id = 1, | |
337 | .dev = { | |
338 | .platform_data = &mtu2_1_platform_data, | |
339 | }, | |
340 | .resource = mtu2_1_resources, | |
341 | .num_resources = ARRAY_SIZE(mtu2_1_resources), | |
342 | }; | |
343 | ||
6d01f510 PM |
344 | static struct resource rtc_resources[] = { |
345 | [0] = { | |
346 | .start = 0xffff2000, | |
347 | .end = 0xffff2000 + 0x58 - 1, | |
348 | .flags = IORESOURCE_IO, | |
349 | }, | |
350 | [1] = { | |
bb943a28 | 351 | /* Shared Period/Carry/Alarm IRQ */ |
6d01f510 PM |
352 | .start = 231, |
353 | .flags = IORESOURCE_IRQ, | |
354 | }, | |
355 | }; | |
356 | ||
357 | static struct platform_device rtc_device = { | |
358 | .name = "sh-rtc", | |
359 | .id = -1, | |
360 | .num_resources = ARRAY_SIZE(rtc_resources), | |
361 | .resource = rtc_resources, | |
362 | }; | |
363 | ||
364 | static struct platform_device *sh7203_devices[] __initdata = { | |
365 | &sci_device, | |
698aa99d MD |
366 | &cmt0_device, |
367 | &cmt1_device, | |
da107c6e MD |
368 | &mtu2_0_device, |
369 | &mtu2_1_device, | |
6d01f510 PM |
370 | &rtc_device, |
371 | }; | |
372 | ||
373 | static int __init sh7203_devices_setup(void) | |
374 | { | |
375 | return platform_add_devices(sh7203_devices, | |
376 | ARRAY_SIZE(sh7203_devices)); | |
377 | } | |
378 | __initcall(sh7203_devices_setup); | |
379 | ||
380 | void __init plat_irq_setup(void) | |
381 | { | |
382 | register_intc_controller(&intc_desc); | |
383 | } | |
698aa99d MD |
384 | |
385 | static struct platform_device *sh7203_early_devices[] __initdata = { | |
386 | &cmt0_device, | |
387 | &cmt1_device, | |
da107c6e MD |
388 | &mtu2_0_device, |
389 | &mtu2_1_device, | |
698aa99d MD |
390 | }; |
391 | ||
da107c6e | 392 | #define STBCR3 0xfffe0408 |
698aa99d MD |
393 | #define STBCR4 0xfffe040c |
394 | ||
395 | void __init plat_early_device_setup(void) | |
396 | { | |
397 | /* enable CMT clock */ | |
398 | __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4); | |
399 | ||
da107c6e MD |
400 | /* enable MTU2 clock */ |
401 | __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); | |
402 | ||
698aa99d MD |
403 | early_platform_add_devices(sh7203_early_devices, |
404 | ARRAY_SIZE(sh7203_early_devices)); | |
405 | } |