[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7722.c

/*
 * SH7722 Setup
 *
 *  Copyright (C) 2006 - 2008  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/mm.h>
#include <linux/uio_driver.h>
#include <linux/usb/m66592.h>
#include <linux/sh_timer.h>
#include <asm/clock.h>
#include <asm/mmzone.h>
#include <asm/dma-sh.h>
#include <asm/siu.h>
#include <cpu/sh7722.h>

static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
	{
		.slave_id	= SHDMA_SLAVE_SCIF0_TX,
		.addr		= 0xffe0000c,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x21,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF0_RX,
		.addr		= 0xffe00014,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x22,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF1_TX,
		.addr		= 0xffe1000c,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x25,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF1_RX,
		.addr		= 0xffe10014,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x26,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
		.addr		= 0xffe2000c,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x29,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
		.addr		= 0xffe20014,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x2a,
	}, {
		.slave_id	= SHDMA_SLAVE_SIUA_TX,
		.addr		= 0xa454c098,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
		.mid_rid	= 0xb1,
	}, {
		.slave_id	= SHDMA_SLAVE_SIUA_RX,
		.addr		= 0xa454c090,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
		.mid_rid	= 0xb2,
	}, {
		.slave_id	= SHDMA_SLAVE_SIUB_TX,
		.addr		= 0xa454c09c,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
		.mid_rid	= 0xb5,
	}, {
		.slave_id	= SHDMA_SLAVE_SIUB_RX,
		.addr		= 0xa454c094,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
		.mid_rid	= 0xb6,
	},
};

static struct sh_dmae_channel sh7722_dmae_channels[] = {
	{
		.offset = 0,
		.dmars = 0,
		.dmars_bit = 0,
	}, {
		.offset = 0x10,
		.dmars = 0,
		.dmars_bit = 8,
	}, {
		.offset = 0x20,
		.dmars = 4,
		.dmars_bit = 0,
	}, {
		.offset = 0x30,
		.dmars = 4,
		.dmars_bit = 8,
	}, {
		.offset = 0x50,
		.dmars = 8,
		.dmars_bit = 0,
	}, {
		.offset = 0x60,
		.dmars = 8,
		.dmars_bit = 8,
	}
};

static struct sh_dmae_pdata dma_platform_data = {
	.slave		= sh7722_dmae_slaves,
	.slave_num	= ARRAY_SIZE(sh7722_dmae_slaves),
	.channel	= sh7722_dmae_channels,
	.channel_num	= ARRAY_SIZE(sh7722_dmae_channels),
};

static struct resource sh7722_dmae_resources[] = {
	[0] = {
		/* Channel registers and DMAOR */
		.start	= 0xfe008020,
		.end	= 0xfe00808f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* DMARSx */
		.start	= 0xfe009000,
		.end	= 0xfe00900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMA error IRQ */
		.start	= 78,
		.end	= 78,
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-3 */
		.start	= 48,
		.end	= 51,
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 4-5 */
		.start	= 76,
		.end	= 77,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device dma_device = {
	.name		= "sh-dma-engine",
	.id		= -1,
	.resource	= sh7722_dmae_resources,
	.num_resources	= ARRAY_SIZE(sh7722_dmae_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

/* Serial */
static struct plat_sci_port scif0_platform_data = {
	.mapbase        = 0xffe00000,
	.flags          = UPF_BOOT_AUTOCONF,
	.type           = PORT_SCIF,
	.irqs           = { 80, 80, 80, 80 },
	.clk		= "scif0",
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase        = 0xffe10000,
	.flags          = UPF_BOOT_AUTOCONF,
	.type           = PORT_SCIF,
	.irqs           = { 81, 81, 81, 81 },
	.clk		= "scif1",
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase        = 0xffe20000,
	.flags          = UPF_BOOT_AUTOCONF,
	.type           = PORT_SCIF,
	.irqs           = { 82, 82, 82, 82 },
	.clk		= "scif2",
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xa465fec0,
		.end	= 0xa465fec0 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Period IRQ */
		.start	= 45,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* Carry IRQ */
		.start	= 46,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		/* Alarm IRQ */
		.start	= 44,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
	.archdata = {
		.hwblk_id = HWBLK_RTC,
	},
};

static struct m66592_platdata usbf_platdata = {
	.on_chip = 1,
};

static struct resource usbf_resources[] = {
	[0] = {
		.name	= "USBF",
		.start	= 0x04480000,
		.end	= 0x044800FF,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 65,
		.end	= 65,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device usbf_device = {
	.name		= "m66592_udc",
	.id             = 0, /* "usbf0" clock */
	.dev = {
		.dma_mask		= NULL,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &usbf_platdata,
	},
	.num_resources	= ARRAY_SIZE(usbf_resources),
	.resource	= usbf_resources,
	.archdata = {
		.hwblk_id = HWBLK_USBF,
	},
};

static struct resource iic_resources[] = {
	[0] = {
		.name	= "IIC",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic_resources),
	.resource       = iic_resources,
	.archdata = {
		.hwblk_id = HWBLK_IIC,
	},
};

static struct uio_info vpu_platform_data = {
	.name = "VPU4",
	.version = "0",
	.irq = 60,
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe9022eb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
	.archdata = {
		.hwblk_id = HWBLK_VPU,
	},
};

static struct uio_info veu_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = 54,
};

static struct resource veu_resources[] = {
	[0] = {
		.name	= "VEU",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu_platform_data,
	},
	.resource	= veu_resources,
	.num_resources	= ARRAY_SIZE(veu_resources),
	.archdata = {
		.hwblk_id = HWBLK_VEU,
	},
};

static struct uio_info jpu_platform_data = {
	.name = "JPU",
	.version = "0",
	.irq = 27,
};

static struct resource jpu_resources[] = {
	[0] = {
		.name	= "JPU",
		.start	= 0xfea00000,
		.end	= 0xfea102d3,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device jpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &jpu_platform_data,
	},
	.resource	= jpu_resources,
	.num_resources	= ARRAY_SIZE(jpu_resources),
	.archdata = {
		.hwblk_id = HWBLK_JPU,
	},
};

static struct sh_timer_config cmt_platform_data = {
	.name = "CMT",
	.channel_offset = 0x60,
	.timer_bit = 5,
	.clk = "cmt0",
	.clockevent_rating = 125,
	.clocksource_rating = 125,
};

static struct resource cmt_resources[] = {
	[0] = {
		.name	= "CMT",
		.start	= 0x044a0060,
		.end	= 0x044a006b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 104,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
	.archdata = {
		.hwblk_id = HWBLK_CMT,
	},
};

static struct sh_timer_config tmu0_platform_data = {
	.name = "TMU0",
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clk = "tmu0",
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.name	= "TMU0",
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 16,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
	.archdata = {
		.hwblk_id = HWBLK_TMU,
	},
};

static struct sh_timer_config tmu1_platform_data = {
	.name = "TMU1",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clk = "tmu0",
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.name	= "TMU1",
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 17,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
	.archdata = {
		.hwblk_id = HWBLK_TMU,
	},
};

static struct sh_timer_config tmu2_platform_data = {
	.name = "TMU2",
	.channel_offset = 0x1c,
	.timer_bit = 2,
	.clk = "tmu0",
};

static struct resource tmu2_resources[] = {
	[0] = {
		.name	= "TMU2",
		.start	= 0xffd80020,
		.end	= 0xffd8002b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 18,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
	.archdata = {
		.hwblk_id = HWBLK_TMU,
	},
};

static struct siu_platform siu_platform_data = {
	.dma_dev	= &dma_device.dev,
	.dma_slave_tx_a	= SHDMA_SLAVE_SIUA_TX,
	.dma_slave_rx_a	= SHDMA_SLAVE_SIUA_RX,
	.dma_slave_tx_b	= SHDMA_SLAVE_SIUB_TX,
	.dma_slave_rx_b	= SHDMA_SLAVE_SIUB_RX,
};

static struct resource siu_resources[] = {
	[0] = {
		.start	= 0xa4540000,
		.end	= 0xa454c10f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 108,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device siu_device = {
	.name		= "sh_siu",
	.id		= -1,
	.dev = {
		.platform_data	= &siu_platform_data,
	},
	.resource	= siu_resources,
	.num_resources	= ARRAY_SIZE(siu_resources),
	.archdata = {
		.hwblk_id = HWBLK_SIU,
	},
};

static struct platform_device *sh7722_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&rtc_device,
	&usbf_device,
	&iic_device,
	&vpu_device,
	&veu_device,
	&jpu_device,
	&siu_device,
	&dma_device,
};

static int __init sh7722_devices_setup(void)
{
	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);

	return platform_add_devices(sh7722_devices,
				    ARRAY_SIZE(sh7722_devices));
}
arch_initcall(sh7722_devices_setup);

static struct platform_device *sh7722_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7722_early_devices,
				   ARRAY_SIZE(sh7722_early_devices));
}

enum {
	UNUSED=0,
	ENABLED,
	DISABLED,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	HUDI,
	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	VPU, TPU,
	USB_USBI0, USB_USBI1,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	CMT, TSIF, SIU, TWODG,
	TMU0, TMU1, TMU2,
	IRDA, JPU, LCDC,

	/* interrupt groups */
	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
	INTC_VECT(RTC_CUI, 0x7c0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { } },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_desc intc_desc __initdata = {
	.name = "sh7722",
	.force_enable = ENABLED,
	.force_disable = DISABLED,
	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
			   prio_registers, sense_registers, ack_registers),
};

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

void __init plat_mem_setup(void)
{
	/* Register the URAM space as Node 1 */
	setup_bootmem_node(1, 0x055f0000, 0x05610000);
}
Commit	Line	Data
41504c39 PM	1	/*
	2	* SH7722 Setup
	3	*
b4d36a25	4	* Copyright (C) 2006 - 2008 Paul Mundt
41504c39 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
520588f4	14	#include <linux/mm.h>
a55f6d25	15	#include <linux/uio_driver.h>
2c59b0b7	16	#include <linux/usb/m66592.h>
46a12f74	17	#include <linux/sh_timer.h>
6c7d826c	18	#include <asm/clock.h>
5bbeafca	19	#include <asm/mmzone.h>
8255fff4	20	#include <asm/dma-sh.h>
331af0c1	21	#include <asm/siu.h>
f69d5782	22	#include <cpu/sh7722.h>
41504c39	23
331af0c1 GL	24	static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
	25	{
	26	.slave_id = SHDMA_SLAVE_SCIF0_TX,
	27	.addr = 0xffe0000c,
	28	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	29	.mid_rid = 0x21,
	30	}, {
	31	.slave_id = SHDMA_SLAVE_SCIF0_RX,
	32	.addr = 0xffe00014,
	33	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	34	.mid_rid = 0x22,
	35	}, {
	36	.slave_id = SHDMA_SLAVE_SCIF1_TX,
	37	.addr = 0xffe1000c,
	38	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	39	.mid_rid = 0x25,
	40	}, {
	41	.slave_id = SHDMA_SLAVE_SCIF1_RX,
	42	.addr = 0xffe10014,
	43	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	44	.mid_rid = 0x26,
	45	}, {
	46	.slave_id = SHDMA_SLAVE_SCIF2_TX,
	47	.addr = 0xffe2000c,
	48	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	49	.mid_rid = 0x29,
	50	}, {
	51	.slave_id = SHDMA_SLAVE_SCIF2_RX,
	52	.addr = 0xffe20014,
	53	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	54	.mid_rid = 0x2a,
	55	}, {
	56	.slave_id = SHDMA_SLAVE_SIUA_TX,
	57	.addr = 0xa454c098,
	58	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_32BIT),
	59	.mid_rid = 0xb1,
	60	}, {
	61	.slave_id = SHDMA_SLAVE_SIUA_RX,
	62	.addr = 0xa454c090,
	63	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_32BIT),
	64	.mid_rid = 0xb2,
	65	}, {
	66	.slave_id = SHDMA_SLAVE_SIUB_TX,
	67	.addr = 0xa454c09c,
	68	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_32BIT),
	69	.mid_rid = 0xb5,
	70	}, {
	71	.slave_id = SHDMA_SLAVE_SIUB_RX,
	72	.addr = 0xa454c094,
	73	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_32BIT),
	74	.mid_rid = 0xb6,
	75	},
	76	};
	77
027811b9 GL	78	static struct sh_dmae_channel sh7722_dmae_channels[] = {
	79	{
	80	.offset = 0,
	81	.dmars = 0,
	82	.dmars_bit = 0,
	83	}, {
	84	.offset = 0x10,
	85	.dmars = 0,
	86	.dmars_bit = 8,
	87	}, {
	88	.offset = 0x20,
	89	.dmars = 4,
	90	.dmars_bit = 0,
	91	}, {
	92	.offset = 0x30,
	93	.dmars = 4,
	94	.dmars_bit = 8,
	95	}, {
	96	.offset = 0x50,
	97	.dmars = 8,
	98	.dmars_bit = 0,
	99	}, {
	100	.offset = 0x60,
	101	.dmars = 8,
	102	.dmars_bit = 8,
	103	}
	104	};
	105
331af0c1	106	static struct sh_dmae_pdata dma_platform_data = {
027811b9 GL	107	.slave = sh7722_dmae_slaves,
	108	.slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
	109	.channel = sh7722_dmae_channels,
	110	.channel_num = ARRAY_SIZE(sh7722_dmae_channels),
	111	};
	112
	113	static struct resource sh7722_dmae_resources[] = {
	114	[0] = {
	115	/* Channel registers and DMAOR */
	116	.start = 0xfe008020,
	117	.end = 0xfe00808f,
	118	.flags = IORESOURCE_MEM,
	119	},
	120	[1] = {
	121	/* DMARSx */
	122	.start = 0xfe009000,
	123	.end = 0xfe00900b,
	124	.flags = IORESOURCE_MEM,
	125	},
	126	{
	127	/* DMA error IRQ */
	128	.start = 78,
	129	.end = 78,
	130	.flags = IORESOURCE_IRQ,
	131	},
	132	{
	133	/* IRQ for channels 0-3 */
	134	.start = 48,
	135	.end = 51,
	136	.flags = IORESOURCE_IRQ,
	137	},
	138	{
	139	/* IRQ for channels 4-5 */
	140	.start = 76,
	141	.end = 77,
	142	.flags = IORESOURCE_IRQ,
	143	},
331af0c1 GL	144	};
	145
	146	struct platform_device dma_device = {
	147	.name = "sh-dma-engine",
	148	.id = -1,
027811b9 GL	149	.resource = sh7722_dmae_resources,
027811b9 GL	150	.num_resources = ARRAY_SIZE(sh7722_dmae_resources),
331af0c1 GL	151	.dev = {
	152	.platform_data = &dma_platform_data,
	153	},
	154	};
	155
bcac24d0 MD	156	/* Serial */
	157	static struct plat_sci_port scif0_platform_data = {
	158	.mapbase = 0xffe00000,
	159	.flags = UPF_BOOT_AUTOCONF,
	160	.type = PORT_SCIF,
	161	.irqs = { 80, 80, 80, 80 },
	162	.clk = "scif0",
	163	};
	164
	165	static struct platform_device scif0_device = {
	166	.name = "sh-sci",
	167	.id = 0,
	168	.dev = {
	169	.platform_data = &scif0_platform_data,
	170	},
	171	};
	172
	173	static struct plat_sci_port scif1_platform_data = {
	174	.mapbase = 0xffe10000,
	175	.flags = UPF_BOOT_AUTOCONF,
	176	.type = PORT_SCIF,
	177	.irqs = { 81, 81, 81, 81 },
	178	.clk = "scif1",
	179	};
	180
	181	static struct platform_device scif1_device = {
	182	.name = "sh-sci",
	183	.id = 1,
	184	.dev = {
	185	.platform_data = &scif1_platform_data,
	186	},
	187	};
	188
	189	static struct plat_sci_port scif2_platform_data = {
	190	.mapbase = 0xffe20000,
	191	.flags = UPF_BOOT_AUTOCONF,
	192	.type = PORT_SCIF,
	193	.irqs = { 82, 82, 82, 82 },
	194	.clk = "scif2",
	195	};
	196
	197	static struct platform_device scif2_device = {
	198	.name = "sh-sci",
	199	.id = 2,
	200	.dev = {
	201	.platform_data = &scif2_platform_data,
	202	},
	203	};
	204
b4d36a25 PM	205	static struct resource rtc_resources[] = {
	206	[0] = {
	207	.start = 0xa465fec0,
	208	.end = 0xa465fec0 + 0x58 - 1,
	209	.flags = IORESOURCE_IO,
	210	},
	211	[1] = {
	212	/* Period IRQ */
	213	.start = 45,
	214	.flags = IORESOURCE_IRQ,
	215	},
	216	[2] = {
	217	/* Carry IRQ */
	218	.start = 46,
	219	.flags = IORESOURCE_IRQ,
	220	},
	221	[3] = {
	222	/* Alarm IRQ */
	223	.start = 44,
	224	.flags = IORESOURCE_IRQ,
	225	},
	226	};
	227
	228	static struct platform_device rtc_device = {
	229	.name = "sh-rtc",
	230	.id = -1,
	231	.num_resources = ARRAY_SIZE(rtc_resources),
	232	.resource = rtc_resources,
f69d5782 MD	233	.archdata = {
	234	.hwblk_id = HWBLK_RTC,
	235	},
b4d36a25 PM	236	};
b4d36a25 PM	237
2c59b0b7 MD	238	static struct m66592_platdata usbf_platdata = {
	239	.on_chip = 1,
	240	};
	241
262feaa0 YS	242	static struct resource usbf_resources[] = {
262feaa0 YS	243	[0] = {
2c59b0b7	244	.name = "USBF",
a0d29798 MD	245	.start = 0x04480000,
a0d29798 MD	246	.end = 0x044800FF,
262feaa0 YS	247	.flags = IORESOURCE_MEM,
	248	},
	249	[1] = {
262feaa0 YS	250	.start = 65,
	251	.end = 65,
	252	.flags = IORESOURCE_IRQ,
	253	},
	254	};
	255
	256	static struct platform_device usbf_device = {
	257	.name = "m66592_udc",
af5be79a	258	.id = 0, /* "usbf0" clock */
262feaa0 YS	259	.dev = {
	260	.dma_mask = NULL,
	261	.coherent_dma_mask = 0xffffffff,
2c59b0b7	262	.platform_data = &usbf_platdata,
262feaa0 YS	263	},
	264	.num_resources = ARRAY_SIZE(usbf_resources),
	265	.resource = usbf_resources,
f69d5782 MD	266	.archdata = {
	267	.hwblk_id = HWBLK_USBF,
	268	},
262feaa0 YS	269	};
262feaa0 YS	270
ef1b2327 MD	271	static struct resource iic_resources[] = {
	272	[0] = {
	273	.name = "IIC",
	274	.start = 0x04470000,
	275	.end = 0x04470017,
	276	.flags = IORESOURCE_MEM,
	277	},
	278	[1] = {
	279	.start = 96,
	280	.end = 99,
	281	.flags = IORESOURCE_IRQ,
	282	},
	283	};
	284
	285	static struct platform_device iic_device = {
	286	.name = "i2c-sh_mobile",
a5616bd0	287	.id = 0, /* "i2c0" clock */
ef1b2327 MD	288	.num_resources = ARRAY_SIZE(iic_resources),
ef1b2327 MD	289	.resource = iic_resources,
f69d5782 MD	290	.archdata = {
	291	.hwblk_id = HWBLK_IIC,
	292	},
ef1b2327 MD	293	};
ef1b2327 MD	294
a55f6d25 MD	295	static struct uio_info vpu_platform_data = {
	296	.name = "VPU4",
	297	.version = "0",
	298	.irq = 60,
	299	};
	300
	301	static struct resource vpu_resources[] = {
	302	[0] = {
	303	.name = "VPU",
	304	.start = 0xfe900000,
	305	.end = 0xfe9022eb,
	306	.flags = IORESOURCE_MEM,
	307	},
1eca5c92 MD	308	[1] = {
	309	/* place holder for contiguous memory */
	310	},
a55f6d25 MD	311	};
	312
	313	static struct platform_device vpu_device = {
	314	.name = "uio_pdrv_genirq",
	315	.id = 0,
	316	.dev = {
	317	.platform_data = &vpu_platform_data,
	318	},
	319	.resource = vpu_resources,
	320	.num_resources = ARRAY_SIZE(vpu_resources),
f69d5782 MD	321	.archdata = {
	322	.hwblk_id = HWBLK_VPU,
	323	},
a55f6d25 MD	324	};
	325
	326	static struct uio_info veu_platform_data = {
	327	.name = "VEU",
	328	.version = "0",
	329	.irq = 54,
	330	};
	331
	332	static struct resource veu_resources[] = {
	333	[0] = {
	334	.name = "VEU",
	335	.start = 0xfe920000,
	336	.end = 0xfe9200b7,
	337	.flags = IORESOURCE_MEM,
	338	},
1eca5c92 MD	339	[1] = {
	340	/* place holder for contiguous memory */
	341	},
a55f6d25 MD	342	};
	343
	344	static struct platform_device veu_device = {
	345	.name = "uio_pdrv_genirq",
	346	.id = 1,
	347	.dev = {
	348	.platform_data = &veu_platform_data,
	349	},
	350	.resource = veu_resources,
	351	.num_resources = ARRAY_SIZE(veu_resources),
f69d5782 MD	352	.archdata = {
	353	.hwblk_id = HWBLK_VEU,
	354	},
a55f6d25 MD	355	};
a55f6d25 MD	356
7d91fcfc TH	357	static struct uio_info jpu_platform_data = {
	358	.name = "JPU",
	359	.version = "0",
	360	.irq = 27,
	361	};
	362
	363	static struct resource jpu_resources[] = {
	364	[0] = {
	365	.name = "JPU",
	366	.start = 0xfea00000,
3442c0d6	367	.end = 0xfea102d3,
7d91fcfc TH	368	.flags = IORESOURCE_MEM,
	369	},
	370	[1] = {
	371	/* place holder for contiguous memory */
	372	},
	373	};
	374
	375	static struct platform_device jpu_device = {
	376	.name = "uio_pdrv_genirq",
	377	.id = 2,
	378	.dev = {
	379	.platform_data = &jpu_platform_data,
	380	},
	381	.resource = jpu_resources,
	382	.num_resources = ARRAY_SIZE(jpu_resources),
f69d5782 MD	383	.archdata = {
	384	.hwblk_id = HWBLK_JPU,
	385	},
7d91fcfc TH	386	};
7d91fcfc TH	387
46a12f74	388	static struct sh_timer_config cmt_platform_data = {
424f59d0 MD	389	.name = "CMT",
	390	.channel_offset = 0x60,
	391	.timer_bit = 5,
	392	.clk = "cmt0",
	393	.clockevent_rating = 125,
583d1d54	394	.clocksource_rating = 125,
424f59d0 MD	395	};
	396
	397	static struct resource cmt_resources[] = {
	398	[0] = {
	399	.name = "CMT",
	400	.start = 0x044a0060,
	401	.end = 0x044a006b,
	402	.flags = IORESOURCE_MEM,
	403	},
	404	[1] = {
	405	.start = 104,
	406	.flags = IORESOURCE_IRQ,
	407	},
	408	};
	409
	410	static struct platform_device cmt_device = {
	411	.name = "sh_cmt",
	412	.id = 0,
	413	.dev = {
	414	.platform_data = &cmt_platform_data,
	415	},
	416	.resource = cmt_resources,
	417	.num_resources = ARRAY_SIZE(cmt_resources),
f69d5782 MD	418	.archdata = {
	419	.hwblk_id = HWBLK_CMT,
	420	},
424f59d0 MD	421	};
424f59d0 MD	422
46a12f74	423	static struct sh_timer_config tmu0_platform_data = {
d43a41bf MD	424	.name = "TMU0",
	425	.channel_offset = 0x04,
	426	.timer_bit = 0,
	427	.clk = "tmu0",
	428	.clockevent_rating = 200,
	429	};
	430
	431	static struct resource tmu0_resources[] = {
	432	[0] = {
	433	.name = "TMU0",
	434	.start = 0xffd80008,
	435	.end = 0xffd80013,
	436	.flags = IORESOURCE_MEM,
	437	},
	438	[1] = {
	439	.start = 16,
	440	.flags = IORESOURCE_IRQ,
	441	},
	442	};
	443
	444	static struct platform_device tmu0_device = {
	445	.name = "sh_tmu",
	446	.id = 0,
	447	.dev = {
	448	.platform_data = &tmu0_platform_data,
	449	},
	450	.resource = tmu0_resources,
	451	.num_resources = ARRAY_SIZE(tmu0_resources),
f69d5782 MD	452	.archdata = {
	453	.hwblk_id = HWBLK_TMU,
	454	},
d43a41bf MD	455	};
d43a41bf MD	456
46a12f74	457	static struct sh_timer_config tmu1_platform_data = {
d43a41bf MD	458	.name = "TMU1",
	459	.channel_offset = 0x10,
	460	.timer_bit = 1,
	461	.clk = "tmu0",
583d1d54	462	.clocksource_rating = 200,
d43a41bf MD	463	};
	464
	465	static struct resource tmu1_resources[] = {
	466	[0] = {
	467	.name = "TMU1",
	468	.start = 0xffd80014,
	469	.end = 0xffd8001f,
	470	.flags = IORESOURCE_MEM,
	471	},
	472	[1] = {
	473	.start = 17,
	474	.flags = IORESOURCE_IRQ,
	475	},
	476	};
	477
	478	static struct platform_device tmu1_device = {
	479	.name = "sh_tmu",
	480	.id = 1,
	481	.dev = {
	482	.platform_data = &tmu1_platform_data,
	483	},
	484	.resource = tmu1_resources,
	485	.num_resources = ARRAY_SIZE(tmu1_resources),
f69d5782 MD	486	.archdata = {
	487	.hwblk_id = HWBLK_TMU,
	488	},
d43a41bf MD	489	};
d43a41bf MD	490
46a12f74	491	static struct sh_timer_config tmu2_platform_data = {
d43a41bf MD	492	.name = "TMU2",
	493	.channel_offset = 0x1c,
	494	.timer_bit = 2,
	495	.clk = "tmu0",
	496	};
	497
	498	static struct resource tmu2_resources[] = {
	499	[0] = {
	500	.name = "TMU2",
	501	.start = 0xffd80020,
	502	.end = 0xffd8002b,
	503	.flags = IORESOURCE_MEM,
	504	},
	505	[1] = {
	506	.start = 18,
	507	.flags = IORESOURCE_IRQ,
	508	},
	509	};
	510
	511	static struct platform_device tmu2_device = {
	512	.name = "sh_tmu",
	513	.id = 2,
	514	.dev = {
	515	.platform_data = &tmu2_platform_data,
	516	},
	517	.resource = tmu2_resources,
	518	.num_resources = ARRAY_SIZE(tmu2_resources),
f69d5782 MD	519	.archdata = {
	520	.hwblk_id = HWBLK_TMU,
	521	},
d43a41bf MD	522	};
d43a41bf MD	523
331af0c1 GL	524	static struct siu_platform siu_platform_data = {
	525	.dma_dev = &dma_device.dev,
	526	.dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
	527	.dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
	528	.dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
	529	.dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
8255fff4 NI	530	};
8255fff4 NI	531
331af0c1 GL	532	static struct resource siu_resources[] = {
	533	[0] = {
	534	.start = 0xa4540000,
	535	.end = 0xa454c10f,
	536	.flags = IORESOURCE_MEM,
	537	},
	538	[1] = {
	539	.start = 108,
	540	.flags = IORESOURCE_IRQ,
	541	},
	542	};
	543
	544	static struct platform_device siu_device = {
	545	.name = "sh_siu",
8255fff4	546	.id = -1,
331af0c1 GL	547	.dev = {
	548	.platform_data = &siu_platform_data,
	549	},
	550	.resource = siu_resources,
	551	.num_resources = ARRAY_SIZE(siu_resources),
	552	.archdata = {
	553	.hwblk_id = HWBLK_SIU,
8255fff4 NI	554	},
	555	};
	556
41504c39	557	static struct platform_device *sh7722_devices[] __initdata = {
bcac24d0 MD	558	&scif0_device,
	559	&scif1_device,
	560	&scif2_device,
424f59d0	561	&cmt_device,
d43a41bf MD	562	&tmu0_device,
	563	&tmu1_device,
	564	&tmu2_device,
b4d36a25	565	&rtc_device,
262feaa0	566	&usbf_device,
ef1b2327	567	&iic_device,
a55f6d25 MD	568	&vpu_device,
a55f6d25 MD	569	&veu_device,
7d91fcfc	570	&jpu_device,
331af0c1	571	&siu_device,
8255fff4	572	&dma_device,
41504c39 PM	573	};
	574
	575	static int __init sh7722_devices_setup(void)
	576	{
1eca5c92 MD	577	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
1eca5c92 MD	578	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
7d91fcfc	579	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
6c7d826c	580
41504c39 PM	581	return platform_add_devices(sh7722_devices,
	582	ARRAY_SIZE(sh7722_devices));
	583	}
955c9863	584	arch_initcall(sh7722_devices_setup);
41504c39	585
28fde686	586	static struct platform_device *sh7722_early_devices[] __initdata = {
bcac24d0 MD	587	&scif0_device,
	588	&scif1_device,
	589	&scif2_device,
28fde686	590	&cmt_device,
d43a41bf MD	591	&tmu0_device,
	592	&tmu1_device,
	593	&tmu2_device,
28fde686 MD	594	};
	595
	596	void __init plat_early_device_setup(void)
	597	{
	598	early_platform_add_devices(sh7722_early_devices,
	599	ARRAY_SIZE(sh7722_early_devices));
	600	}
	601
1b06428e MD	602	enum {
1b06428e MD	603	UNUSED=0,
8d9adaba	604	ENABLED,
e9125ac0	605	DISABLED,
1b06428e MD	606
	607	/* interrupt sources */
	608	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	609	HUDI,
	610	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	611	RTC_ATI, RTC_PRI, RTC_CUI,
	612	DMAC0, DMAC1, DMAC2, DMAC3,
	613	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	614	VPU, TPU,
	615	USB_USBI0, USB_USBI1,
	616	DMAC4, DMAC5, DMAC_DADERR,
	617	KEYSC,
	618	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
	619	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	620	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
1b06428e MD	621	CMT, TSIF, SIU, TWODG,
	622	TMU0, TMU1, TMU2,
	623	IRDA, JPU, LCDC,
	624
	625	/* interrupt groups */
1b06428e	626	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
41504c39 PM	627	};
41504c39 PM	628
5c37e025	629	static struct intc_vect vectors[] __initdata = {
1b06428e MD	630	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	631	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	632	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	633	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	634	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
	635	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
	636	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
	637	INTC_VECT(RTC_CUI, 0x7c0),
	638	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	639	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	640	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	641	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	642	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
	643	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
	644	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	645	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	646	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
	647	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
	648	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
	649	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	650	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	651	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	652	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
8d9adaba MD	653	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
8d9adaba MD	654	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
1b06428e MD	655	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	656	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
	657	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	658	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
	659	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
41504c39 PM	660	};
41504c39 PM	661
5c37e025	662	static struct intc_group groups[] __initdata = {
1b06428e MD	663	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	664	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	665	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	666	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	667	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
	668	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	669	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	670	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	671	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
1b06428e	672	};
68abdbbb	673
5c37e025	674	static struct intc_mask_reg mask_registers[] __initdata = {
1b06428e MD	675	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	676	{ } },
	677	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	678	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	679	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	680	{ 0, 0, 0, VPU, } },
	681	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	682	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	683	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	684	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	685	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	686	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
	687	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	688	{ 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
	689	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	690	{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	691	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	692	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
e9125ac0	693	{ DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
1b06428e MD	694	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	695	{ 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
	696	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	697	{ } },
	698	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	699	{ 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
	700	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	701	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
68abdbbb	702	};
41504c39	703
5c37e025	704	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	705	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
	706	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	707	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	708	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	709	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
	710	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	711	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
	712	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
	713	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
	714	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	715	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
	716	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
	717	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
1b06428e MD	718	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	719	};
	720
5c37e025	721	static struct intc_sense_reg sense_registers[] __initdata = {
1b06428e MD	722	{ 0xa414001c, 16, 2, /* ICR1 */
	723	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	724	};
	725
6bdfb22a YS	726	static struct intc_mask_reg ack_registers[] __initdata = {
	727	{ 0xa4140024, 0, 8, /* INTREQ00 */
	728	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	729	};
	730
8d9adaba MD	731	static struct intc_desc intc_desc __initdata = {
	732	.name = "sh7722",
	733	.force_enable = ENABLED,
e9125ac0	734	.force_disable = DISABLED,
8d9adaba MD	735	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
	736	prio_registers, sense_registers, ack_registers),
	737	};
1b06428e	738
90015c89	739	void __init plat_irq_setup(void)
41504c39	740	{
1b06428e	741	register_intc_controller(&intc_desc);
41504c39	742	}
520588f4 PM	743
	744	void __init plat_mem_setup(void)
	745	{
	746	/* Register the URAM space as Node 1 */
	747	setup_bootmem_node(1, 0x055f0000, 0x05610000);
	748	}