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sh: add platform_device for SPI1 in setup-sh7757
[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7757.c
CommitLineData
c01f0f1a
YS		 1/*
2 * SH7757 Setup
3 *
8ac53ed5 4 * Copyright (C) 2009, 2011 Renesas Solutions Corp.
c01f0f1a
YS		 5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/io.h>
17#include <linux/mm.h>
21d41f2b 18#include <linux/dma-mapping.h>
c01f0f1a 19#include <linux/sh_timer.h>
8ac53ed5
YS		 20#include <linux/sh_dma.h>
21
22#include <cpu/dma-register.h>
23#include <cpu/sh7757.h>
c01f0f1a 24
a9571d7b
MD		 25static struct plat_sci_port scif2_platform_data = {
26 .mapbase = 0xfe4b0000, /* SCIF2 */
27 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 .scbrr_algo_id = SCBRR_ALGO_2,
a9571d7b
MD		 30 .type = PORT_SCIF,
31 .irqs = { 40, 40, 40, 40 },
32};
33
34static struct platform_device scif2_device = {
35 .name = "sh-sci",
a7f5551c 36 .id = 0,
a9571d7b
MD		 37 .dev = {
38 .platform_data = &scif2_platform_data,
39 },
40};
41
42static struct plat_sci_port scif3_platform_data = {
43 .mapbase = 0xfe4c0000, /* SCIF3 */
44 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
46 .scbrr_algo_id = SCBRR_ALGO_2,
a9571d7b
MD		 47 .type = PORT_SCIF,
48 .irqs = { 76, 76, 76, 76 },
49};
50
51static struct platform_device scif3_device = {
52 .name = "sh-sci",
a7f5551c 53 .id = 1,
a9571d7b
MD		 54 .dev = {
55 .platform_data = &scif3_platform_data,
56 },
57};
58
59static struct plat_sci_port scif4_platform_data = {
60 .mapbase = 0xfe4d0000, /* SCIF4 */
61 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
63 .scbrr_algo_id = SCBRR_ALGO_2,
a9571d7b
MD		 64 .type = PORT_SCIF,
65 .irqs = { 104, 104, 104, 104 },
66};
67
68static struct platform_device scif4_device = {
69 .name = "sh-sci",
a7f5551c 70 .id = 2,
a9571d7b
MD		 71 .dev = {
72 .platform_data = &scif4_platform_data,
73 },
74};
75
c01f0f1a 76static struct sh_timer_config tmu0_platform_data = {
c01f0f1a
YS		 77 .channel_offset = 0x04,
78 .timer_bit = 0,
c01f0f1a
YS		 79 .clockevent_rating = 200,
80};
81
82static struct resource tmu0_resources[] = {
83 [0] = {
c01f0f1a
YS		 84 .start = 0xfe430008,
85 .end = 0xfe430013,
86 .flags = IORESOURCE_MEM,
87 },
88 [1] = {
89 .start = 28,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94static struct platform_device tmu0_device = {
95 .name = "sh_tmu",
96 .id = 0,
97 .dev = {
98 .platform_data = &tmu0_platform_data,
99 },
100 .resource = tmu0_resources,
101 .num_resources = ARRAY_SIZE(tmu0_resources),
102};
103
104static struct sh_timer_config tmu1_platform_data = {
c01f0f1a
YS		 105 .channel_offset = 0x10,
106 .timer_bit = 1,
c01f0f1a
YS		 107 .clocksource_rating = 200,
108};
109
110static struct resource tmu1_resources[] = {
111 [0] = {
c01f0f1a
YS		 112 .start = 0xfe430014,
113 .end = 0xfe43001f,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = 29,
118 .flags = IORESOURCE_IRQ,
119 },
120};
121
122static struct platform_device tmu1_device = {
123 .name = "sh_tmu",
124 .id = 1,
125 .dev = {
126 .platform_data = &tmu1_platform_data,
127 },
128 .resource = tmu1_resources,
129 .num_resources = ARRAY_SIZE(tmu1_resources),
130};
131
d0371667
YS		 132static struct resource spi0_resources[] = {
133 [0] = {
134 .start = 0xfe002000,
135 .end = 0xfe0020ff,
11c582e3 136 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
d0371667
YS		 137 },
138 [1] = {
139 .start = 86,
140 .flags = IORESOURCE_IRQ,
141 },
142};
143
8ac53ed5
YS		 144/* DMA */
145static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
146 {
147 .slave_id = SHDMA_SLAVE_SDHI_TX,
148 .addr = 0x1fe50030,
149 .chcr = SM_INC | 0x800 | 0x40000000 |
150 TS_INDEX2VAL(XMIT_SZ_16BIT),
151 .mid_rid = 0xc5,
152 },
153 {
154 .slave_id = SHDMA_SLAVE_SDHI_RX,
155 .addr = 0x1fe50030,
156 .chcr = DM_INC | 0x800 | 0x40000000 |
157 TS_INDEX2VAL(XMIT_SZ_16BIT),
158 .mid_rid = 0xc6,
159 },
160 {
161 .slave_id = SHDMA_SLAVE_MMCIF_TX,
162 .addr = 0x1fcb0034,
163 .chcr = SM_INC | 0x800 | 0x40000000 |
164 TS_INDEX2VAL(XMIT_SZ_32BIT),
165 .mid_rid = 0xd3,
166 },
167 {
168 .slave_id = SHDMA_SLAVE_MMCIF_RX,
169 .addr = 0x1fcb0034,
170 .chcr = DM_INC | 0x800 | 0x40000000 |
171 TS_INDEX2VAL(XMIT_SZ_32BIT),
172 .mid_rid = 0xd7,
173 },
174};
175
176static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
177 {
178 .slave_id = SHDMA_SLAVE_SCIF2_TX,
179 .addr = 0x1f4b000c,
180 .chcr = SM_INC | 0x800 | 0x40000000 |
181 TS_INDEX2VAL(XMIT_SZ_8BIT),
182 .mid_rid = 0x21,
183 },
184 {
185 .slave_id = SHDMA_SLAVE_SCIF2_RX,
186 .addr = 0x1f4b0014,
6afba9e7 187 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 188 TS_INDEX2VAL(XMIT_SZ_8BIT),
189 .mid_rid = 0x22,
190 },
191 {
192 .slave_id = SHDMA_SLAVE_SCIF3_TX,
193 .addr = 0x1f4c000c,
194 .chcr = SM_INC | 0x800 | 0x40000000 |
195 TS_INDEX2VAL(XMIT_SZ_8BIT),
196 .mid_rid = 0x29,
197 },
198 {
199 .slave_id = SHDMA_SLAVE_SCIF3_RX,
200 .addr = 0x1f4c0014,
6afba9e7 201 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 202 TS_INDEX2VAL(XMIT_SZ_8BIT),
203 .mid_rid = 0x2a,
204 },
205 {
206 .slave_id = SHDMA_SLAVE_SCIF4_TX,
207 .addr = 0x1f4d000c,
208 .chcr = SM_INC | 0x800 | 0x40000000 |
209 TS_INDEX2VAL(XMIT_SZ_8BIT),
210 .mid_rid = 0x41,
211 },
212 {
213 .slave_id = SHDMA_SLAVE_SCIF4_RX,
214 .addr = 0x1f4d0014,
6afba9e7 215 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 216 TS_INDEX2VAL(XMIT_SZ_8BIT),
217 .mid_rid = 0x42,
218 },
219};
220
221static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
222 {
223 .slave_id = SHDMA_SLAVE_RIIC0_TX,
224 .addr = 0x1e500012,
225 .chcr = SM_INC | 0x800 | 0x40000000 |
226 TS_INDEX2VAL(XMIT_SZ_8BIT),
227 .mid_rid = 0x21,
228 },
229 {
230 .slave_id = SHDMA_SLAVE_RIIC0_RX,
231 .addr = 0x1e500013,
6afba9e7 232 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 233 TS_INDEX2VAL(XMIT_SZ_8BIT),
234 .mid_rid = 0x22,
235 },
236 {
237 .slave_id = SHDMA_SLAVE_RIIC1_TX,
238 .addr = 0x1e510012,
239 .chcr = SM_INC | 0x800 | 0x40000000 |
240 TS_INDEX2VAL(XMIT_SZ_8BIT),
241 .mid_rid = 0x29,
242 },
243 {
244 .slave_id = SHDMA_SLAVE_RIIC1_RX,
245 .addr = 0x1e510013,
6afba9e7 246 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 247 TS_INDEX2VAL(XMIT_SZ_8BIT),
248 .mid_rid = 0x2a,
249 },
250 {
251 .slave_id = SHDMA_SLAVE_RIIC2_TX,
252 .addr = 0x1e520012,
253 .chcr = SM_INC | 0x800 | 0x40000000 |
254 TS_INDEX2VAL(XMIT_SZ_8BIT),
255 .mid_rid = 0xa1,
256 },
257 {
258 .slave_id = SHDMA_SLAVE_RIIC2_RX,
259 .addr = 0x1e520013,
6afba9e7 260 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 261 TS_INDEX2VAL(XMIT_SZ_8BIT),
262 .mid_rid = 0xa2,
263 },
264 {
265 .slave_id = SHDMA_SLAVE_RIIC3_TX,
266 .addr = 0x1e530012,
267 .chcr = SM_INC | 0x800 | 0x40000000 |
268 TS_INDEX2VAL(XMIT_SZ_8BIT),
6afba9e7 269 .mid_rid = 0xa9,
8ac53ed5
YS		 270 },
271 {
272 .slave_id = SHDMA_SLAVE_RIIC3_RX,
273 .addr = 0x1e530013,
6afba9e7 274 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 275 TS_INDEX2VAL(XMIT_SZ_8BIT),
276 .mid_rid = 0xaf,
277 },
278 {
279 .slave_id = SHDMA_SLAVE_RIIC4_TX,
280 .addr = 0x1e540012,
281 .chcr = SM_INC | 0x800 | 0x40000000 |
282 TS_INDEX2VAL(XMIT_SZ_8BIT),
6afba9e7 283 .mid_rid = 0xc5,
8ac53ed5
YS		 284 },
285 {
286 .slave_id = SHDMA_SLAVE_RIIC4_RX,
287 .addr = 0x1e540013,
6afba9e7 288 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5 289 TS_INDEX2VAL(XMIT_SZ_8BIT),
6afba9e7 290 .mid_rid = 0xc6,
8ac53ed5
YS		 291 },
292};
293
294static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
295 {
296 .slave_id = SHDMA_SLAVE_RIIC5_TX,
297 .addr = 0x1e550012,
298 .chcr = SM_INC | 0x800 | 0x40000000 |
299 TS_INDEX2VAL(XMIT_SZ_8BIT),
300 .mid_rid = 0x21,
301 },
302 {
303 .slave_id = SHDMA_SLAVE_RIIC5_RX,
304 .addr = 0x1e550013,
6afba9e7 305 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 306 TS_INDEX2VAL(XMIT_SZ_8BIT),
307 .mid_rid = 0x22,
308 },
309 {
310 .slave_id = SHDMA_SLAVE_RIIC6_TX,
311 .addr = 0x1e560012,
312 .chcr = SM_INC | 0x800 | 0x40000000 |
313 TS_INDEX2VAL(XMIT_SZ_8BIT),
314 .mid_rid = 0x29,
315 },
316 {
317 .slave_id = SHDMA_SLAVE_RIIC6_RX,
318 .addr = 0x1e560013,
6afba9e7 319 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 320 TS_INDEX2VAL(XMIT_SZ_8BIT),
321 .mid_rid = 0x2a,
322 },
323 {
324 .slave_id = SHDMA_SLAVE_RIIC7_TX,
325 .addr = 0x1e570012,
326 .chcr = SM_INC | 0x800 | 0x40000000 |
327 TS_INDEX2VAL(XMIT_SZ_8BIT),
328 .mid_rid = 0x41,
329 },
330 {
331 .slave_id = SHDMA_SLAVE_RIIC7_RX,
332 .addr = 0x1e570013,
6afba9e7 333 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 334 TS_INDEX2VAL(XMIT_SZ_8BIT),
335 .mid_rid = 0x42,
336 },
337 {
338 .slave_id = SHDMA_SLAVE_RIIC8_TX,
339 .addr = 0x1e580012,
340 .chcr = SM_INC | 0x800 | 0x40000000 |
341 TS_INDEX2VAL(XMIT_SZ_8BIT),
342 .mid_rid = 0x45,
343 },
344 {
345 .slave_id = SHDMA_SLAVE_RIIC8_RX,
346 .addr = 0x1e580013,
6afba9e7 347 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 348 TS_INDEX2VAL(XMIT_SZ_8BIT),
349 .mid_rid = 0x46,
350 },
351 {
352 .slave_id = SHDMA_SLAVE_RIIC9_TX,
353 .addr = 0x1e590012,
354 .chcr = SM_INC | 0x800 | 0x40000000 |
355 TS_INDEX2VAL(XMIT_SZ_8BIT),
356 .mid_rid = 0x51,
357 },
358 {
359 .slave_id = SHDMA_SLAVE_RIIC9_RX,
360 .addr = 0x1e590013,
6afba9e7 361 .chcr = DM_INC | 0x800 | 0x40000000 |
8ac53ed5
YS		 362 TS_INDEX2VAL(XMIT_SZ_8BIT),
363 .mid_rid = 0x52,
364 },
365};
366
367static const struct sh_dmae_channel sh7757_dmae_channels[] = {
368 {
369 .offset = 0,
370 .dmars = 0,
371 .dmars_bit = 0,
372 }, {
373 .offset = 0x10,
374 .dmars = 0,
375 .dmars_bit = 8,
376 }, {
377 .offset = 0x20,
378 .dmars = 4,
379 .dmars_bit = 0,
380 }, {
381 .offset = 0x30,
382 .dmars = 4,
383 .dmars_bit = 8,
384 }, {
385 .offset = 0x50,
386 .dmars = 8,
387 .dmars_bit = 0,
388 }, {
389 .offset = 0x60,
390 .dmars = 8,
391 .dmars_bit = 8,
392 }
393};
394
395static const unsigned int ts_shift[] = TS_SHIFT;
396
397static struct sh_dmae_pdata dma0_platform_data = {
398 .slave = sh7757_dmae0_slaves,
399 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
400 .channel = sh7757_dmae_channels,
401 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
402 .ts_low_shift = CHCR_TS_LOW_SHIFT,
403 .ts_low_mask = CHCR_TS_LOW_MASK,
404 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
405 .ts_high_mask = CHCR_TS_HIGH_MASK,
406 .ts_shift = ts_shift,
407 .ts_shift_num = ARRAY_SIZE(ts_shift),
408 .dmaor_init = DMAOR_INIT,
409};
410
411static struct sh_dmae_pdata dma1_platform_data = {
412 .slave = sh7757_dmae1_slaves,
413 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
414 .channel = sh7757_dmae_channels,
415 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
416 .ts_low_shift = CHCR_TS_LOW_SHIFT,
417 .ts_low_mask = CHCR_TS_LOW_MASK,
418 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
419 .ts_high_mask = CHCR_TS_HIGH_MASK,
420 .ts_shift = ts_shift,
421 .ts_shift_num = ARRAY_SIZE(ts_shift),
422 .dmaor_init = DMAOR_INIT,
423};
424
425static struct sh_dmae_pdata dma2_platform_data = {
426 .slave = sh7757_dmae2_slaves,
427 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
428 .channel = sh7757_dmae_channels,
429 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
430 .ts_low_shift = CHCR_TS_LOW_SHIFT,
431 .ts_low_mask = CHCR_TS_LOW_MASK,
432 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
433 .ts_high_mask = CHCR_TS_HIGH_MASK,
434 .ts_shift = ts_shift,
435 .ts_shift_num = ARRAY_SIZE(ts_shift),
436 .dmaor_init = DMAOR_INIT,
437};
438
439static struct sh_dmae_pdata dma3_platform_data = {
440 .slave = sh7757_dmae3_slaves,
441 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
442 .channel = sh7757_dmae_channels,
443 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
444 .ts_low_shift = CHCR_TS_LOW_SHIFT,
445 .ts_low_mask = CHCR_TS_LOW_MASK,
446 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
447 .ts_high_mask = CHCR_TS_HIGH_MASK,
448 .ts_shift = ts_shift,
449 .ts_shift_num = ARRAY_SIZE(ts_shift),
450 .dmaor_init = DMAOR_INIT,
451};
452
453/* channel 0 to 5 */
454static struct resource sh7757_dmae0_resources[] = {
455 [0] = {
456 /* Channel registers and DMAOR */
457 .start = 0xff608020,
458 .end = 0xff60808f,
459 .flags = IORESOURCE_MEM,
460 },
461 [1] = {
462 /* DMARSx */
463 .start = 0xff609000,
464 .end = 0xff60900b,
465 .flags = IORESOURCE_MEM,
466 },
467 {
a4d52473 468 .name = "error_irq",
8ac53ed5
YS		 469 .start = 34,
470 .end = 34,
471 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
472 },
473};
474
475/* channel 6 to 11 */
476static struct resource sh7757_dmae1_resources[] = {
477 [0] = {
478 /* Channel registers and DMAOR */
479 .start = 0xff618020,
480 .end = 0xff61808f,
481 .flags = IORESOURCE_MEM,
482 },
483 [1] = {
484 /* DMARSx */
485 .start = 0xff619000,
486 .end = 0xff61900b,
487 .flags = IORESOURCE_MEM,
488 },
489 {
a4d52473 490 .name = "error_irq",
8ac53ed5
YS		 491 .start = 34,
492 .end = 34,
493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
494 },
495 {
496 /* IRQ for channels 4 */
497 .start = 46,
498 .end = 46,
499 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
500 },
501 {
502 /* IRQ for channels 5 */
503 .start = 46,
504 .end = 46,
505 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
506 },
507 {
508 /* IRQ for channels 6 */
509 .start = 88,
510 .end = 88,
511 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
512 },
513 {
514 /* IRQ for channels 7 */
515 .start = 88,
516 .end = 88,
517 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
518 },
519 {
520 /* IRQ for channels 8 */
521 .start = 88,
522 .end = 88,
523 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
524 },
525 {
526 /* IRQ for channels 9 */
527 .start = 88,
528 .end = 88,
529 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
530 },
531 {
532 /* IRQ for channels 10 */
533 .start = 88,
534 .end = 88,
535 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
536 },
537 {
538 /* IRQ for channels 11 */
539 .start = 88,
540 .end = 88,
541 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
542 },
543};
544
545/* channel 12 to 17 */
546static struct resource sh7757_dmae2_resources[] = {
547 [0] = {
548 /* Channel registers and DMAOR */
549 .start = 0xff708020,
550 .end = 0xff70808f,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 /* DMARSx */
555 .start = 0xff709000,
556 .end = 0xff70900b,
557 .flags = IORESOURCE_MEM,
558 },
559 {
a4d52473 560 .name = "error_irq",
8ac53ed5
YS		 561 .start = 323,
562 .end = 323,
563 .flags = IORESOURCE_IRQ,
564 },
565 {
566 /* IRQ for channels 12 to 16 */
567 .start = 272,
568 .end = 276,
569 .flags = IORESOURCE_IRQ,
570 },
571 {
572 /* IRQ for channel 17 */
573 .start = 279,
574 .end = 279,
575 .flags = IORESOURCE_IRQ,
576 },
577};
578
579/* channel 18 to 23 */
580static struct resource sh7757_dmae3_resources[] = {
581 [0] = {
582 /* Channel registers and DMAOR */
583 .start = 0xff718020,
584 .end = 0xff71808f,
585 .flags = IORESOURCE_MEM,
586 },
587 [1] = {
588 /* DMARSx */
589 .start = 0xff719000,
590 .end = 0xff71900b,
591 .flags = IORESOURCE_MEM,
592 },
593 {
a4d52473 594 .name = "error_irq",
8ac53ed5
YS		 595 .start = 324,
596 .end = 324,
597 .flags = IORESOURCE_IRQ,
598 },
599 {
600 /* IRQ for channels 18 to 22 */
601 .start = 280,
602 .end = 284,
603 .flags = IORESOURCE_IRQ,
604 },
605 {
606 /* IRQ for channel 23 */
607 .start = 288,
608 .end = 288,
609 .flags = IORESOURCE_IRQ,
610 },
611};
612
613static struct platform_device dma0_device = {
614 .name = "sh-dma-engine",
615 .id = 0,
616 .resource = sh7757_dmae0_resources,
617 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
618 .dev = {
619 .platform_data = &dma0_platform_data,
620 },
621};
622
623static struct platform_device dma1_device = {
624 .name = "sh-dma-engine",
625 .id = 1,
626 .resource = sh7757_dmae1_resources,
627 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
628 .dev = {
629 .platform_data = &dma1_platform_data,
630 },
631};
632
633static struct platform_device dma2_device = {
634 .name = "sh-dma-engine",
635 .id = 2,
636 .resource = sh7757_dmae2_resources,
637 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
638 .dev = {
639 .platform_data = &dma2_platform_data,
640 },
641};
642
643static struct platform_device dma3_device = {
644 .name = "sh-dma-engine",
645 .id = 3,
646 .resource = sh7757_dmae3_resources,
647 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
648 .dev = {
649 .platform_data = &dma3_platform_data,
650 },
651};
652
d0371667
YS		 653static struct platform_device spi0_device = {
654 .name = "sh_spi",
655 .id = 0,
656 .dev = {
657 .dma_mask = NULL,
658 .coherent_dma_mask = 0xffffffff,
659 },
660 .num_resources = ARRAY_SIZE(spi0_resources),
661 .resource = spi0_resources,
662};
663
a206c008
SY		 664static struct resource spi1_resources[] = {
665 {
666 .start = 0xffd8ee70,
667 .end = 0xffd8eeff,
668 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
669 },
670 {
671 .start = 54,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676static struct platform_device spi1_device = {
677 .name = "sh_spi",
678 .id = 1,
679 .num_resources = ARRAY_SIZE(spi1_resources),
680 .resource = spi1_resources,
681};
682
f2b97261
YS		 683static struct resource usb_ehci_resources[] = {
684 [0] = {
685 .start = 0xfe4f1000,
686 .end = 0xfe4f10ff,
687 .flags = IORESOURCE_MEM,
688 },
689 [1] = {
690 .start = 57,
691 .end = 57,
692 .flags = IORESOURCE_IRQ,
693 },
694};
695
696static struct platform_device usb_ehci_device = {
697 .name = "sh_ehci",
698 .id = -1,
699 .dev = {
700 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
701 .coherent_dma_mask = DMA_BIT_MASK(32),
702 },
703 .num_resources = ARRAY_SIZE(usb_ehci_resources),
704 .resource = usb_ehci_resources,
705};
706
707static struct resource usb_ohci_resources[] = {
708 [0] = {
709 .start = 0xfe4f1800,
710 .end = 0xfe4f18ff,
711 .flags = IORESOURCE_MEM,
712 },
713 [1] = {
714 .start = 57,
715 .end = 57,
716 .flags = IORESOURCE_IRQ,
717 },
718};
719
720static struct platform_device usb_ohci_device = {
721 .name = "sh_ohci",
722 .id = -1,
723 .dev = {
724 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
725 .coherent_dma_mask = DMA_BIT_MASK(32),
726 },
727 .num_resources = ARRAY_SIZE(usb_ohci_resources),
728 .resource = usb_ohci_resources,
729};
730
c01f0f1a 731static struct platform_device *sh7757_devices[] __initdata = {
a9571d7b
MD		 732 &scif2_device,
733 &scif3_device,
734 &scif4_device,
c01f0f1a
YS		 735 &tmu0_device,
736 &tmu1_device,
8ac53ed5
YS		 737 &dma0_device,
738 &dma1_device,
739 &dma2_device,
740 &dma3_device,
d0371667 741 &spi0_device,
a206c008 742 &spi1_device,
f2b97261
YS		 743 &usb_ehci_device,
744 &usb_ohci_device,
c01f0f1a
YS		 745};
746
747static int __init sh7757_devices_setup(void)
748{
749 return platform_add_devices(sh7757_devices,
750 ARRAY_SIZE(sh7757_devices));
751}
752arch_initcall(sh7757_devices_setup);
753
a9571d7b
MD		 754static struct platform_device *sh7757_early_devices[] __initdata = {
755 &scif2_device,
756 &scif3_device,
757 &scif4_device,
758 &tmu0_device,
759 &tmu1_device,
760};
761
762void __init plat_early_device_setup(void)
763{
764 early_platform_add_devices(sh7757_early_devices,
765 ARRAY_SIZE(sh7757_early_devices));
766}
767
c01f0f1a
YS		 768enum {
769 UNUSED = 0,
770
771 /* interrupt sources */
772
773 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
774 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
775 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
776 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
777
778 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
779 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
780 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
781 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
782 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
783
c3721d5b
YS		 784 SDHI, DVC,
785 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
786 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
c01f0f1a 787 HUDI,
c01f0f1a 788 ARC4,
c3721d5b
YS		 789 DMAC0_5, DMAC6_7, DMAC8_11,
790 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
791 USB0, USB1,
c01f0f1a 792 JMC,
c3721d5b 793 SPI0, SPI1,
c01f0f1a 794 TMR01, TMR23, TMR45,
c01f0f1a 795 FRT,
c3721d5b
YS		 796 LPC, LPC5, LPC6, LPC7, LPC8,
797 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
c01f0f1a 798 ETHERC,
c3721d5b 799 ADC0, ADC1,
c01f0f1a 800 SIM,
c01f0f1a
YS		 801 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
802 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
803 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
804 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
805 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
806 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
807 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
808 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
809 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
810 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
c3721d5b
YS		 811 ONFICTL,
812 MMC1, MMC2,
813 ECCU,
814 PCIC,
815 G200,
816 RSPI,
c01f0f1a 817 SGPIO,
c3721d5b
YS		 818 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
819 DMINT20, DMINT21, DMINT22, DMINT23,
820 DDRECC,
821 TSIP,
822 PCIE_BRIDGE,
823 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
824 GETHER0, GETHER1, GETHER2,
825 PBIA, PBIB, PBIC,
826 DMAE2, DMAE3,
827 SERMUX2, SERMUX3,
c01f0f1a
YS		 828
829 /* interrupt groups */
830
831 TMU012, TMU345,
832};
833
834static struct intc_vect vectors[] __initdata = {
835 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
836 INTC_VECT(SDHI, 0x4c0),
837 INTC_VECT(DVC, 0x4e0),
838 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
839 INTC_VECT(IRQ10, 0x540),
c01f0f1a
YS		 840 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
841 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
842 INTC_VECT(HUDI, 0x600),
843 INTC_VECT(ARC4, 0x620),
c3721d5b
YS		 844 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
845 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
846 INTC_VECT(DMAC0_5, 0x6c0),
c01f0f1a
YS		 847 INTC_VECT(IRQ11, 0x6e0),
848 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
849 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
c3721d5b
YS		 850 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
851 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
c01f0f1a
YS		 852 INTC_VECT(USB0, 0x840),
853 INTC_VECT(IRQ12, 0x880),
854 INTC_VECT(JMC, 0x8a0),
855 INTC_VECT(SPI1, 0x8c0),
856 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
857 INTC_VECT(USB1, 0x920),
858 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
859 INTC_VECT(TMR45, 0xa40),
c01f0f1a
YS		 860 INTC_VECT(FRT, 0xa80),
861 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
862 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
863 INTC_VECT(LPC, 0xb20),
864 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
865 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
866 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
c3721d5b
YS		 867 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
868 INTC_VECT(PECI2, 0xc40),
c01f0f1a
YS		 869 INTC_VECT(IRQ15, 0xc60),
870 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
871 INTC_VECT(SPI0, 0xcc0),
872 INTC_VECT(ADC1, 0xce0),
c3721d5b
YS		 873 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
874 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
c01f0f1a
YS		 875 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
876 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
877 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
878 INTC_VECT(TMU5, 0xe40),
879 INTC_VECT(ADC0, 0xe60),
880 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
881 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
882 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
883 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
884 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
885 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
886 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
887 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
888 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
889 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
890 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
891 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
892 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
893 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
894 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
c3721d5b
YS		 895 INTC_VECT(IIC6_2, 0x1920),
896 INTC_VECT(ONFICTL, 0x1960),
897 INTC_VECT(IIC6_3, 0x1980),
c01f0f1a
YS		 898 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
899 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
900 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
901 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
902 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
903 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
c3721d5b
YS		 904 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
905 INTC_VECT(ECCU, 0x1cc0),
906 INTC_VECT(PCIC, 0x1ce0),
907 INTC_VECT(G200, 0x1d00),
908 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
909 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
910 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
911 INTC_VECT(PECI5, 0x1f00),
912 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
913 INTC_VECT(SGPIO, 0x1fc0),
914 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
915 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
916 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
917 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
918 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
919 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
920 INTC_VECT(DDRECC, 0x2620),
921 INTC_VECT(TSIP, 0x2640),
922 INTC_VECT(PCIE_BRIDGE, 0x27c0),
923 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
924 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
925 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
926 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
927 INTC_VECT(WDT8B, 0x2900),
928 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
929 INTC_VECT(GETHER2, 0x29a0),
930 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
931 INTC_VECT(PBIC, 0x2a40),
932 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
933 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
934 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
935 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
c01f0f1a
YS		 936};
937
938static struct intc_group groups[] __initdata = {
939 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
940 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
941};
942
943static struct intc_mask_reg mask_registers[] __initdata = {
944 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
945 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
946
947 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
948 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
949 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
950 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
951 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
952 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
953 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
954 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
955 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
956
957 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
958 { 0, 0, 0, 0, 0, 0, 0, 0,
c3721d5b
YS		 959 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
960 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
961 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
c01f0f1a
YS		 962 } },
963
964 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
965 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
966 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
c3721d5b 967 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
c01f0f1a
YS		 968 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
969 } },
970
971 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
c3721d5b
YS		 972 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
973 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
c01f0f1a 974 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
c3721d5b 975 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
c01f0f1a
YS		 976 } },
977
c3721d5b
YS		 978 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
979 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
c01f0f1a 980 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
c3721d5b 981 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
c01f0f1a
YS		 982 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
983 } },
c3721d5b
YS		 984
985 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
986 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
987 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
988 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
989 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
990 } },
991
992 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
993 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
994 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
995 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
996 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
997 } },
c01f0f1a
YS		 998};
999
1000#define INTPRI 0xffd00010
1001#define INT2PRI0 0xffd40000
1002#define INT2PRI1 0xffd40004
1003#define INT2PRI2 0xffd40008
1004#define INT2PRI3 0xffd4000c
1005#define INT2PRI4 0xffd40010
1006#define INT2PRI5 0xffd40014
1007#define INT2PRI6 0xffd40018
1008#define INT2PRI7 0xffd4001c
1009#define INT2PRI8 0xffd400a0
1010#define INT2PRI9 0xffd400a4
1011#define INT2PRI10 0xffd400a8
1012#define INT2PRI11 0xffd400ac
1013#define INT2PRI12 0xffd400b0
1014#define INT2PRI13 0xffd400b4
1015#define INT2PRI14 0xffd400b8
1016#define INT2PRI15 0xffd400bc
1017#define INT2PRI16 0xffd10000
1018#define INT2PRI17 0xffd10004
1019#define INT2PRI18 0xffd10008
1020#define INT2PRI19 0xffd1000c
1021#define INT2PRI20 0xffd10010
1022#define INT2PRI21 0xffd10014
1023#define INT2PRI22 0xffd10018
1024#define INT2PRI23 0xffd1001c
1025#define INT2PRI24 0xffd100a0
1026#define INT2PRI25 0xffd100a4
1027#define INT2PRI26 0xffd100a8
1028#define INT2PRI27 0xffd100ac
1029#define INT2PRI28 0xffd100b0
1030#define INT2PRI29 0xffd100b4
1031#define INT2PRI30 0xffd100b8
1032#define INT2PRI31 0xffd100bc
c3721d5b
YS		 1033#define INT2PRI32 0xffd20000
1034#define INT2PRI33 0xffd20004
1035#define INT2PRI34 0xffd20008
1036#define INT2PRI35 0xffd2000c
1037#define INT2PRI36 0xffd20010
1038#define INT2PRI37 0xffd20014
1039#define INT2PRI38 0xffd20018
1040#define INT2PRI39 0xffd2001c
1041#define INT2PRI40 0xffd200a0
1042#define INT2PRI41 0xffd200a4
1043#define INT2PRI42 0xffd200a8
1044#define INT2PRI43 0xffd200ac
1045#define INT2PRI44 0xffd200b0
1046#define INT2PRI45 0xffd200b4
1047#define INT2PRI46 0xffd200b8
1048#define INT2PRI47 0xffd200bc
c01f0f1a
YS		 1049
1050static struct intc_prio_reg prio_registers[] __initdata = {
1051 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1052 IRQ4, IRQ5, IRQ6, IRQ7 } },
1053
1054 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1055 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
c3721d5b
YS		 1056 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1057 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
c01f0f1a 1058 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
c3721d5b
YS		 1059 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1060 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
c01f0f1a
YS		 1061 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1062 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1063 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
c3721d5b
YS		 1064 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1065 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
c01f0f1a
YS		 1066 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1067 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1068
1069 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
c3721d5b 1070 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
c01f0f1a
YS		 1071 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1072 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1073 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1074 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
c3721d5b
YS		 1075 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1076 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1077 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
c01f0f1a 1078 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
c3721d5b
YS		 1079 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1080 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1081 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
c01f0f1a 1082 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
c3721d5b 1083 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
c01f0f1a 1084 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
c3721d5b
YS		 1085 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1086 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1087 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1088 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1089 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1090 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1091 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1092 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1093 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1094 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1095 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1096 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1097 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1098 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1099 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1100 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1101};
1102
1103static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1104 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
1105 IRQ11, IRQ10, IRQ9, IRQ8 } },
c01f0f1a
YS		 1106};
1107
1108static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
c3721d5b
YS		 1109 mask_registers, prio_registers,
1110 sense_registers_irq8to15);
c01f0f1a
YS		 1111
1112/* Support for external interrupt pins in IRQ mode */
1113static struct intc_vect vectors_irq0123[] __initdata = {
b00c2c79
YS		 1114 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1115 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
c01f0f1a
YS		 1116};
1117
1118static struct intc_vect vectors_irq4567[] __initdata = {
b00c2c79
YS		 1119 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1120 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
c01f0f1a
YS		 1121};
1122
1123static struct intc_sense_reg sense_registers[] __initdata = {
1124 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
1125 IRQ4, IRQ5, IRQ6, IRQ7 } },
1126};
1127
1128static struct intc_mask_reg ack_registers[] __initdata = {
1129 { 0xffd00024, 0, 32, /* INTREQ */
1130 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1131};
1132
1133static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1134 vectors_irq0123, NULL, mask_registers,
1135 prio_registers, sense_registers, ack_registers);
1136
1137static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1138 vectors_irq4567, NULL, mask_registers,
1139 prio_registers, sense_registers, ack_registers);
1140
1141/* External interrupt pins in IRL mode */
1142static struct intc_vect vectors_irl0123[] __initdata = {
1143 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1144 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1145 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1146 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1147 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1148 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1149 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1150 INTC_VECT(IRL0_HHHL, 0x3c0),
1151};
1152
1153static struct intc_vect vectors_irl4567[] __initdata = {
b00c2c79
YS		 1154 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1155 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1156 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1157 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1158 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1159 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1160 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1161 INTC_VECT(IRL4_HHHL, 0x3c0),
c01f0f1a
YS		 1162};
1163
1164static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1165 NULL, mask_registers, NULL, NULL);
1166
1167static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1168 NULL, mask_registers, NULL, NULL);
1169
1170#define INTC_ICR0 0xffd00000
1171#define INTC_INTMSK0 0xffd00044
1172#define INTC_INTMSK1 0xffd00048
1173#define INTC_INTMSK2 0xffd40080
1174#define INTC_INTMSKCLR1 0xffd00068
1175#define INTC_INTMSKCLR2 0xffd40084
1176
1177void __init plat_irq_setup(void)
1178{
1179 /* disable IRQ3-0 + IRQ7-4 */
9d56dd3b 1180 __raw_writel(0xff000000, INTC_INTMSK0);
c01f0f1a
YS		 1181
1182 /* disable IRL3-0 + IRL7-4 */
9d56dd3b
PM		 1183 __raw_writel(0xc0000000, INTC_INTMSK1);
1184 __raw_writel(0xfffefffe, INTC_INTMSK2);
c01f0f1a
YS		 1185
1186 /* select IRL mode for IRL3-0 + IRL7-4 */
9d56dd3b 1187 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
c01f0f1a
YS		 1188
1189 /* disable holding function, ie enable "SH-4 Mode" */
9d56dd3b 1190 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
c01f0f1a
YS		 1191
1192 register_intc_controller(&intc_desc);
1193}
1194
1195void __init plat_irq_setup_pins(int mode)
1196{
1197 switch (mode) {
1198 case IRQ_MODE_IRQ7654:
1199 /* select IRQ mode for IRL7-4 */
9d56dd3b 1200 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
c01f0f1a
YS		 1201 register_intc_controller(&intc_desc_irq4567);
1202 break;
1203 case IRQ_MODE_IRQ3210:
1204 /* select IRQ mode for IRL3-0 */
9d56dd3b 1205 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
c01f0f1a
YS		 1206 register_intc_controller(&intc_desc_irq0123);
1207 break;
1208 case IRQ_MODE_IRL7654:
1209 /* enable IRL7-4 but don't provide any masking */
9d56dd3b
PM		 1210 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1211 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
c01f0f1a
YS		 1212 break;
1213 case IRQ_MODE_IRL3210:
1214 /* enable IRL0-3 but don't provide any masking */
9d56dd3b
PM		 1215 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1216 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
c01f0f1a
YS		 1217 break;
1218 case IRQ_MODE_IRL7654_MASK:
1219 /* enable IRL7-4 and mask using cpu intc controller */
9d56dd3b 1220 __raw_writel(0x40000000, INTC_INTMSKCLR1);
c01f0f1a
YS		 1221 register_intc_controller(&intc_desc_irl4567);
1222 break;
1223 case IRQ_MODE_IRL3210_MASK:
1224 /* enable IRL0-3 and mask using cpu intc controller */
9d56dd3b 1225 __raw_writel(0x80000000, INTC_INTMSKCLR1);
c01f0f1a
YS		 1226 register_intc_controller(&intc_desc_irl0123);
1227 break;
1228 default:
1229 BUG();
1230 }
1231}
1232
1233void __init plat_mem_setup(void)
1234{
1235}
Linux kernel - Deliverables
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