[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7780.c

/*
 * SH7780 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <asm/dma-sh.h>

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xffe00000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 40, 40, 40, 40 },
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xffe10000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 76, 76, 76, 76 },
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct sh_timer_config tmu0_platform_data = {
	.name = "TMU0",
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clk = "peripheral_clk",
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.name	= "TMU0",
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.name = "TMU1",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clk = "peripheral_clk",
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.name	= "TMU1",
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 29,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.name = "TMU2",
	.channel_offset = 0x1c,
	.timer_bit = 2,
	.clk = "peripheral_clk",
};

static struct resource tmu2_resources[] = {
	[0] = {
		.name	= "TMU2",
		.start	= 0xffd80020,
		.end	= 0xffd8002f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 30,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};

static struct sh_timer_config tmu3_platform_data = {
	.name = "TMU3",
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clk = "peripheral_clk",
};

static struct resource tmu3_resources[] = {
	[0] = {
		.name	= "TMU3",
		.start	= 0xffdc0008,
		.end	= 0xffdc0013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 96,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu3_device = {
	.name		= "sh_tmu",
	.id		= 3,
	.dev = {
		.platform_data	= &tmu3_platform_data,
	},
	.resource	= tmu3_resources,
	.num_resources	= ARRAY_SIZE(tmu3_resources),
};

static struct sh_timer_config tmu4_platform_data = {
	.name = "TMU4",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clk = "peripheral_clk",
};

static struct resource tmu4_resources[] = {
	[0] = {
		.name	= "TMU4",
		.start	= 0xffdc0014,
		.end	= 0xffdc001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 97,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu4_device = {
	.name		= "sh_tmu",
	.id		= 4,
	.dev = {
		.platform_data	= &tmu4_platform_data,
	},
	.resource	= tmu4_resources,
	.num_resources	= ARRAY_SIZE(tmu4_resources),
};

static struct sh_timer_config tmu5_platform_data = {
	.name = "TMU5",
	.channel_offset = 0x1c,
	.timer_bit = 2,
	.clk = "peripheral_clk",
};

static struct resource tmu5_resources[] = {
	[0] = {
		.name	= "TMU5",
		.start	= 0xffdc0020,
		.end	= 0xffdc002b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 98,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu5_device = {
	.name		= "sh_tmu",
	.id		= 5,
	.dev = {
		.platform_data	= &tmu5_platform_data,
	},
	.resource	= tmu5_resources,
	.num_resources	= ARRAY_SIZE(tmu5_resources),
};

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xffe80000,
		.end	= 0xffe80000 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Shared Period/Carry/Alarm IRQ */
		.start	= 20,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

/* DMA */
static struct sh_dmae_channel sh7780_dmae0_channels[] = {
	{
		.offset = 0,
		.dmars = 0,
		.dmars_bit = 0,
	}, {
		.offset = 0x10,
		.dmars = 0,
		.dmars_bit = 8,
	}, {
		.offset = 0x20,
		.dmars = 4,
		.dmars_bit = 0,
	}, {
		.offset = 0x30,
		.dmars = 4,
		.dmars_bit = 8,
	}, {
		.offset = 0x50,
		.dmars = 8,
		.dmars_bit = 0,
	}, {
		.offset = 0x60,
		.dmars = 8,
		.dmars_bit = 8,
	}
};

static struct sh_dmae_channel sh7780_dmae1_channels[] = {
	{
		.offset = 0,
	}, {
		.offset = 0x10,
	}, {
		.offset = 0x20,
	}, {
		.offset = 0x30,
	}, {
		.offset = 0x50,
	}, {
		.offset = 0x60,
	}
};

static struct sh_dmae_pdata dma0_platform_data = {
	.channel	= sh7780_dmae0_channels,
	.channel_num	= ARRAY_SIZE(sh7780_dmae0_channels),
};

static struct sh_dmae_pdata dma1_platform_data = {
	.channel	= sh7780_dmae1_channels,
	.channel_num	= ARRAY_SIZE(sh7780_dmae1_channels),
};

static struct resource sh7780_dmae0_resources[] = {
	[0] = {
		/* Channel registers and DMAOR */
		.start	= 0xfc808020,
		.end	= 0xfc80808f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* DMARSx */
		.start	= 0xfc809000,
		.end	= 0xfc80900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
		.start	= 34,
		.end	= 34,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
	},
};

static struct resource sh7780_dmae1_resources[] = {
	[0] = {
		/* Channel registers and DMAOR */
		.start	= 0xfc818020,
		.end	= 0xfc81808f,
		.flags	= IORESOURCE_MEM,
	},
	/* DMAC1 has no DMARS */
	{
		/* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
		.start	= 46,
		.end	= 46,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
	},
};

static struct platform_device dma0_device = {
	.name           = "sh-dma-engine",
	.id             = 0,
	.resource	= sh7780_dmae0_resources,
	.num_resources	= ARRAY_SIZE(sh7780_dmae0_resources),
	.dev            = {
		.platform_data	= &dma0_platform_data,
	},
};

static struct platform_device dma1_device = {
	.name		= "sh-dma-engine",
	.id		= 1,
	.resource	= sh7780_dmae1_resources,
	.num_resources	= ARRAY_SIZE(sh7780_dmae1_resources),
	.dev		= {
		.platform_data	= &dma1_platform_data,
	},
};

static struct platform_device *sh7780_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&tmu3_device,
	&tmu4_device,
	&tmu5_device,
	&rtc_device,
	&dma0_device,
	&dma1_device,
};

static int __init sh7780_devices_setup(void)
{
	return platform_add_devices(sh7780_devices,
				    ARRAY_SIZE(sh7780_devices));
}
arch_initcall(sh7780_devices_setup);
static struct platform_device *sh7780_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&tmu3_device,
	&tmu4_device,
	&tmu5_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7780_early_devices,
				   ARRAY_SIZE(sh7780_early_devices));
}

enum {
	UNUSED = 0,

	/* interrupt sources */

	IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
	IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
	IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
	IRL_HHLL, IRL_HHLH, IRL_HHHL,

	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
	HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
	PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
	SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL,	GPIO,

	/* interrupt groups */

	TMU012,	TMU345,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
	INTC_VECT(RTC, 0x4c0),
	INTC_VECT(WDT, 0x560),
	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
	INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
	INTC_VECT(HUDI, 0x600),
	INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
	INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
	INTC_VECT(DMAC0, 0x6c0),
	INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
	INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
	INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
	INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
	INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
	INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
	INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
	INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
	INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
	INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
	INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
	INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
	INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
	INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
	INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
	INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
	INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
	INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
	INTC_VECT(TMU5, 0xe40),
	INTC_VECT(SSI, 0xe80),
	INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
	INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
	INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
	INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
	INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
	  { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
	    SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
	    PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
	    HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
						 TMU2, TMU2_TICPI } },
	{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
	{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
	{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
	{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
						 PCISERR, PCIINTA, } },
	{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
						 PCIINTD, PCIC5 } },
	{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
	{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
			 mask_registers, prio_registers, NULL);

/* Support for external interrupt pins in IRQ mode */

static struct intc_vect irq_vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
	INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
	INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
};

static struct intc_mask_reg irq_mask_registers[] __initdata = {
	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg irq_prio_registers[] __initdata = {
	{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
					       IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg irq_sense_registers[] __initdata = {
	{ 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
					    IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg irq_ack_registers[] __initdata = {
	{ 0xffd00024, 0, 32, /* INTREQ */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
			     NULL, irq_mask_registers, irq_prio_registers,
			     irq_sense_registers, irq_ack_registers);

/* External interrupt pins in IRL mode */

static struct intc_vect irl_vectors[] __initdata = {
	INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
	INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
	INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
	INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
	INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
	INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
	INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
	INTC_VECT(IRL_HHHL, 0x3c0),
};

static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
	  { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
	    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
	    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
	    IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
};

static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	    IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
	    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
	    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
	    IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
};

static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
			 NULL, irl7654_mask_registers, NULL, NULL);

static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
			 NULL, irl3210_mask_registers, NULL, NULL);

#define INTC_ICR0	0xffd00000
#define INTC_INTMSK0	0xffd00044
#define INTC_INTMSK1	0xffd00048
#define INTC_INTMSK2	0xffd40080
#define INTC_INTMSKCLR1	0xffd00068
#define INTC_INTMSKCLR2	0xffd40084

void __init plat_irq_setup(void)
{
	/* disable IRQ7-0 */
	__raw_writel(0xff000000, INTC_INTMSK0);

	/* disable IRL3-0 + IRL7-4 */
	__raw_writel(0xc0000000, INTC_INTMSK1);
	__raw_writel(0xfffefffe, INTC_INTMSK2);

	/* select IRL mode for IRL3-0 + IRL7-4 */
	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);

	/* disable holding function, ie enable "SH-4 Mode" */
	__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);

	register_intc_controller(&intc_desc);
}

void __init plat_irq_setup_pins(int mode)
{
	switch (mode) {
	case IRQ_MODE_IRQ:
		/* select IRQ mode for IRL3-0 + IRL7-4 */
		__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
		register_intc_controller(&intc_irq_desc);
		break;
	case IRQ_MODE_IRL7654:
		/* enable IRL7-4 but don't provide any masking */
		__raw_writel(0x40000000, INTC_INTMSKCLR1);
		__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
		break;
	case IRQ_MODE_IRL3210:
		/* enable IRL0-3 but don't provide any masking */
		__raw_writel(0x80000000, INTC_INTMSKCLR1);
		__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
		break;
	case IRQ_MODE_IRL7654_MASK:
		/* enable IRL7-4 and mask using cpu intc controller */
		__raw_writel(0x40000000, INTC_INTMSKCLR1);
		register_intc_controller(&intc_irl7654_desc);
		break;
	case IRQ_MODE_IRL3210_MASK:
		/* enable IRL0-3 and mask using cpu intc controller */
		__raw_writel(0x80000000, INTC_INTMSKCLR1);
		register_intc_controller(&intc_irl3210_desc);
		break;
	default:
		BUG();
	}
}
Commit	Line	Data
959f85f8 PM	1	/*
	2	* SH7780 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
953c8ef2	13	#include <linux/io.h>
96de1a8f	14	#include <linux/serial_sci.h>
ccc19565	15	#include <linux/sh_timer.h>
ecb6fd52	16	#include <asm/dma-sh.h>
ccc19565	17
a9571d7b MD	18	static struct plat_sci_port scif0_platform_data = {
	19	.mapbase = 0xffe00000,
	20	.flags = UPF_BOOT_AUTOCONF,
	21	.type = PORT_SCIF,
	22	.irqs = { 40, 40, 40, 40 },
	23	};
	24
	25	static struct platform_device scif0_device = {
	26	.name = "sh-sci",
	27	.id = 0,
	28	.dev = {
	29	.platform_data = &scif0_platform_data,
	30	},
	31	};
	32
	33	static struct plat_sci_port scif1_platform_data = {
	34	.mapbase = 0xffe10000,
	35	.flags = UPF_BOOT_AUTOCONF,
	36	.type = PORT_SCIF,
	37	.irqs = { 76, 76, 76, 76 },
	38	};
	39
	40	static struct platform_device scif1_device = {
	41	.name = "sh-sci",
	42	.id = 1,
	43	.dev = {
	44	.platform_data = &scif1_platform_data,
	45	},
	46	};
	47
ccc19565 MD	48	static struct sh_timer_config tmu0_platform_data = {
	49	.name = "TMU0",
	50	.channel_offset = 0x04,
	51	.timer_bit = 0,
af777ce4	52	.clk = "peripheral_clk",
ccc19565 MD	53	.clockevent_rating = 200,
	54	};
	55
	56	static struct resource tmu0_resources[] = {
	57	[0] = {
	58	.name = "TMU0",
	59	.start = 0xffd80008,
	60	.end = 0xffd80013,
	61	.flags = IORESOURCE_MEM,
	62	},
	63	[1] = {
	64	.start = 28,
	65	.flags = IORESOURCE_IRQ,
	66	},
	67	};
	68
	69	static struct platform_device tmu0_device = {
	70	.name = "sh_tmu",
	71	.id = 0,
	72	.dev = {
	73	.platform_data = &tmu0_platform_data,
	74	},
	75	.resource = tmu0_resources,
	76	.num_resources = ARRAY_SIZE(tmu0_resources),
	77	};
	78
	79	static struct sh_timer_config tmu1_platform_data = {
	80	.name = "TMU1",
	81	.channel_offset = 0x10,
	82	.timer_bit = 1,
af777ce4	83	.clk = "peripheral_clk",
ccc19565 MD	84	.clocksource_rating = 200,
	85	};
	86
	87	static struct resource tmu1_resources[] = {
	88	[0] = {
	89	.name = "TMU1",
	90	.start = 0xffd80014,
	91	.end = 0xffd8001f,
	92	.flags = IORESOURCE_MEM,
	93	},
	94	[1] = {
	95	.start = 29,
	96	.flags = IORESOURCE_IRQ,
	97	},
	98	};
	99
	100	static struct platform_device tmu1_device = {
	101	.name = "sh_tmu",
	102	.id = 1,
	103	.dev = {
	104	.platform_data = &tmu1_platform_data,
	105	},
	106	.resource = tmu1_resources,
	107	.num_resources = ARRAY_SIZE(tmu1_resources),
	108	};
	109
	110	static struct sh_timer_config tmu2_platform_data = {
	111	.name = "TMU2",
	112	.channel_offset = 0x1c,
	113	.timer_bit = 2,
af777ce4	114	.clk = "peripheral_clk",
ccc19565 MD	115	};
	116
	117	static struct resource tmu2_resources[] = {
	118	[0] = {
	119	.name = "TMU2",
	120	.start = 0xffd80020,
	121	.end = 0xffd8002f,
	122	.flags = IORESOURCE_MEM,
	123	},
	124	[1] = {
	125	.start = 30,
	126	.flags = IORESOURCE_IRQ,
	127	},
	128	};
	129
	130	static struct platform_device tmu2_device = {
	131	.name = "sh_tmu",
	132	.id = 2,
	133	.dev = {
	134	.platform_data = &tmu2_platform_data,
	135	},
	136	.resource = tmu2_resources,
	137	.num_resources = ARRAY_SIZE(tmu2_resources),
	138	};
	139
	140	static struct sh_timer_config tmu3_platform_data = {
	141	.name = "TMU3",
	142	.channel_offset = 0x04,
	143	.timer_bit = 0,
af777ce4	144	.clk = "peripheral_clk",
ccc19565 MD	145	};
	146
	147	static struct resource tmu3_resources[] = {
	148	[0] = {
	149	.name = "TMU3",
	150	.start = 0xffdc0008,
	151	.end = 0xffdc0013,
	152	.flags = IORESOURCE_MEM,
	153	},
	154	[1] = {
	155	.start = 96,
	156	.flags = IORESOURCE_IRQ,
	157	},
	158	};
	159
	160	static struct platform_device tmu3_device = {
	161	.name = "sh_tmu",
	162	.id = 3,
	163	.dev = {
	164	.platform_data = &tmu3_platform_data,
	165	},
	166	.resource = tmu3_resources,
	167	.num_resources = ARRAY_SIZE(tmu3_resources),
	168	};
	169
	170	static struct sh_timer_config tmu4_platform_data = {
	171	.name = "TMU4",
	172	.channel_offset = 0x10,
	173	.timer_bit = 1,
af777ce4	174	.clk = "peripheral_clk",
ccc19565 MD	175	};
	176
	177	static struct resource tmu4_resources[] = {
	178	[0] = {
	179	.name = "TMU4",
	180	.start = 0xffdc0014,
	181	.end = 0xffdc001f,
	182	.flags = IORESOURCE_MEM,
	183	},
	184	[1] = {
	185	.start = 97,
	186	.flags = IORESOURCE_IRQ,
	187	},
	188	};
	189
	190	static struct platform_device tmu4_device = {
	191	.name = "sh_tmu",
	192	.id = 4,
	193	.dev = {
	194	.platform_data = &tmu4_platform_data,
	195	},
	196	.resource = tmu4_resources,
	197	.num_resources = ARRAY_SIZE(tmu4_resources),
	198	};
	199
	200	static struct sh_timer_config tmu5_platform_data = {
	201	.name = "TMU5",
	202	.channel_offset = 0x1c,
	203	.timer_bit = 2,
af777ce4	204	.clk = "peripheral_clk",
ccc19565 MD	205	};
	206
	207	static struct resource tmu5_resources[] = {
	208	[0] = {
	209	.name = "TMU5",
	210	.start = 0xffdc0020,
	211	.end = 0xffdc002b,
	212	.flags = IORESOURCE_MEM,
	213	},
	214	[1] = {
	215	.start = 98,
	216	.flags = IORESOURCE_IRQ,
	217	},
	218	};
	219
	220	static struct platform_device tmu5_device = {
	221	.name = "sh_tmu",
	222	.id = 5,
	223	.dev = {
	224	.platform_data = &tmu5_platform_data,
	225	},
	226	.resource = tmu5_resources,
	227	.num_resources = ARRAY_SIZE(tmu5_resources),
	228	};
959f85f8 PM	229
	230	static struct resource rtc_resources[] = {
	231	[0] = {
	232	.start = 0xffe80000,
	233	.end = 0xffe80000 + 0x58 - 1,
	234	.flags = IORESOURCE_IO,
	235	},
	236	[1] = {
a842fb2d	237	/* Shared Period/Carry/Alarm IRQ */
39c7aa9e	238	.start = 20,
959f85f8 PM	239	.flags = IORESOURCE_IRQ,
	240	},
	241	};
	242
	243	static struct platform_device rtc_device = {
	244	.name = "sh-rtc",
	245	.id = -1,
	246	.num_resources = ARRAY_SIZE(rtc_resources),
	247	.resource = rtc_resources,
	248	};
	249
027811b9 GL	250	/* DMA */
	251	static struct sh_dmae_channel sh7780_dmae0_channels[] = {
	252	{
	253	.offset = 0,
	254	.dmars = 0,
	255	.dmars_bit = 0,
	256	}, {
	257	.offset = 0x10,
	258	.dmars = 0,
	259	.dmars_bit = 8,
	260	}, {
	261	.offset = 0x20,
	262	.dmars = 4,
	263	.dmars_bit = 0,
	264	}, {
	265	.offset = 0x30,
	266	.dmars = 4,
	267	.dmars_bit = 8,
	268	}, {
	269	.offset = 0x50,
	270	.dmars = 8,
	271	.dmars_bit = 0,
	272	}, {
	273	.offset = 0x60,
	274	.dmars = 8,
	275	.dmars_bit = 8,
	276	}
ecb6fd52 NI	277	};
ecb6fd52 NI	278
027811b9 GL	279	static struct sh_dmae_channel sh7780_dmae1_channels[] = {
	280	{
	281	.offset = 0,
	282	}, {
	283	.offset = 0x10,
	284	}, {
	285	.offset = 0x20,
	286	}, {
	287	.offset = 0x30,
	288	}, {
	289	.offset = 0x50,
	290	}, {
	291	.offset = 0x60,
	292	}
	293	};
	294
	295	static struct sh_dmae_pdata dma0_platform_data = {
	296	.channel = sh7780_dmae0_channels,
	297	.channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
	298	};
	299
	300	static struct sh_dmae_pdata dma1_platform_data = {
	301	.channel = sh7780_dmae1_channels,
	302	.channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
	303	};
	304
	305	static struct resource sh7780_dmae0_resources[] = {
	306	[0] = {
	307	/* Channel registers and DMAOR */
	308	.start = 0xfc808020,
	309	.end = 0xfc80808f,
	310	.flags = IORESOURCE_MEM,
	311	},
	312	[1] = {
	313	/* DMARSx */
	314	.start = 0xfc809000,
	315	.end = 0xfc80900b,
	316	.flags = IORESOURCE_MEM,
	317	},
	318	{
	319	/* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
	320	.start = 34,
	321	.end = 34,
	322	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_SHAREABLE,
	323	},
	324	};
	325
	326	static struct resource sh7780_dmae1_resources[] = {
	327	[0] = {
	328	/* Channel registers and DMAOR */
	329	.start = 0xfc818020,
	330	.end = 0xfc81808f,
	331	.flags = IORESOURCE_MEM,
	332	},
	333	/* DMAC1 has no DMARS */
	334	{
	335	/* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
	336	.start = 46,
	337	.end = 46,
	338	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_SHAREABLE,
	339	},
	340	};
	341
	342	static struct platform_device dma0_device = {
ecb6fd52	343	.name = "sh-dma-engine",
027811b9 GL	344	.id = 0,
	345	.resource = sh7780_dmae0_resources,
	346	.num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
ecb6fd52	347	.dev = {
027811b9 GL	348	.platform_data = &dma0_platform_data,
	349	},
	350	};
	351
	352	static struct platform_device dma1_device = {
	353	.name = "sh-dma-engine",
	354	.id = 1,
	355	.resource = sh7780_dmae1_resources,
	356	.num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
	357	.dev = {
	358	.platform_data = &dma1_platform_data,
ecb6fd52 NI	359	},
	360	};
	361
959f85f8	362	static struct platform_device *sh7780_devices[] __initdata = {
a9571d7b MD	363	&scif0_device,
a9571d7b MD	364	&scif1_device,
ccc19565 MD	365	&tmu0_device,
	366	&tmu1_device,
	367	&tmu2_device,
	368	&tmu3_device,
	369	&tmu4_device,
	370	&tmu5_device,
959f85f8	371	&rtc_device,
027811b9 GL	372	&dma0_device,
027811b9 GL	373	&dma1_device,
959f85f8 PM	374	};
	375
	376	static int __init sh7780_devices_setup(void)
	377	{
	378	return platform_add_devices(sh7780_devices,
	379	ARRAY_SIZE(sh7780_devices));
	380	}
ba9a6337	381	arch_initcall(sh7780_devices_setup);
ccc19565	382	static struct platform_device *sh7780_early_devices[] __initdata = {
a9571d7b MD	383	&scif0_device,
a9571d7b MD	384	&scif1_device,
ccc19565 MD	385	&tmu0_device,
	386	&tmu1_device,
	387	&tmu2_device,
	388	&tmu3_device,
	389	&tmu4_device,
	390	&tmu5_device,
	391	};
	392
	393	void __init plat_early_device_setup(void)
	394	{
	395	early_platform_add_devices(sh7780_early_devices,
	396	ARRAY_SIZE(sh7780_early_devices));
	397	}
	398
39c7aa9e MD	399	enum {
39c7aa9e MD	400	UNUSED = 0,
66a74057	401
39c7aa9e	402	/* interrupt sources */
66a74057	403
39c7aa9e MD	404	IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
	405	IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
	406	IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
	407	IRL_HHLL, IRL_HHLH, IRL_HHHL,
9a7ef6d5	408
39c7aa9e	409	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
a842fb2d MD	410	RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
	411	HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
	412	PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
	413	SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
9a7ef6d5	414
39c7aa9e MD	415	/* interrupt groups */
39c7aa9e MD	416
a842fb2d	417	TMU012, TMU345,
66a74057 PM	418	};
66a74057 PM	419
5c37e025	420	static struct intc_vect vectors[] __initdata = {
a842fb2d MD	421	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
a842fb2d MD	422	INTC_VECT(RTC, 0x4c0),
39c7aa9e MD	423	INTC_VECT(WDT, 0x560),
	424	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
	425	INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
	426	INTC_VECT(HUDI, 0x600),
a842fb2d MD	427	INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
	428	INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
	429	INTC_VECT(DMAC0, 0x6c0),
	430	INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
	431	INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
	432	INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
	433	INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
39c7aa9e MD	434	INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
	435	INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
	436	INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
a842fb2d MD	437	INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
	438	INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
	439	INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
	440	INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
	441	INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
39c7aa9e	442	INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
a842fb2d MD	443	INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
	444	INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
	445	INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
	446	INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
39c7aa9e MD	447	INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
	448	INTC_VECT(TMU5, 0xe40),
	449	INTC_VECT(SSI, 0xe80),
a842fb2d MD	450	INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
	451	INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
	452	INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
	453	INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
39c7aa9e	454	};
d619500a	455
5c37e025	456	static struct intc_group groups[] __initdata = {
39c7aa9e	457	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
39c7aa9e	458	INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
39c7aa9e	459	};
d619500a	460
5c37e025	461	static struct intc_mask_reg mask_registers[] __initdata = {
39c7aa9e MD	462	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
	463	{ 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
	464	SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
	465	PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
	466	HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
	467	};
	468
5c37e025	469	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	470	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
	471	TMU2, TMU2_TICPI } },
	472	{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
	473	{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
	474	{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
	475	{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
	476	PCISERR, PCIINTA, } },
	477	{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
	478	PCIINTD, PCIC5 } },
	479	{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
	480	{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
39c7aa9e MD	481	};
39c7aa9e MD	482
7f3edee8	483	static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
39c7aa9e MD	484	mask_registers, prio_registers, NULL);
	485
	486	/* Support for external interrupt pins in IRQ mode */
	487
5c37e025	488	static struct intc_vect irq_vectors[] __initdata = {
39c7aa9e MD	489	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
	490	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
	491	INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
	492	INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
	493	};
	494
5c37e025	495	static struct intc_mask_reg irq_mask_registers[] __initdata = {
39c7aa9e MD	496	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
	497	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	498	};
	499
5c37e025	500	static struct intc_prio_reg irq_prio_registers[] __initdata = {
6ef5fb2c MD	501	{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
6ef5fb2c MD	502	IRQ4, IRQ5, IRQ6, IRQ7 } },
d619500a MD	503	};
d619500a MD	504
5c37e025	505	static struct intc_sense_reg irq_sense_registers[] __initdata = {
39c7aa9e MD	506	{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
	507	IRQ4, IRQ5, IRQ6, IRQ7 } },
	508	};
	509
6bdfb22a YS	510	static struct intc_mask_reg irq_ack_registers[] __initdata = {
	511	{ 0xffd00024, 0, 32, /* INTREQ */
	512	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	513	};
	514
	515	static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
	516	NULL, irq_mask_registers, irq_prio_registers,
	517	irq_sense_registers, irq_ack_registers);
39c7aa9e MD	518
	519	/* External interrupt pins in IRL mode */
	520
5c37e025	521	static struct intc_vect irl_vectors[] __initdata = {
39c7aa9e MD	522	INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
	523	INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
	524	INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
	525	INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
	526	INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
	527	INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
	528	INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
	529	INTC_VECT(IRL_HHHL, 0x3c0),
	530	};
	531
5c37e025	532	static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
953c8ef2	533	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
39c7aa9e MD	534	{ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
	535	IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
	536	IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
	537	IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
	538	};
	539
5c37e025	540	static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
953c8ef2	541	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
39c7aa9e MD	542	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	543	IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
	544	IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
	545	IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
	546	IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
	547	};
	548
	549	static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
7f3edee8	550	NULL, irl7654_mask_registers, NULL, NULL);
39c7aa9e MD	551
39c7aa9e MD	552	static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
7f3edee8	553	NULL, irl3210_mask_registers, NULL, NULL);
39c7aa9e	554
953c8ef2 MD	555	#define INTC_ICR0 0xffd00000
	556	#define INTC_INTMSK0 0xffd00044
	557	#define INTC_INTMSK1 0xffd00048
	558	#define INTC_INTMSK2 0xffd40080
	559	#define INTC_INTMSKCLR1 0xffd00068
	560	#define INTC_INTMSKCLR2 0xffd40084
	561
90015c89	562	void __init plat_irq_setup(void)
66a74057	563	{
953c8ef2	564	/* disable IRQ7-0 */
9d56dd3b	565	__raw_writel(0xff000000, INTC_INTMSK0);
953c8ef2 MD	566
953c8ef2 MD	567	/* disable IRL3-0 + IRL7-4 */
9d56dd3b PM	568	__raw_writel(0xc0000000, INTC_INTMSK1);
9d56dd3b PM	569	__raw_writel(0xfffefffe, INTC_INTMSK2);
953c8ef2 MD	570
953c8ef2 MD	571	/* select IRL mode for IRL3-0 + IRL7-4 */
9d56dd3b	572	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
953c8ef2 MD	573
953c8ef2 MD	574	/* disable holding function, ie enable "SH-4 Mode" */
9d56dd3b	575	__raw_writel(__raw_readl(INTC_ICR0) \| 0x00200000, INTC_ICR0);
953c8ef2	576
39c7aa9e MD	577	register_intc_controller(&intc_desc);
	578	}
	579
	580	void __init plat_irq_setup_pins(int mode)
	581	{
	582	switch (mode) {
	583	case IRQ_MODE_IRQ:
953c8ef2	584	/* select IRQ mode for IRL3-0 + IRL7-4 */
9d56dd3b	585	__raw_writel(__raw_readl(INTC_ICR0) \| 0x00c00000, INTC_ICR0);
39c7aa9e MD	586	register_intc_controller(&intc_irq_desc);
	587	break;
	588	case IRQ_MODE_IRL7654:
953c8ef2	589	/* enable IRL7-4 but don't provide any masking */
9d56dd3b PM	590	__raw_writel(0x40000000, INTC_INTMSKCLR1);
9d56dd3b PM	591	__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
39c7aa9e MD	592	break;
39c7aa9e MD	593	case IRQ_MODE_IRL3210:
953c8ef2	594	/* enable IRL0-3 but don't provide any masking */
9d56dd3b PM	595	__raw_writel(0x80000000, INTC_INTMSKCLR1);
9d56dd3b PM	596	__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
953c8ef2 MD	597	break;
	598	case IRQ_MODE_IRL7654_MASK:
	599	/* enable IRL7-4 and mask using cpu intc controller */
9d56dd3b	600	__raw_writel(0x40000000, INTC_INTMSKCLR1);
953c8ef2 MD	601	register_intc_controller(&intc_irl7654_desc);
	602	break;
	603	case IRQ_MODE_IRL3210_MASK:
	604	/* enable IRL0-3 and mask using cpu intc controller */
9d56dd3b	605	__raw_writel(0x80000000, INTC_INTMSKCLR1);
39c7aa9e MD	606	register_intc_controller(&intc_irl3210_desc);
	607	break;
	608	default:
	609	BUG();
	610	}
66a74057	611	}