[deliverable/linux.git] / arch / sh / kernel / gpio.c

/*
 * Pinmuxed GPIO support for SuperH.
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/gpio.h>

static struct pinmux_info *registered_gpio;

static struct pinmux_info *gpio_controller(unsigned gpio)
{
	if (!registered_gpio)
		return NULL;

	if (gpio < registered_gpio->first_gpio)
		return NULL;

	if (gpio > registered_gpio->last_gpio)
		return NULL;

	return registered_gpio;
}

static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
			 unsigned long field_width, unsigned long in_pos)
{
	unsigned long data, mask, pos;

	data = 0;
	mask = (1 << field_width) - 1;
	pos = reg_width - ((in_pos + 1) * field_width);

#ifdef DEBUG
	pr_info("read_reg: addr = %lx, pos = %ld, "
		"r_width = %ld, f_width = %ld\n",
		reg, pos, reg_width, field_width);
#endif

	switch (reg_width) {
	case 8:
		data = ctrl_inb(reg);
		break;
	case 16:
		data = ctrl_inw(reg);
		break;
	case 32:
		data = ctrl_inl(reg);
		break;
	}

	return (data >> pos) & mask;
}

static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
			   unsigned long field_width, unsigned long in_pos,
			   unsigned long value)
{
	unsigned long mask, pos;

	mask = (1 << field_width) - 1;
	pos = reg_width - ((in_pos + 1) * field_width);

#ifdef DEBUG
	pr_info("write_reg addr = %lx, value = %ld, pos = %ld, "
		"r_width = %ld, f_width = %ld\n",
		reg, value, pos, reg_width, field_width);
#endif

	mask = ~(mask << pos);
	value = value << pos;

	switch (reg_width) {
	case 8:
		ctrl_outb((ctrl_inb(reg) & mask) | value, reg);
		break;
	case 16:
		ctrl_outw((ctrl_inw(reg) & mask) | value, reg);
		break;
	case 32:
		ctrl_outl((ctrl_inl(reg) & mask) | value, reg);
		break;
	}
}

static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
{
	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	struct pinmux_data_reg *data_reg;
	int k, n;

	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
		return -1;

	k = 0;
	while (1) {
		data_reg = gpioc->data_regs + k;

		if (!data_reg->reg_width)
			break;

		for (n = 0; n < data_reg->reg_width; n++) {
			if (data_reg->enum_ids[n] == gpiop->enum_id) {
				gpiop->flags &= ~PINMUX_FLAG_DREG;
				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
				gpiop->flags &= ~PINMUX_FLAG_DBIT;
				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
				return 0;
			}
		}
		k++;
	}

	BUG();

	return -1;
}

static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
			struct pinmux_data_reg **drp, int *bitp)
{
	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	int k, n;

	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
		return -1;

	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
	*drp = gpioc->data_regs + k;
	*bitp = n;
	return 0;
}

static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
			  struct pinmux_cfg_reg **crp, int *indexp,
			  unsigned long **cntp)
{
	struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width;
	int k, n;

	k = 0;
	while (1) {
		config_reg = gpioc->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;
		for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
			if (config_reg->enum_ids[n] == enum_id) {
				*crp = config_reg;
				*indexp = n;
				*cntp = &config_reg->cnt[n / (1 << f_width)];
				return 0;
			}
		}
		k++;
	}

	return -1;
}

static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
			    int pos, pinmux_enum_t *enum_idp)
{
	pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
	pinmux_enum_t *data = gpioc->gpio_data;
	int k;

	if (!enum_in_range(enum_id, &gpioc->data)) {
		if (!enum_in_range(enum_id, &gpioc->mark)) {
			pr_err("non data/mark enum_id for gpio %d\n", gpio);
			return -1;
		}
	}

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < gpioc->gpio_data_size; k++) {
		if (data[k] == enum_id) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
	return -1;
}

static void write_config_reg(struct pinmux_info *gpioc,
			     struct pinmux_cfg_reg *crp,
			     int index)
{
	unsigned long ncomb, pos, value;

	ncomb = 1 << crp->field_width;
	pos = index / ncomb;
	value = index % ncomb;

	gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
}

static int check_config_reg(struct pinmux_info *gpioc,
			    struct pinmux_cfg_reg *crp,
			    int index)
{
	unsigned long ncomb, pos, value;

	ncomb = 1 << crp->field_width;
	pos = index / ncomb;
	value = index % ncomb;

	if (gpio_read_reg(crp->reg, crp->reg_width,
			  crp->field_width, pos) == value)
		return 0;

	return -1;
}

enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };

static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
			      int pinmux_type, int cfg_mode)
{
	struct pinmux_cfg_reg *cr = NULL;
	pinmux_enum_t enum_id;
	struct pinmux_range *range;
	int in_range, pos, index;
	unsigned long *cntp;

	switch (pinmux_type) {

	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &gpioc->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &gpioc->input;
		break;

	case PINMUX_TYPE_INPUT_PULLUP:
		range = &gpioc->input_pu;
		break;

	case PINMUX_TYPE_INPUT_PULLDOWN:
		range = &gpioc->input_pd;
		break;

	default:
		goto out_err;
	}

	pos = 0;
	enum_id = 0;
	index = 0;
	while (1) {
		pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
		if (pos <= 0)
			goto out_err;

		if (!enum_id)
			break;

		in_range = enum_in_range(enum_id, &gpioc->function);
		if (!in_range && range) {
			in_range = enum_in_range(enum_id, range);

			if (in_range && enum_id == range->force)
				continue;
		}

		if (!in_range)
			continue;

		if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
			goto out_err;

		switch (cfg_mode) {
		case GPIO_CFG_DRYRUN:
			if (!*cntp || !check_config_reg(gpioc, cr, index))
				continue;
			break;

		case GPIO_CFG_REQ:
			write_config_reg(gpioc, cr, index);
			*cntp = *cntp + 1;
			break;

		case GPIO_CFG_FREE:
			*cntp = *cntp - 1;
			break;
		}
	}

	return 0;
 out_err:
	return -1;
}

static DEFINE_SPINLOCK(gpio_lock);

int __gpio_request(unsigned gpio)
{
	struct pinmux_info *gpioc = gpio_controller(gpio);
	struct pinmux_data_reg *dummy;
	unsigned long flags;
	int i, ret, pinmux_type;

	ret = -EINVAL;

	if (!gpioc)
		goto err_out;

	spin_lock_irqsave(&gpio_lock, flags);

	if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
		goto err_unlock;

	/* setup pin function here if no data is associated with pin */

	if (get_data_reg(gpioc, gpio, &dummy, &i) != 0)
		pinmux_type = PINMUX_TYPE_FUNCTION;
	else
		pinmux_type = PINMUX_TYPE_GPIO;

	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
		if (pinmux_config_gpio(gpioc, gpio,
				       pinmux_type,
				       GPIO_CFG_DRYRUN) != 0)
			goto err_unlock;

		if (pinmux_config_gpio(gpioc, gpio,
				       pinmux_type,
				       GPIO_CFG_REQ) != 0)
			BUG();
	}

	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[gpio].flags |= pinmux_type;

	ret = 0;
 err_unlock:
	spin_unlock_irqrestore(&gpio_lock, flags);
 err_out:
	return ret;
}
EXPORT_SYMBOL(__gpio_request);

void gpio_free(unsigned gpio)
{
	struct pinmux_info *gpioc = gpio_controller(gpio);
	unsigned long flags;
	int pinmux_type;

	if (!gpioc)
		return;

	spin_lock_irqsave(&gpio_lock, flags);

	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
	pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[gpio].flags |= PINMUX_TYPE_NONE;

	spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(gpio_free);

static int pinmux_direction(struct pinmux_info *gpioc,
			    unsigned gpio, int new_pinmux_type)
{
	int pinmux_type;
	int ret = -EINVAL;

	if (!gpioc)
		goto err_out;

	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
		break;
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
		break;
	default:
		goto err_out;
	}

	if (pinmux_config_gpio(gpioc, gpio,
			       new_pinmux_type,
			       GPIO_CFG_DRYRUN) != 0)
		goto err_out;

	if (pinmux_config_gpio(gpioc, gpio,
			       new_pinmux_type,
			       GPIO_CFG_REQ) != 0)
		BUG();

	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[gpio].flags |= new_pinmux_type;

	ret = 0;
 err_out:
	return ret;
}

int gpio_direction_input(unsigned gpio)
{
	struct pinmux_info *gpioc = gpio_controller(gpio);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&gpio_lock, flags);
	ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT);
	spin_unlock_irqrestore(&gpio_lock, flags);

	return ret;
}
EXPORT_SYMBOL(gpio_direction_input);

static void __gpio_set_value(struct pinmux_info *gpioc,
			     unsigned gpio, int value)
{
	struct pinmux_data_reg *dr = NULL;
	int bit = 0;

	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
		BUG();
	else
		gpio_write_reg(dr->reg, dr->reg_width, 1, bit, !!value);
}

int gpio_direction_output(unsigned gpio, int value)
{
	struct pinmux_info *gpioc = gpio_controller(gpio);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&gpio_lock, flags);
	__gpio_set_value(gpioc, gpio, value);
	ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
	spin_unlock_irqrestore(&gpio_lock, flags);

	return ret;
}
EXPORT_SYMBOL(gpio_direction_output);

static int __gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
{
	struct pinmux_data_reg *dr = NULL;
	int bit = 0;

	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
		BUG();
		return 0;
	}

	return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
}

int gpio_get_value(unsigned gpio)
{
	return __gpio_get_value(gpio_controller(gpio), gpio);
}
EXPORT_SYMBOL(gpio_get_value);

void gpio_set_value(unsigned gpio, int value)
{
	struct pinmux_info *gpioc = gpio_controller(gpio);
	unsigned long flags;

	spin_lock_irqsave(&gpio_lock, flags);
	__gpio_set_value(gpioc, gpio, value);
	spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(gpio_set_value);

int register_pinmux(struct pinmux_info *pip)
{
	int k;

	registered_gpio = pip;
	pr_info("pinmux: %s handling gpio %d -> %d\n",
		pip->name, pip->first_gpio, pip->last_gpio);

	for (k = pip->first_gpio; k <= pip->last_gpio; k++)
		setup_data_reg(pip, k);

	return 0;
}
Commit	Line	Data
2967dab1 MD	1	/*
	2	* Pinmuxed GPIO support for SuperH.
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/errno.h>
	12	#include <linux/kernel.h>
	13	#include <linux/list.h>
	14	#include <linux/module.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/irq.h>
	19	#include <linux/bitops.h>
	20	#include <linux/gpio.h>
	21
	22	static struct pinmux_info *registered_gpio;
	23
	24	static struct pinmux_info *gpio_controller(unsigned gpio)
	25	{
	26	if (!registered_gpio)
	27	return NULL;
	28
	29	if (gpio < registered_gpio->first_gpio)
	30	return NULL;
	31
	32	if (gpio > registered_gpio->last_gpio)
	33	return NULL;
	34
	35	return registered_gpio;
	36	}
	37
	38	static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
	39	{
	40	if (enum_id < r->begin)
	41	return 0;
	42
	43	if (enum_id > r->end)
	44	return 0;
	45
	46	return 1;
	47	}
	48
0fc64cc0 MD	49	static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
0fc64cc0 MD	50	unsigned long field_width, unsigned long in_pos)
2967dab1 MD	51	{
	52	unsigned long data, mask, pos;
	53
	54	data = 0;
	55	mask = (1 << field_width) - 1;
	56	pos = reg_width - ((in_pos + 1) * field_width);
	57
	58	#ifdef DEBUG
0fc64cc0	59	pr_info("read_reg: addr = %lx, pos = %ld, "
2967dab1	60	"r_width = %ld, f_width = %ld\n",
0fc64cc0	61	reg, pos, reg_width, field_width);
2967dab1 MD	62	#endif
	63
	64	switch (reg_width) {
	65	case 8:
	66	data = ctrl_inb(reg);
	67	break;
	68	case 16:
	69	data = ctrl_inw(reg);
	70	break;
	71	case 32:
	72	data = ctrl_inl(reg);
	73	break;
	74	}
	75
0fc64cc0 MD	76	return (data >> pos) & mask;
	77	}
	78
	79	static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
	80	unsigned long field_width, unsigned long in_pos,
	81	unsigned long value)
	82	{
	83	unsigned long mask, pos;
	84
	85	mask = (1 << field_width) - 1;
	86	pos = reg_width - ((in_pos + 1) * field_width);
2967dab1	87
0fc64cc0 MD	88	#ifdef DEBUG
	89	pr_info("write_reg addr = %lx, value = %ld, pos = %ld, "
	90	"r_width = %ld, f_width = %ld\n",
	91	reg, value, pos, reg_width, field_width);
	92	#endif
	93
	94	mask = ~(mask << pos);
	95	value = value << pos;
2967dab1 MD	96
	97	switch (reg_width) {
	98	case 8:
0fc64cc0	99	ctrl_outb((ctrl_inb(reg) & mask) \| value, reg);
2967dab1 MD	100	break;
2967dab1 MD	101	case 16:
0fc64cc0	102	ctrl_outw((ctrl_inw(reg) & mask) \| value, reg);
2967dab1 MD	103	break;
2967dab1 MD	104	case 32:
0fc64cc0	105	ctrl_outl((ctrl_inl(reg) & mask) \| value, reg);
2967dab1 MD	106	break;
2967dab1 MD	107	}
2967dab1 MD	108	}
2967dab1 MD	109
18801be7	110	static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
2967dab1	111	{
18801be7	112	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
2967dab1 MD	113	struct pinmux_data_reg *data_reg;
	114	int k, n;
	115
18801be7	116	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
2967dab1 MD	117	return -1;
	118
	119	k = 0;
	120	while (1) {
	121	data_reg = gpioc->data_regs + k;
	122
	123	if (!data_reg->reg_width)
	124	break;
	125
	126	for (n = 0; n < data_reg->reg_width; n++) {
18801be7 MD	127	if (data_reg->enum_ids[n] == gpiop->enum_id) {
	128	gpiop->flags &= ~PINMUX_FLAG_DREG;
	129	gpiop->flags \|= (k << PINMUX_FLAG_DREG_SHIFT);
	130	gpiop->flags &= ~PINMUX_FLAG_DBIT;
	131	gpiop->flags \|= (n << PINMUX_FLAG_DBIT_SHIFT);
2967dab1	132	return 0;
2967dab1 MD	133	}
	134	}
	135	k++;
	136	}
	137
18801be7 MD	138	BUG();
18801be7 MD	139
2967dab1 MD	140	return -1;
	141	}
	142
18801be7 MD	143	static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
	144	struct pinmux_data_reg *drp, int bitp)
	145	{
	146	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	147	int k, n;
	148
	149	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
	150	return -1;
	151
	152	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	153	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
	154	*drp = gpioc->data_regs + k;
	155	*bitp = n;
	156	return 0;
	157	}
	158
2967dab1 MD	159	static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
	160	struct pinmux_cfg_reg *crp, int indexp,
	161	unsigned long **cntp)
	162	{
	163	struct pinmux_cfg_reg *config_reg;
	164	unsigned long r_width, f_width;
	165	int k, n;
	166
	167	k = 0;
	168	while (1) {
	169	config_reg = gpioc->cfg_regs + k;
	170
	171	r_width = config_reg->reg_width;
	172	f_width = config_reg->field_width;
	173
	174	if (!r_width)
	175	break;
	176	for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
	177	if (config_reg->enum_ids[n] == enum_id) {
	178	*crp = config_reg;
	179	*indexp = n;
	180	*cntp = &config_reg->cnt[n / (1 << f_width)];
	181	return 0;
	182	}
	183	}
	184	k++;
	185	}
	186
	187	return -1;
	188	}
	189
	190	static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
	191	int pos, pinmux_enum_t *enum_idp)
	192	{
	193	pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
	194	pinmux_enum_t *data = gpioc->gpio_data;
	195	int k;
	196
	197	if (!enum_in_range(enum_id, &gpioc->data)) {
	198	if (!enum_in_range(enum_id, &gpioc->mark)) {
	199	pr_err("non data/mark enum_id for gpio %d\n", gpio);
	200	return -1;
	201	}
	202	}
	203
	204	if (pos) {
	205	*enum_idp = data[pos + 1];
	206	return pos + 1;
	207	}
	208
	209	for (k = 0; k < gpioc->gpio_data_size; k++) {
	210	if (data[k] == enum_id) {
	211	*enum_idp = data[k + 1];
	212	return k + 1;
	213	}
	214	}
	215
	216	pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
	217	return -1;
	218	}
	219
0fc64cc0 MD	220	static void write_config_reg(struct pinmux_info *gpioc,
	221	struct pinmux_cfg_reg *crp,
	222	int index)
2967dab1 MD	223	{
	224	unsigned long ncomb, pos, value;
	225
	226	ncomb = 1 << crp->field_width;
	227	pos = index / ncomb;
	228	value = index % ncomb;
	229
0fc64cc0	230	gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
2967dab1 MD	231	}
	232
	233	static int check_config_reg(struct pinmux_info *gpioc,
	234	struct pinmux_cfg_reg *crp,
	235	int index)
	236	{
	237	unsigned long ncomb, pos, value;
	238
	239	ncomb = 1 << crp->field_width;
	240	pos = index / ncomb;
	241	value = index % ncomb;
	242
0fc64cc0 MD	243	if (gpio_read_reg(crp->reg, crp->reg_width,
0fc64cc0 MD	244	crp->field_width, pos) == value)
2967dab1 MD	245	return 0;
	246
	247	return -1;
	248	}
	249
	250	enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
	251
0fc64cc0 MD	252	static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
0fc64cc0 MD	253	int pinmux_type, int cfg_mode)
2967dab1 MD	254	{
	255	struct pinmux_cfg_reg *cr = NULL;
	256	pinmux_enum_t enum_id;
	257	struct pinmux_range *range;
	258	int in_range, pos, index;
	259	unsigned long *cntp;
	260
	261	switch (pinmux_type) {
	262
	263	case PINMUX_TYPE_FUNCTION:
	264	range = NULL;
	265	break;
	266
	267	case PINMUX_TYPE_OUTPUT:
	268	range = &gpioc->output;
	269	break;
	270
	271	case PINMUX_TYPE_INPUT:
	272	range = &gpioc->input;
	273	break;
	274
	275	case PINMUX_TYPE_INPUT_PULLUP:
	276	range = &gpioc->input_pu;
	277	break;
	278
	279	case PINMUX_TYPE_INPUT_PULLDOWN:
	280	range = &gpioc->input_pd;
	281	break;
	282
	283	default:
	284	goto out_err;
	285	}
	286
	287	pos = 0;
	288	enum_id = 0;
	289	index = 0;
	290	while (1) {
	291	pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
	292	if (pos <= 0)
	293	goto out_err;
	294
	295	if (!enum_id)
	296	break;
	297
	298	in_range = enum_in_range(enum_id, &gpioc->function);
42eed42b	299	if (!in_range && range) {
2967dab1 MD	300	in_range = enum_in_range(enum_id, range);
2967dab1 MD	301
42eed42b MD	302	if (in_range && enum_id == range->force)
	303	continue;
	304	}
	305
2967dab1 MD	306	if (!in_range)
	307	continue;
	308
	309	if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
	310	goto out_err;
	311
	312	switch (cfg_mode) {
	313	case GPIO_CFG_DRYRUN:
	314	if (!*cntp \|\| !check_config_reg(gpioc, cr, index))
	315	continue;
	316	break;
	317
	318	case GPIO_CFG_REQ:
0fc64cc0	319	write_config_reg(gpioc, cr, index);
2967dab1 MD	320	cntp = cntp + 1;
	321	break;
	322
	323	case GPIO_CFG_FREE:
	324	cntp = cntp - 1;
	325	break;
	326	}
	327	}
	328
	329	return 0;
	330	out_err:
	331	return -1;
	332	}
	333
	334	static DEFINE_SPINLOCK(gpio_lock);
	335
	336	int __gpio_request(unsigned gpio)
	337	{
	338	struct pinmux_info *gpioc = gpio_controller(gpio);
	339	struct pinmux_data_reg *dummy;
	340	unsigned long flags;
	341	int i, ret, pinmux_type;
	342
	343	ret = -EINVAL;
	344
	345	if (!gpioc)
	346	goto err_out;
	347
	348	spin_lock_irqsave(&gpio_lock, flags);
	349
	350	if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
	351	goto err_unlock;
	352
	353	/* setup pin function here if no data is associated with pin */
	354
	355	if (get_data_reg(gpioc, gpio, &dummy, &i) != 0)
	356	pinmux_type = PINMUX_TYPE_FUNCTION;
	357	else
	358	pinmux_type = PINMUX_TYPE_GPIO;
	359
	360	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
	361	if (pinmux_config_gpio(gpioc, gpio,
	362	pinmux_type,
	363	GPIO_CFG_DRYRUN) != 0)
	364	goto err_unlock;
	365
	366	if (pinmux_config_gpio(gpioc, gpio,
	367	pinmux_type,
	368	GPIO_CFG_REQ) != 0)
	369	BUG();
	370	}
	371
18801be7 MD	372	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
18801be7 MD	373	gpioc->gpios[gpio].flags \|= pinmux_type;
2967dab1 MD	374
	375	ret = 0;
	376	err_unlock:
	377	spin_unlock_irqrestore(&gpio_lock, flags);
	378	err_out:
	379	return ret;
	380	}
	381	EXPORT_SYMBOL(__gpio_request);
	382
	383	void gpio_free(unsigned gpio)
	384	{
	385	struct pinmux_info *gpioc = gpio_controller(gpio);
	386	unsigned long flags;
	387	int pinmux_type;
	388
	389	if (!gpioc)
	390	return;
	391
	392	spin_lock_irqsave(&gpio_lock, flags);
	393
	394	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
	395	pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
18801be7 MD	396	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
18801be7 MD	397	gpioc->gpios[gpio].flags \|= PINMUX_TYPE_NONE;
2967dab1 MD	398
	399	spin_unlock_irqrestore(&gpio_lock, flags);
	400	}
	401	EXPORT_SYMBOL(gpio_free);
	402
	403	static int pinmux_direction(struct pinmux_info *gpioc,
	404	unsigned gpio, int new_pinmux_type)
	405	{
0fc64cc0 MD	406	int pinmux_type;
	407	int ret = -EINVAL;
	408
	409	if (!gpioc)
	410	goto err_out;
2967dab1	411
2967dab1 MD	412	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
	413
	414	switch (pinmux_type) {
	415	case PINMUX_TYPE_GPIO:
	416	break;
	417	case PINMUX_TYPE_OUTPUT:
	418	case PINMUX_TYPE_INPUT:
	419	case PINMUX_TYPE_INPUT_PULLUP:
	420	case PINMUX_TYPE_INPUT_PULLDOWN:
	421	pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
	422	break;
	423	default:
	424	goto err_out;
	425	}
	426
	427	if (pinmux_config_gpio(gpioc, gpio,
	428	new_pinmux_type,
	429	GPIO_CFG_DRYRUN) != 0)
	430	goto err_out;
	431
	432	if (pinmux_config_gpio(gpioc, gpio,
	433	new_pinmux_type,
	434	GPIO_CFG_REQ) != 0)
	435	BUG();
	436
18801be7 MD	437	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
18801be7 MD	438	gpioc->gpios[gpio].flags \|= new_pinmux_type;
2967dab1 MD	439
	440	ret = 0;
	441	err_out:
	442	return ret;
	443	}
	444
	445	int gpio_direction_input(unsigned gpio)
	446	{
	447	struct pinmux_info *gpioc = gpio_controller(gpio);
	448	unsigned long flags;
0fc64cc0	449	int ret;
2967dab1 MD	450
	451	spin_lock_irqsave(&gpio_lock, flags);
	452	ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT);
	453	spin_unlock_irqrestore(&gpio_lock, flags);
0fc64cc0	454
2967dab1 MD	455	return ret;
	456	}
	457	EXPORT_SYMBOL(gpio_direction_input);
	458
0fc64cc0 MD	459	static void __gpio_set_value(struct pinmux_info *gpioc,
0fc64cc0 MD	460	unsigned gpio, int value)
2967dab1 MD	461	{
	462	struct pinmux_data_reg *dr = NULL;
	463	int bit = 0;
	464
0fc64cc0	465	if (!gpioc \|\| get_data_reg(gpioc, gpio, &dr, &bit) != 0)
2967dab1 MD	466	BUG();
2967dab1 MD	467	else
0fc64cc0	468	gpio_write_reg(dr->reg, dr->reg_width, 1, bit, !!value);
2967dab1 MD	469	}
	470
	471	int gpio_direction_output(unsigned gpio, int value)
	472	{
	473	struct pinmux_info *gpioc = gpio_controller(gpio);
	474	unsigned long flags;
0fc64cc0	475	int ret;
2967dab1 MD	476
2967dab1 MD	477	spin_lock_irqsave(&gpio_lock, flags);
0fc64cc0	478	__gpio_set_value(gpioc, gpio, value);
2967dab1 MD	479	ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
2967dab1 MD	480	spin_unlock_irqrestore(&gpio_lock, flags);
0fc64cc0	481
2967dab1 MD	482	return ret;
	483	}
	484	EXPORT_SYMBOL(gpio_direction_output);
	485
0fc64cc0	486	static int __gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
2967dab1	487	{
0fc64cc0 MD	488	struct pinmux_data_reg *dr = NULL;
0fc64cc0 MD	489	int bit = 0;
2967dab1	490
0fc64cc0	491	if (!gpioc \|\| get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
2967dab1	492	BUG();
0fc64cc0	493	return 0;
2967dab1 MD	494	}
2967dab1 MD	495
0fc64cc0 MD	496	return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
	497	}
	498
	499	int gpio_get_value(unsigned gpio)
	500	{
	501	return __gpio_get_value(gpio_controller(gpio), gpio);
2967dab1 MD	502	}
	503	EXPORT_SYMBOL(gpio_get_value);
	504
	505	void gpio_set_value(unsigned gpio, int value)
	506	{
	507	struct pinmux_info *gpioc = gpio_controller(gpio);
	508	unsigned long flags;
	509
0fc64cc0 MD	510	spin_lock_irqsave(&gpio_lock, flags);
	511	__gpio_set_value(gpioc, gpio, value);
	512	spin_unlock_irqrestore(&gpio_lock, flags);
2967dab1 MD	513	}
	514	EXPORT_SYMBOL(gpio_set_value);
	515
	516	int register_pinmux(struct pinmux_info *pip)
	517	{
18801be7 MD	518	int k;
18801be7 MD	519
2967dab1 MD	520	registered_gpio = pip;
	521	pr_info("pinmux: %s handling gpio %d -> %d\n",
	522	pip->name, pip->first_gpio, pip->last_gpio);
	523
18801be7 MD	524	for (k = pip->first_gpio; k <= pip->last_gpio; k++)
	525	setup_data_reg(pip, k);
	526
2967dab1 MD	527	return 0;
2967dab1 MD	528	}