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1da177e4 LT |
1 | /* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $ |
2 | * | |
3 | * arch/sh/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | * | |
11 | * Head.S contains the SH exception handlers and startup code. | |
12 | */ | |
13 | #include <linux/linkage.h> | |
14 | ||
b7e108ee PM |
15 | #ifdef CONFIG_CPU_SH4A |
16 | #define SYNCO() synco | |
17 | ||
18 | #define PREFI(label, reg) \ | |
19 | mov.l label, reg; \ | |
20 | prefi @reg | |
21 | #else | |
22 | #define SYNCO() | |
23 | #define PREFI(label, reg) | |
24 | #endif | |
25 | ||
1da177e4 LT |
26 | .section .empty_zero_page, "aw" |
27 | ENTRY(empty_zero_page) | |
28 | .long 1 /* MOUNT_ROOT_RDONLY */ | |
29 | .long 0 /* RAMDISK_FLAGS */ | |
30 | .long 0x0200 /* ORIG_ROOT_DEV */ | |
31 | .long 1 /* LOADER_TYPE */ | |
32 | .long 0x00360000 /* INITRD_START */ | |
33 | .long 0x000a0000 /* INITRD_SIZE */ | |
34 | .long 0 | |
35 | .balign 4096,0,4096 | |
36 | ||
37 | .text | |
38 | /* | |
39 | * Condition at the entry of _stext: | |
40 | * | |
41 | * BSC has already been initialized. | |
42 | * INTC may or may not be initialized. | |
43 | * VBR may or may not be initialized. | |
44 | * MMU may or may not be initialized. | |
45 | * Cache may or may not be initialized. | |
46 | * Hardware (including on-chip modules) may or may not be initialized. | |
47 | * | |
48 | */ | |
49 | ENTRY(_stext) | |
50 | ! Initialize Status Register | |
51 | mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF | |
52 | ldc r0, sr | |
53 | ! Initialize global interrupt mask | |
54 | mov #0, r0 | |
55 | ldc r0, r6_bank | |
b7e108ee PM |
56 | |
57 | /* | |
58 | * Prefetch if possible to reduce cache miss penalty. | |
59 | * | |
60 | * We do this early on for SH-4A as a micro-optimization, | |
61 | * as later on we will have speculative execution enabled | |
62 | * and this will become less of an issue. | |
63 | */ | |
64 | PREFI(5f, r0) | |
65 | PREFI(6f, r0) | |
66 | ||
1da177e4 LT |
67 | ! |
68 | mov.l 2f, r0 | |
69 | mov r0, r15 ! Set initial r15 (stack pointer) | |
70 | mov #0x20, r1 ! | |
71 | shll8 r1 ! r1 = 8192 | |
72 | sub r1, r0 ! | |
73 | ldc r0, r7_bank ! ... and initial thread_info | |
b7e108ee | 74 | |
1da177e4 LT |
75 | ! Clear BSS area |
76 | mov.l 3f, r1 | |
77 | add #4, r1 | |
78 | mov.l 4f, r2 | |
79 | mov #0, r0 | |
80 | 9: cmp/hs r2, r1 | |
81 | bf/s 9b ! while (r1 < r2) | |
82 | mov.l r0,@-r2 | |
b7e108ee PM |
83 | |
84 | ! Additional CPU initialization | |
85 | mov.l 6f, r0 | |
86 | jsr @r0 | |
87 | nop | |
88 | ||
89 | SYNCO() ! Wait for pending instructions.. | |
90 | ||
1da177e4 LT |
91 | ! Start kernel |
92 | mov.l 5f, r0 | |
93 | jmp @r0 | |
94 | nop | |
95 | ||
96 | .balign 4 | |
97 | 1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF | |
50e98e72 | 98 | 2: .long init_thread_union+8192 |
1da177e4 LT |
99 | 3: .long __bss_start |
100 | 4: .long _end | |
101 | 5: .long start_kernel | |
102 | 6: .long sh_cpu_init |