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1da177e4 LT |
1 | /* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $ |
2 | * | |
3 | * arch/sh/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima | |
3d467676 | 6 | * Copyright (C) 2010 Matt Fleming |
1da177e4 LT |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | * | |
12 | * Head.S contains the SH exception handlers and startup code. | |
13 | */ | |
bbe215c2 | 14 | #include <linux/init.h> |
1da177e4 | 15 | #include <linux/linkage.h> |
d153ea88 | 16 | #include <asm/thread_info.h> |
a0ab3668 PM |
17 | #include <asm/mmu.h> |
18 | #include <cpu/mmu_context.h> | |
1da177e4 | 19 | |
b7e108ee PM |
20 | #ifdef CONFIG_CPU_SH4A |
21 | #define SYNCO() synco | |
22 | ||
23 | #define PREFI(label, reg) \ | |
24 | mov.l label, reg; \ | |
25 | prefi @reg | |
26 | #else | |
27 | #define SYNCO() | |
28 | #define PREFI(label, reg) | |
29 | #endif | |
30 | ||
1da177e4 LT |
31 | .section .empty_zero_page, "aw" |
32 | ENTRY(empty_zero_page) | |
33 | .long 1 /* MOUNT_ROOT_RDONLY */ | |
34 | .long 0 /* RAMDISK_FLAGS */ | |
35 | .long 0x0200 /* ORIG_ROOT_DEV */ | |
36 | .long 1 /* LOADER_TYPE */ | |
972ad0e0 PM |
37 | .long 0x00000000 /* INITRD_START */ |
38 | .long 0x00000000 /* INITRD_SIZE */ | |
a0ab3668 | 39 | #ifdef CONFIG_32BIT |
7a2eacb7 SM |
40 | .long 0x53453f00 + 32 /* "SE?" = 32 bit */ |
41 | #else | |
42 | .long 0x53453f00 + 29 /* "SE?" = 29 bit */ | |
43 | #endif | |
e2dfb912 PM |
44 | 1: |
45 | .skip PAGE_SIZE - empty_zero_page - 1b | |
1da177e4 | 46 | |
bbe215c2 | 47 | __HEAD |
339547bf | 48 | |
1da177e4 LT |
49 | /* |
50 | * Condition at the entry of _stext: | |
51 | * | |
52 | * BSC has already been initialized. | |
53 | * INTC may or may not be initialized. | |
54 | * VBR may or may not be initialized. | |
55 | * MMU may or may not be initialized. | |
56 | * Cache may or may not be initialized. | |
57 | * Hardware (including on-chip modules) may or may not be initialized. | |
58 | * | |
59 | */ | |
60 | ENTRY(_stext) | |
61 | ! Initialize Status Register | |
62 | mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF | |
63 | ldc r0, sr | |
64 | ! Initialize global interrupt mask | |
de398406 | 65 | #ifdef CONFIG_CPU_HAS_SR_RB |
aba1030a | 66 | mov #0, r0 |
1da177e4 | 67 | ldc r0, r6_bank |
de398406 YS |
68 | #endif |
69 | ||
b7e108ee PM |
70 | /* |
71 | * Prefetch if possible to reduce cache miss penalty. | |
72 | * | |
73 | * We do this early on for SH-4A as a micro-optimization, | |
74 | * as later on we will have speculative execution enabled | |
75 | * and this will become less of an issue. | |
76 | */ | |
77 | PREFI(5f, r0) | |
78 | PREFI(6f, r0) | |
79 | ||
1da177e4 LT |
80 | ! |
81 | mov.l 2f, r0 | |
82 | mov r0, r15 ! Set initial r15 (stack pointer) | |
de398406 | 83 | #ifdef CONFIG_CPU_HAS_SR_RB |
aba1030a | 84 | mov.l 7f, r0 |
1da177e4 | 85 | ldc r0, r7_bank ! ... and initial thread_info |
de398406 | 86 | #endif |
740a3e67 | 87 | |
d01447b3 | 88 | #ifdef CONFIG_PMB |
2023b843 PM |
89 | /* |
90 | * Reconfigure the initial PMB mappings setup by the hardware. | |
91 | * | |
92 | * When we boot in 32-bit MMU mode there are 2 PMB entries already | |
93 | * setup for us. | |
94 | * | |
95 | * Entry VPN PPN V SZ C UB WT | |
96 | * --------------------------------------------------------------- | |
97 | * 0 0x80000000 0x00000000 1 512MB 1 0 1 | |
98 | * 1 0xA0000000 0x00000000 1 512MB 0 0 0 | |
99 | * | |
100 | * But we reprogram them here because we want complete control over | |
101 | * our address space and the initial mappings may not map PAGE_OFFSET | |
102 | * to __MEMORY_START (or even map all of our RAM). | |
103 | * | |
104 | * Once we've setup cached and uncached mappings we clear the rest of the | |
105 | * PMB entries. This clearing also deals with the fact that PMB entries | |
106 | * can persist across reboots. The PMB could have been left in any state | |
107 | * when the reboot occurred, so to be safe we clear all entries and start | |
108 | * with with a clean slate. | |
109 | * | |
110 | * The uncached mapping is constructed using the smallest possible | |
111 | * mapping with a single unbufferable page. Only the kernel text needs to | |
112 | * be covered via the uncached mapping so that certain functions can be | |
113 | * run uncached. | |
114 | * | |
115 | * Drivers and the like that have previously abused the 1:1 identity | |
116 | * mapping are unsupported in 32-bit mode and must specify their caching | |
117 | * preference when page tables are constructed. | |
118 | * | |
119 | * This frees up the P2 space for more nefarious purposes. | |
120 | * | |
121 | * Register utilization is as follows: | |
122 | * | |
123 | * r0 = PMB_DATA data field | |
124 | * r1 = PMB_DATA address field | |
125 | * r2 = PMB_ADDR data field | |
126 | * r3 = PMB_ADDR address field | |
127 | * r4 = PMB_E_SHIFT | |
128 | * r5 = remaining amount of RAM to map | |
129 | * r6 = PMB mapping size we're trying to use | |
130 | * r7 = cached_to_uncached | |
131 | * r8 = scratch register | |
132 | * r9 = scratch register | |
133 | * r10 = number of PMB entries we've setup | |
134 | */ | |
135 | ||
136 | mov.l .LMMUCR, r1 /* Flush the TLB */ | |
137 | mov.l @r1, r0 | |
138 | or #MMUCR_TI, r0 | |
139 | mov.l r0, @r1 | |
140 | ||
141 | mov.l .LMEMORY_SIZE, r5 | |
2023b843 PM |
142 | |
143 | mov #PMB_E_SHIFT, r0 | |
144 | mov #0x1, r4 | |
145 | shld r0, r4 | |
77c2019f | 146 | |
2023b843 PM |
147 | mov.l .LFIRST_DATA_ENTRY, r0 |
148 | mov.l .LPMB_DATA, r1 | |
149 | mov.l .LFIRST_ADDR_ENTRY, r2 | |
150 | mov.l .LPMB_ADDR, r3 | |
151 | ||
d01447b3 PM |
152 | /* |
153 | * First we need to walk the PMB and figure out if there are any | |
154 | * existing mappings that match the initial mappings VPN/PPN. | |
155 | * If these have already been established by the bootloader, we | |
156 | * don't bother setting up new entries here, and let the late PMB | |
157 | * initialization take care of things instead. | |
158 | * | |
159 | * Note that we may need to coalesce and merge entries in order | |
160 | * to reclaim more available PMB slots, which is much more than | |
161 | * we want to do at this early stage. | |
162 | */ | |
163 | mov #0, r10 | |
164 | mov #NR_PMB_ENTRIES, r9 | |
165 | ||
166 | mov r1, r7 /* temporary PMB_DATA iter */ | |
167 | ||
168 | .Lvalidate_existing_mappings: | |
169 | ||
170 | mov.l @r7, r8 | |
171 | and r0, r8 | |
172 | cmp/eq r0, r8 /* Check for valid __MEMORY_START mappings */ | |
173 | bt .Lpmb_done | |
174 | ||
175 | add #1, r10 /* Increment the loop counter */ | |
176 | cmp/eq r9, r10 | |
177 | bf/s .Lvalidate_existing_mappings | |
178 | add r4, r7 /* Increment to the next PMB_DATA entry */ | |
179 | ||
180 | /* | |
181 | * If we've fallen through, continue with setting up the initial | |
182 | * mappings. | |
183 | */ | |
184 | ||
185 | mov r5, r7 /* cached_to_uncached */ | |
2023b843 PM |
186 | mov #0, r10 |
187 | ||
9edef286 | 188 | #ifdef CONFIG_UNCACHED_MAPPING |
2023b843 PM |
189 | /* |
190 | * Uncached mapping | |
191 | */ | |
192 | mov #(PMB_SZ_16M >> 2), r9 | |
193 | shll2 r9 | |
194 | ||
195 | mov #(PMB_UB >> 8), r8 | |
196 | shll8 r8 | |
197 | ||
198 | or r0, r8 | |
199 | or r9, r8 | |
200 | mov.l r8, @r1 | |
201 | mov r2, r8 | |
202 | add r7, r8 | |
203 | mov.l r8, @r3 | |
204 | ||
205 | add r4, r1 | |
206 | add r4, r3 | |
207 | add #1, r10 | |
9edef286 | 208 | #endif |
2023b843 PM |
209 | |
210 | /* | |
211 | * Iterate over all of the available sizes from largest to | |
212 | * smallest for constructing the cached mapping. | |
213 | */ | |
77c2019f PM |
214 | #define __PMB_ITER_BY_SIZE(size) \ |
215 | .L##size: \ | |
216 | mov #(size >> 4), r6; \ | |
217 | shll16 r6; \ | |
218 | shll8 r6; \ | |
219 | \ | |
220 | cmp/hi r5, r6; \ | |
221 | bt 9999f; \ | |
222 | \ | |
223 | mov #(PMB_SZ_##size##M >> 2), r9; \ | |
224 | shll2 r9; \ | |
225 | \ | |
226 | /* \ | |
227 | * Cached mapping \ | |
228 | */ \ | |
229 | mov #PMB_C, r8; \ | |
230 | or r0, r8; \ | |
231 | or r9, r8; \ | |
232 | mov.l r8, @r1; \ | |
233 | mov.l r2, @r3; \ | |
234 | \ | |
235 | /* Increment to the next PMB_DATA entry */ \ | |
236 | add r4, r1; \ | |
237 | /* Increment to the next PMB_ADDR entry */ \ | |
238 | add r4, r3; \ | |
239 | /* Increment number of PMB entries */ \ | |
77c2019f PM |
240 | add #1, r10; \ |
241 | \ | |
242 | sub r6, r5; \ | |
243 | add r6, r0; \ | |
244 | add r6, r2; \ | |
245 | \ | |
246 | bra .L##size; \ | |
247 | 9999: | |
248 | ||
77c2019f PM |
249 | __PMB_ITER_BY_SIZE(512) |
250 | __PMB_ITER_BY_SIZE(128) | |
251 | __PMB_ITER_BY_SIZE(64) | |
252 | __PMB_ITER_BY_SIZE(16) | |
3d467676 | 253 | |
9edef286 | 254 | #ifdef CONFIG_UNCACHED_MAPPING |
2023b843 | 255 | /* |
3125ee72 PM |
256 | * Now that we can access it, update cached_to_uncached and |
257 | * uncached_size. | |
2023b843 | 258 | */ |
3d467676 MF |
259 | mov.l .Lcached_to_uncached, r0 |
260 | mov.l r7, @r0 | |
261 | ||
3125ee72 PM |
262 | mov.l .Luncached_size, r0 |
263 | mov #1, r7 | |
264 | shll16 r7 | |
265 | shll8 r7 | |
266 | mov.l r7, @r0 | |
9edef286 | 267 | #endif |
3125ee72 | 268 | |
3d467676 MF |
269 | /* |
270 | * Clear the remaining PMB entries. | |
271 | * | |
272 | * r3 = entry to begin clearing from | |
273 | * r10 = number of entries we've setup so far | |
274 | */ | |
275 | mov #0, r1 | |
51becfd9 | 276 | mov #NR_PMB_ENTRIES, r0 |
3d467676 MF |
277 | |
278 | .Lagain: | |
279 | mov.l r1, @r3 /* Clear PMB_ADDR entry */ | |
280 | add #1, r10 /* Increment the loop counter */ | |
281 | cmp/eq r0, r10 | |
282 | bf/s .Lagain | |
283 | add r4, r3 /* Increment to the next PMB_ADDR entry */ | |
284 | ||
285 | mov.l 6f, r0 | |
286 | icbi @r0 | |
287 | ||
d01447b3 PM |
288 | .Lpmb_done: |
289 | #endif /* CONFIG_PMB */ | |
3d467676 | 290 | |
740a3e67 PM |
291 | #ifndef CONFIG_SH_NO_BSS_INIT |
292 | /* | |
293 | * Don't clear BSS if running on slow platforms such as an RTL simulation, | |
294 | * remote memory via SHdebug link, etc. For these the memory can be guaranteed | |
295 | * to be all zero on boot anyway. | |
296 | */ | |
297 | ! Clear BSS area | |
aba1030a PM |
298 | #ifdef CONFIG_SMP |
299 | mov.l 3f, r0 | |
300 | cmp/eq #0, r0 ! skip clear if set to zero | |
301 | bt 10f | |
302 | #endif | |
303 | ||
1da177e4 LT |
304 | mov.l 3f, r1 |
305 | add #4, r1 | |
306 | mov.l 4f, r2 | |
307 | mov #0, r0 | |
308 | 9: cmp/hs r2, r1 | |
309 | bf/s 9b ! while (r1 < r2) | |
310 | mov.l r0,@-r2 | |
b7e108ee | 311 | |
aba1030a | 312 | 10: |
740a3e67 PM |
313 | #endif |
314 | ||
b7e108ee PM |
315 | ! Additional CPU initialization |
316 | mov.l 6f, r0 | |
317 | jsr @r0 | |
318 | nop | |
319 | ||
320 | SYNCO() ! Wait for pending instructions.. | |
aba1030a | 321 | |
1da177e4 LT |
322 | ! Start kernel |
323 | mov.l 5f, r0 | |
324 | jmp @r0 | |
325 | nop | |
326 | ||
327 | .balign 4 | |
de398406 YS |
328 | #if defined(CONFIG_CPU_SH2) |
329 | 1: .long 0x000000F0 ! IMASK=0xF | |
330 | #else | |
1da177e4 | 331 | 1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF |
de398406 | 332 | #endif |
aba1030a | 333 | ENTRY(stack_start) |
d153ea88 | 334 | 2: .long init_thread_union+THREAD_SIZE |
1da177e4 LT |
335 | 3: .long __bss_start |
336 | 4: .long _end | |
337 | 5: .long start_kernel | |
338 | 6: .long sh_cpu_init | |
aba1030a | 339 | 7: .long init_thread_union |
3d467676 | 340 | |
d01447b3 | 341 | #ifdef CONFIG_PMB |
3d467676 MF |
342 | .LPMB_ADDR: .long PMB_ADDR |
343 | .LPMB_DATA: .long PMB_DATA | |
344 | .LFIRST_ADDR_ENTRY: .long PAGE_OFFSET | PMB_V | |
345 | .LFIRST_DATA_ENTRY: .long __MEMORY_START | PMB_V | |
346 | .LMMUCR: .long MMUCR | |
9edef286 PM |
347 | .LMEMORY_SIZE: .long __MEMORY_SIZE |
348 | #ifdef CONFIG_UNCACHED_MAPPING | |
3d467676 | 349 | .Lcached_to_uncached: .long cached_to_uncached |
3125ee72 | 350 | .Luncached_size: .long uncached_size |
9edef286 | 351 | #endif |
3d467676 | 352 | #endif |