[deliverable/linux.git] / arch / sh / kernel / head_32.S

/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
 *
 *  arch/sh/kernel/head.S
 *
 *  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
 *  Copyright (C) 2010  Matt Fleming
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Head.S contains the SH exception handlers and startup code.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/mmu.h>
#include <cpu/mmu_context.h>

#ifdef CONFIG_CPU_SH4A
#define SYNCO()		synco

#define PREFI(label, reg)	\
	mov.l	label, reg;	\
	prefi	@reg
#else
#define SYNCO()
#define PREFI(label, reg)
#endif

	.section	.empty_zero_page, "aw"
ENTRY(empty_zero_page)
	.long	1		/* MOUNT_ROOT_RDONLY */
	.long	0		/* RAMDISK_FLAGS */
	.long	0x0200		/* ORIG_ROOT_DEV */
	.long	1		/* LOADER_TYPE */
	.long	0x00000000	/* INITRD_START */
	.long	0x00000000	/* INITRD_SIZE */
#ifdef CONFIG_32BIT
	.long	0x53453f00 + 32	/* "SE?" = 32 bit */
#else
	.long	0x53453f00 + 29	/* "SE?" = 29 bit */
#endif
1:
	.skip	PAGE_SIZE - empty_zero_page - 1b

	__HEAD

/*
 * Condition at the entry of _stext:
 *
 *   BSC has already been initialized.
 *   INTC may or may not be initialized.
 *   VBR may or may not be initialized.
 *   MMU may or may not be initialized.
 *   Cache may or may not be initialized.
 *   Hardware (including on-chip modules) may or may not be initialized. 
 *
 */
ENTRY(_stext)
	!			Initialize Status Register
	mov.l	1f, r0		! MD=1, RB=0, BL=0, IMASK=0xF
	ldc	r0, sr
	!			Initialize global interrupt mask
#ifdef CONFIG_CPU_HAS_SR_RB
	mov	#0, r0
	ldc	r0, r6_bank
#endif
	
	/*
	 * Prefetch if possible to reduce cache miss penalty.
	 *
	 * We do this early on for SH-4A as a micro-optimization,
	 * as later on we will have speculative execution enabled
	 * and this will become less of an issue.
	 */
	PREFI(5f, r0)
	PREFI(6f, r0)

	!
	mov.l	2f, r0
	mov	r0, r15		! Set initial r15 (stack pointer)
#ifdef CONFIG_CPU_HAS_SR_RB
	mov.l	7f, r0
	ldc	r0, r7_bank	! ... and initial thread_info
#endif

#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
/*
 * Reconfigure the initial PMB mappings setup by the hardware.
 *
 * When we boot in 32-bit MMU mode there are 2 PMB entries already
 * setup for us.
 *
 * Entry       VPN	   PPN	    V	SZ	C	UB	WT
 * ---------------------------------------------------------------
 *   0	    0x80000000 0x00000000   1  512MB	1	0	1
 *   1	    0xA0000000 0x00000000   1  512MB	0	0	0
 *
 * But we reprogram them here because we want complete control over
 * our address space and the initial mappings may not map PAGE_OFFSET
 * to __MEMORY_START (or even map all of our RAM).
 *
 * Once we've setup cached and uncached mappings we clear the rest of the
 * PMB entries. This clearing also deals with the fact that PMB entries
 * can persist across reboots. The PMB could have been left in any state
 * when the reboot occurred, so to be safe we clear all entries and start
 * with with a clean slate.
 *
 * The uncached mapping is constructed using the smallest possible
 * mapping with a single unbufferable page. Only the kernel text needs to
 * be covered via the uncached mapping so that certain functions can be
 * run uncached.
 *
 * Drivers and the like that have previously abused the 1:1 identity
 * mapping are unsupported in 32-bit mode and must specify their caching
 * preference when page tables are constructed.
 *
 * This frees up the P2 space for more nefarious purposes.
 *
 * Register utilization is as follows:
 *
 *	r0 = PMB_DATA data field
 *	r1 = PMB_DATA address field
 *	r2 = PMB_ADDR data field
 *	r3 = PMB_ADDR address field
 *	r4 = PMB_E_SHIFT
 *	r5 = remaining amount of RAM to map
 *	r6 = PMB mapping size we're trying to use
 *	r7 = cached_to_uncached
 *	r8 = scratch register
 *	r9 = scratch register
 *	r10 = number of PMB entries we've setup
 */

	mov.l	.LMMUCR, r1	/* Flush the TLB */
	mov.l	@r1, r0
	or	#MMUCR_TI, r0
	mov.l	r0, @r1

	mov.l	.LMEMORY_SIZE, r5
	mov	r5, r7

	mov	#PMB_E_SHIFT, r0
	mov	#0x1, r4
	shld	r0, r4

	mov.l	.LFIRST_DATA_ENTRY, r0
	mov.l	.LPMB_DATA, r1
	mov.l	.LFIRST_ADDR_ENTRY, r2
	mov.l	.LPMB_ADDR, r3

	mov	#0, r10

	/*
	 * Uncached mapping
	 */
	mov	#(PMB_SZ_16M >> 2), r9
	shll2	r9

	mov	#(PMB_UB >> 8), r8
	shll8	r8

	or	r0, r8
	or	r9, r8
	mov.l	r8, @r1
	mov	r2, r8
	add	r7, r8
	mov.l	r8, @r3

	add	r4, r1
	add	r4, r3
	add	#1, r10

/*
 * Iterate over all of the available sizes from largest to
 * smallest for constructing the cached mapping.
 */
#define __PMB_ITER_BY_SIZE(size)			\
.L##size:						\
	mov	#(size >> 4), r6;			\
	shll16	r6;					\
	shll8	r6;					\
							\
	cmp/hi	r5, r6;					\
	bt	9999f;					\
							\
	mov	#(PMB_SZ_##size##M >> 2), r9;		\
	shll2	r9;					\
							\
	/*						\
	 * Cached mapping				\
	 */						\
	mov	#PMB_C, r8;				\
	or	r0, r8;					\
	or	r9, r8;					\
	mov.l	r8, @r1;				\
	mov.l	r2, @r3;				\
							\
	/* Increment to the next PMB_DATA entry */	\
	add	r4, r1;					\
	/* Increment to the next PMB_ADDR entry */	\
	add	r4, r3;					\
	/* Increment number of PMB entries */		\
	add	#1, r10;				\
							\
	sub	r6, r5;					\
	add	r6, r0;					\
	add	r6, r2;					\
							\
	bra	.L##size;				\
9999:

	__PMB_ITER_BY_SIZE(512)
	__PMB_ITER_BY_SIZE(128)
	__PMB_ITER_BY_SIZE(64)
	__PMB_ITER_BY_SIZE(16)

	/*
	 * Now that we can access it, update cached_to_uncached and
	 * uncached_size.
	 */
	mov.l	.Lcached_to_uncached, r0
	mov.l	r7, @r0

	mov.l	.Luncached_size, r0
	mov	#1, r7
	shll16	r7
	shll8	r7
	mov.l	r7, @r0

	/*
	 * Clear the remaining PMB entries.
	 *
	 * r3 = entry to begin clearing from
	 * r10 = number of entries we've setup so far
	 */
	mov	#0, r1
	mov	#PMB_ENTRY_MAX, r0

.Lagain:
	mov.l	r1, @r3		/* Clear PMB_ADDR entry */
	add	#1, r10		/* Increment the loop counter */
	cmp/eq	r0, r10
	bf/s	.Lagain
	 add	r4, r3		/* Increment to the next PMB_ADDR entry */

	mov.l	6f, r0
	icbi	@r0

#endif /* !CONFIG_PMB_LEGACY */

#ifndef CONFIG_SH_NO_BSS_INIT
	/*
	 * Don't clear BSS if running on slow platforms such as an RTL simulation,
	 * remote memory via SHdebug link, etc.  For these the memory can be guaranteed
	 * to be all zero on boot anyway.
	 */
				! Clear BSS area
#ifdef CONFIG_SMP	
	mov.l	3f, r0
	cmp/eq	#0, r0		! skip clear if set to zero
	bt	10f
#endif
	
	mov.l	3f, r1
	add	#4, r1
	mov.l	4f, r2
	mov	#0, r0
9:	cmp/hs	r2, r1
	bf/s	9b		! while (r1 < r2)
	 mov.l	r0,@-r2

10:		
#endif

	!			Additional CPU initialization
	mov.l	6f, r0
	jsr	@r0
	 nop

	SYNCO()			! Wait for pending instructions..
	
	!			Start kernel
	mov.l	5f, r0
	jmp	@r0
	 nop

	.balign 4
#if defined(CONFIG_CPU_SH2)
1:	.long	0x000000F0		! IMASK=0xF
#else
1:	.long	0x400080F0		! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
#endif
ENTRY(stack_start)
2:	.long	init_thread_union+THREAD_SIZE
3:	.long	__bss_start
4:	.long	_end
5:	.long	start_kernel
6:	.long	sh_cpu_init
7:	.long	init_thread_union

#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
.LPMB_ADDR:		.long	PMB_ADDR
.LPMB_DATA:		.long	PMB_DATA
.LFIRST_ADDR_ENTRY:	.long	PAGE_OFFSET | PMB_V
.LFIRST_DATA_ENTRY:	.long	__MEMORY_START | PMB_V
.LMMUCR:		.long	MMUCR
.Lcached_to_uncached:	.long	cached_to_uncached
.Luncached_size:	.long	uncached_size
.LMEMORY_SIZE:		.long	__MEMORY_SIZE
#endif
Commit	Line	Data
1da177e4 LT	1	/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
	2	*
	3	* arch/sh/kernel/head.S
	4	*
	5	* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
3d467676	6	* Copyright (C) 2010 Matt Fleming
1da177e4 LT	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*
	12	* Head.S contains the SH exception handlers and startup code.
	13	*/
bbe215c2	14	#include <linux/init.h>
1da177e4	15	#include <linux/linkage.h>
d153ea88	16	#include <asm/thread_info.h>
a0ab3668 PM	17	#include <asm/mmu.h>
a0ab3668 PM	18	#include <cpu/mmu_context.h>
1da177e4	19
b7e108ee PM	20	#ifdef CONFIG_CPU_SH4A
	21	#define SYNCO() synco
	22
	23	#define PREFI(label, reg) \
	24	mov.l label, reg; \
	25	prefi @reg
	26	#else
	27	#define SYNCO()
	28	#define PREFI(label, reg)
	29	#endif
	30
1da177e4 LT	31	.section .empty_zero_page, "aw"
	32	ENTRY(empty_zero_page)
	33	.long 1 /* MOUNT_ROOT_RDONLY */
	34	.long 0 /* RAMDISK_FLAGS */
	35	.long 0x0200 /* ORIG_ROOT_DEV */
	36	.long 1 /* LOADER_TYPE */
972ad0e0 PM	37	.long 0x00000000 /* INITRD_START */
972ad0e0 PM	38	.long 0x00000000 /* INITRD_SIZE */
a0ab3668	39	#ifdef CONFIG_32BIT
7a2eacb7 SM	40	.long 0x53453f00 + 32 /* "SE?" = 32 bit */
	41	#else
	42	.long 0x53453f00 + 29 /* "SE?" = 29 bit */
	43	#endif
e2dfb912 PM	44	1:
e2dfb912 PM	45	.skip PAGE_SIZE - empty_zero_page - 1b
1da177e4	46
bbe215c2	47	__HEAD
339547bf	48
1da177e4 LT	49	/*
	50	* Condition at the entry of _stext:
	51	*
	52	* BSC has already been initialized.
	53	* INTC may or may not be initialized.
	54	* VBR may or may not be initialized.
	55	* MMU may or may not be initialized.
	56	* Cache may or may not be initialized.
	57	* Hardware (including on-chip modules) may or may not be initialized.
	58	*
	59	*/
	60	ENTRY(_stext)
	61	! Initialize Status Register
	62	mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
	63	ldc r0, sr
	64	! Initialize global interrupt mask
de398406	65	#ifdef CONFIG_CPU_HAS_SR_RB
aba1030a	66	mov #0, r0
1da177e4	67	ldc r0, r6_bank
de398406 YS	68	#endif
de398406 YS	69
b7e108ee PM	70	/*
	71	* Prefetch if possible to reduce cache miss penalty.
	72	*
	73	* We do this early on for SH-4A as a micro-optimization,
	74	* as later on we will have speculative execution enabled
	75	* and this will become less of an issue.
	76	*/
	77	PREFI(5f, r0)
	78	PREFI(6f, r0)
	79
1da177e4 LT	80	!
	81	mov.l 2f, r0
	82	mov r0, r15 ! Set initial r15 (stack pointer)
de398406	83	#ifdef CONFIG_CPU_HAS_SR_RB
aba1030a	84	mov.l 7f, r0
1da177e4	85	ldc r0, r7_bank ! ... and initial thread_info
de398406	86	#endif
740a3e67	87
3d467676	88	#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
2023b843 PM	89	/*
	90	* Reconfigure the initial PMB mappings setup by the hardware.
	91	*
	92	* When we boot in 32-bit MMU mode there are 2 PMB entries already
	93	* setup for us.
	94	*
	95	* Entry VPN PPN V SZ C UB WT
	96	* ---------------------------------------------------------------
	97	* 0 0x80000000 0x00000000 1 512MB 1 0 1
	98	* 1 0xA0000000 0x00000000 1 512MB 0 0 0
	99	*
	100	* But we reprogram them here because we want complete control over
	101	* our address space and the initial mappings may not map PAGE_OFFSET
	102	* to __MEMORY_START (or even map all of our RAM).
	103	*
	104	* Once we've setup cached and uncached mappings we clear the rest of the
	105	* PMB entries. This clearing also deals with the fact that PMB entries
	106	* can persist across reboots. The PMB could have been left in any state
	107	* when the reboot occurred, so to be safe we clear all entries and start
	108	* with with a clean slate.
	109	*
	110	* The uncached mapping is constructed using the smallest possible
	111	* mapping with a single unbufferable page. Only the kernel text needs to
	112	* be covered via the uncached mapping so that certain functions can be
	113	* run uncached.
	114	*
	115	* Drivers and the like that have previously abused the 1:1 identity
	116	* mapping are unsupported in 32-bit mode and must specify their caching
	117	* preference when page tables are constructed.
	118	*
	119	* This frees up the P2 space for more nefarious purposes.
	120	*
	121	* Register utilization is as follows:
	122	*
	123	* r0 = PMB_DATA data field
	124	* r1 = PMB_DATA address field
	125	* r2 = PMB_ADDR data field
	126	* r3 = PMB_ADDR address field
	127	* r4 = PMB_E_SHIFT
	128	* r5 = remaining amount of RAM to map
	129	* r6 = PMB mapping size we're trying to use
	130	* r7 = cached_to_uncached
	131	* r8 = scratch register
	132	* r9 = scratch register
	133	* r10 = number of PMB entries we've setup
	134	*/
	135
	136	mov.l .LMMUCR, r1 /* Flush the TLB */
	137	mov.l @r1, r0
	138	or #MMUCR_TI, r0
	139	mov.l r0, @r1
	140
	141	mov.l .LMEMORY_SIZE, r5
	142	mov r5, r7
	143
	144	mov #PMB_E_SHIFT, r0
	145	mov #0x1, r4
	146	shld r0, r4
77c2019f	147
2023b843 PM	148	mov.l .LFIRST_DATA_ENTRY, r0
	149	mov.l .LPMB_DATA, r1
	150	mov.l .LFIRST_ADDR_ENTRY, r2
	151	mov.l .LPMB_ADDR, r3
	152
	153	mov #0, r10
	154
	155	/*
	156	* Uncached mapping
	157	*/
	158	mov #(PMB_SZ_16M >> 2), r9
	159	shll2 r9
	160
	161	mov #(PMB_UB >> 8), r8
	162	shll8 r8
	163
	164	or r0, r8
	165	or r9, r8
	166	mov.l r8, @r1
	167	mov r2, r8
	168	add r7, r8
	169	mov.l r8, @r3
	170
	171	add r4, r1
	172	add r4, r3
	173	add #1, r10
	174
	175	/*
	176	* Iterate over all of the available sizes from largest to
	177	* smallest for constructing the cached mapping.
	178	*/
77c2019f PM	179	#define __PMB_ITER_BY_SIZE(size) \
	180	.L##size: \
	181	mov #(size >> 4), r6; \
	182	shll16 r6; \
	183	shll8 r6; \
	184	\
	185	cmp/hi r5, r6; \
	186	bt 9999f; \
	187	\
	188	mov #(PMB_SZ_##size##M >> 2), r9; \
	189	shll2 r9; \
	190	\
	191	/* \
	192	* Cached mapping \
	193	*/ \
	194	mov #PMB_C, r8; \
	195	or r0, r8; \
	196	or r9, r8; \
	197	mov.l r8, @r1; \
	198	mov.l r2, @r3; \
	199	\
	200	/* Increment to the next PMB_DATA entry */ \
	201	add r4, r1; \
	202	/* Increment to the next PMB_ADDR entry */ \
	203	add r4, r3; \
	204	/* Increment number of PMB entries */ \
77c2019f PM	205	add #1, r10; \
	206	\
	207	sub r6, r5; \
	208	add r6, r0; \
	209	add r6, r2; \
	210	\
	211	bra .L##size; \
	212	9999:
	213
77c2019f PM	214	__PMB_ITER_BY_SIZE(512)
	215	__PMB_ITER_BY_SIZE(128)
	216	__PMB_ITER_BY_SIZE(64)
	217	__PMB_ITER_BY_SIZE(16)
3d467676	218
2023b843	219	/*
3125ee72 PM	220	* Now that we can access it, update cached_to_uncached and
3125ee72 PM	221	* uncached_size.
2023b843	222	*/
3d467676 MF	223	mov.l .Lcached_to_uncached, r0
	224	mov.l r7, @r0
	225
3125ee72 PM	226	mov.l .Luncached_size, r0
	227	mov #1, r7
	228	shll16 r7
	229	shll8 r7
	230	mov.l r7, @r0
	231
3d467676 MF	232	/*
	233	* Clear the remaining PMB entries.
	234	*
	235	* r3 = entry to begin clearing from
	236	* r10 = number of entries we've setup so far
	237	*/
	238	mov #0, r1
	239	mov #PMB_ENTRY_MAX, r0
	240
	241	.Lagain:
	242	mov.l r1, @r3 /* Clear PMB_ADDR entry */
	243	add #1, r10 /* Increment the loop counter */
	244	cmp/eq r0, r10
	245	bf/s .Lagain
	246	add r4, r3 /* Increment to the next PMB_ADDR entry */
	247
	248	mov.l 6f, r0
	249	icbi @r0
	250
	251	#endif /* !CONFIG_PMB_LEGACY */
	252
740a3e67 PM	253	#ifndef CONFIG_SH_NO_BSS_INIT
	254	/*
	255	* Don't clear BSS if running on slow platforms such as an RTL simulation,
	256	* remote memory via SHdebug link, etc. For these the memory can be guaranteed
	257	* to be all zero on boot anyway.
	258	*/
	259	! Clear BSS area
aba1030a PM	260	#ifdef CONFIG_SMP
	261	mov.l 3f, r0
	262	cmp/eq #0, r0 ! skip clear if set to zero
	263	bt 10f
	264	#endif
	265
1da177e4 LT	266	mov.l 3f, r1
	267	add #4, r1
	268	mov.l 4f, r2
	269	mov #0, r0
	270	9: cmp/hs r2, r1
	271	bf/s 9b ! while (r1 < r2)
	272	mov.l r0,@-r2
b7e108ee	273
aba1030a	274	10:
740a3e67 PM	275	#endif
740a3e67 PM	276
b7e108ee PM	277	! Additional CPU initialization
	278	mov.l 6f, r0
	279	jsr @r0
	280	nop
	281
	282	SYNCO() ! Wait for pending instructions..
aba1030a	283
1da177e4 LT	284	! Start kernel
	285	mov.l 5f, r0
	286	jmp @r0
	287	nop
	288
	289	.balign 4
de398406 YS	290	#if defined(CONFIG_CPU_SH2)
	291	1: .long 0x000000F0 ! IMASK=0xF
	292	#else
1da177e4	293	1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
de398406	294	#endif
aba1030a	295	ENTRY(stack_start)
d153ea88	296	2: .long init_thread_union+THREAD_SIZE
1da177e4 LT	297	3: .long __bss_start
	298	4: .long _end
	299	5: .long start_kernel
	300	6: .long sh_cpu_init
aba1030a	301	7: .long init_thread_union
3d467676 MF	302
	303	#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
	304	.LPMB_ADDR: .long PMB_ADDR
	305	.LPMB_DATA: .long PMB_DATA
	306	.LFIRST_ADDR_ENTRY: .long PAGE_OFFSET \| PMB_V
	307	.LFIRST_DATA_ENTRY: .long __MEMORY_START \| PMB_V
	308	.LMMUCR: .long MMUCR
	309	.Lcached_to_uncached: .long cached_to_uncached
3125ee72	310	.Luncached_size: .long uncached_size
3d467676 MF	311	.LMEMORY_SIZE: .long __MEMORY_SIZE
3d467676 MF	312	#endif