[deliverable/linux.git] / arch / sh / kernel / head_32.S

/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
 *
 *  arch/sh/kernel/head.S
 *
 *  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Head.S contains the SH exception handlers and startup code.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/mmu.h>
#include <cpu/mmu_context.h>

#ifdef CONFIG_CPU_SH4A
#define SYNCO()		synco

#define PREFI(label, reg)	\
	mov.l	label, reg;	\
	prefi	@reg
#else
#define SYNCO()
#define PREFI(label, reg)
#endif

	.section	.empty_zero_page, "aw"
ENTRY(empty_zero_page)
	.long	1		/* MOUNT_ROOT_RDONLY */
	.long	0		/* RAMDISK_FLAGS */
	.long	0x0200		/* ORIG_ROOT_DEV */
	.long	1		/* LOADER_TYPE */
	.long	0x00000000	/* INITRD_START */
	.long	0x00000000	/* INITRD_SIZE */
#ifdef CONFIG_32BIT
	.long	0x53453f00 + 32	/* "SE?" = 32 bit */
#else
	.long	0x53453f00 + 29	/* "SE?" = 29 bit */
#endif
1:
	.skip	PAGE_SIZE - empty_zero_page - 1b

	__HEAD

/*
 * Condition at the entry of _stext:
 *
 *   BSC has already been initialized.
 *   INTC may or may not be initialized.
 *   VBR may or may not be initialized.
 *   MMU may or may not be initialized.
 *   Cache may or may not be initialized.
 *   Hardware (including on-chip modules) may or may not be initialized. 
 *
 */
ENTRY(_stext)
	!			Initialize Status Register
	mov.l	1f, r0		! MD=1, RB=0, BL=0, IMASK=0xF
	ldc	r0, sr
	!			Initialize global interrupt mask
#ifdef CONFIG_CPU_HAS_SR_RB
	mov	#0, r0
	ldc	r0, r6_bank
#endif
	
	/*
	 * Prefetch if possible to reduce cache miss penalty.
	 *
	 * We do this early on for SH-4A as a micro-optimization,
	 * as later on we will have speculative execution enabled
	 * and this will become less of an issue.
	 */
	PREFI(5f, r0)
	PREFI(6f, r0)

	!
	mov.l	2f, r0
	mov	r0, r15		! Set initial r15 (stack pointer)
#ifdef CONFIG_CPU_HAS_SR_RB
	mov.l	7f, r0
	ldc	r0, r7_bank	! ... and initial thread_info
#endif

#ifndef CONFIG_SH_NO_BSS_INIT
	/*
	 * Don't clear BSS if running on slow platforms such as an RTL simulation,
	 * remote memory via SHdebug link, etc.  For these the memory can be guaranteed
	 * to be all zero on boot anyway.
	 */
				! Clear BSS area
#ifdef CONFIG_SMP	
	mov.l	3f, r0
	cmp/eq	#0, r0		! skip clear if set to zero
	bt	10f
#endif
	
	mov.l	3f, r1
	add	#4, r1
	mov.l	4f, r2
	mov	#0, r0
9:	cmp/hs	r2, r1
	bf/s	9b		! while (r1 < r2)
	 mov.l	r0,@-r2

10:		
#endif

	!			Additional CPU initialization
	mov.l	6f, r0
	jsr	@r0
	 nop

	SYNCO()			! Wait for pending instructions..
	
	!			Start kernel
	mov.l	5f, r0
	jmp	@r0
	 nop

	.balign 4
#if defined(CONFIG_CPU_SH2)
1:	.long	0x000000F0		! IMASK=0xF
#else
1:	.long	0x400080F0		! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
#endif
ENTRY(stack_start)
2:	.long	init_thread_union+THREAD_SIZE
3:	.long	__bss_start
4:	.long	_end
5:	.long	start_kernel
6:	.long	sh_cpu_init
7:	.long	init_thread_union
Commit	Line	Data
1da177e4 LT	1	/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
	2	*
	3	* arch/sh/kernel/head.S
	4	*
	5	* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*
	11	* Head.S contains the SH exception handlers and startup code.
	12	*/
bbe215c2	13	#include <linux/init.h>
1da177e4	14	#include <linux/linkage.h>
d153ea88	15	#include <asm/thread_info.h>
a0ab3668 PM	16	#include <asm/mmu.h>
a0ab3668 PM	17	#include <cpu/mmu_context.h>
1da177e4	18
b7e108ee PM	19	#ifdef CONFIG_CPU_SH4A
	20	#define SYNCO() synco
	21
	22	#define PREFI(label, reg) \
	23	mov.l label, reg; \
	24	prefi @reg
	25	#else
	26	#define SYNCO()
	27	#define PREFI(label, reg)
	28	#endif
	29
1da177e4 LT	30	.section .empty_zero_page, "aw"
	31	ENTRY(empty_zero_page)
	32	.long 1 /* MOUNT_ROOT_RDONLY */
	33	.long 0 /* RAMDISK_FLAGS */
	34	.long 0x0200 /* ORIG_ROOT_DEV */
	35	.long 1 /* LOADER_TYPE */
972ad0e0 PM	36	.long 0x00000000 /* INITRD_START */
972ad0e0 PM	37	.long 0x00000000 /* INITRD_SIZE */
a0ab3668	38	#ifdef CONFIG_32BIT
7a2eacb7 SM	39	.long 0x53453f00 + 32 /* "SE?" = 32 bit */
	40	#else
	41	.long 0x53453f00 + 29 /* "SE?" = 29 bit */
	42	#endif
e2dfb912 PM	43	1:
e2dfb912 PM	44	.skip PAGE_SIZE - empty_zero_page - 1b
1da177e4	45
bbe215c2	46	__HEAD
339547bf	47
1da177e4 LT	48	/*
	49	* Condition at the entry of _stext:
	50	*
	51	* BSC has already been initialized.
	52	* INTC may or may not be initialized.
	53	* VBR may or may not be initialized.
	54	* MMU may or may not be initialized.
	55	* Cache may or may not be initialized.
	56	* Hardware (including on-chip modules) may or may not be initialized.
	57	*
	58	*/
	59	ENTRY(_stext)
	60	! Initialize Status Register
	61	mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
	62	ldc r0, sr
	63	! Initialize global interrupt mask
de398406	64	#ifdef CONFIG_CPU_HAS_SR_RB
aba1030a	65	mov #0, r0
1da177e4	66	ldc r0, r6_bank
de398406 YS	67	#endif
de398406 YS	68
b7e108ee PM	69	/*
	70	* Prefetch if possible to reduce cache miss penalty.
	71	*
	72	* We do this early on for SH-4A as a micro-optimization,
	73	* as later on we will have speculative execution enabled
	74	* and this will become less of an issue.
	75	*/
	76	PREFI(5f, r0)
	77	PREFI(6f, r0)
	78
1da177e4 LT	79	!
	80	mov.l 2f, r0
	81	mov r0, r15 ! Set initial r15 (stack pointer)
de398406	82	#ifdef CONFIG_CPU_HAS_SR_RB
aba1030a	83	mov.l 7f, r0
1da177e4	84	ldc r0, r7_bank ! ... and initial thread_info
de398406	85	#endif
740a3e67 PM	86
	87	#ifndef CONFIG_SH_NO_BSS_INIT
	88	/*
	89	* Don't clear BSS if running on slow platforms such as an RTL simulation,
	90	* remote memory via SHdebug link, etc. For these the memory can be guaranteed
	91	* to be all zero on boot anyway.
	92	*/
	93	! Clear BSS area
aba1030a PM	94	#ifdef CONFIG_SMP
	95	mov.l 3f, r0
	96	cmp/eq #0, r0 ! skip clear if set to zero
	97	bt 10f
	98	#endif
	99
1da177e4 LT	100	mov.l 3f, r1
	101	add #4, r1
	102	mov.l 4f, r2
	103	mov #0, r0
	104	9: cmp/hs r2, r1
	105	bf/s 9b ! while (r1 < r2)
	106	mov.l r0,@-r2
b7e108ee	107
aba1030a	108	10:
740a3e67 PM	109	#endif
740a3e67 PM	110
b7e108ee PM	111	! Additional CPU initialization
	112	mov.l 6f, r0
	113	jsr @r0
	114	nop
	115
	116	SYNCO() ! Wait for pending instructions..
aba1030a	117
1da177e4 LT	118	! Start kernel
	119	mov.l 5f, r0
	120	jmp @r0
	121	nop
	122
	123	.balign 4
de398406 YS	124	#if defined(CONFIG_CPU_SH2)
	125	1: .long 0x000000F0 ! IMASK=0xF
	126	#else
1da177e4	127	1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
de398406	128	#endif
aba1030a	129	ENTRY(stack_start)
d153ea88	130	2: .long init_thread_union+THREAD_SIZE
1da177e4 LT	131	3: .long __bss_start
	132	4: .long _end
	133	5: .long start_kernel
	134	6: .long sh_cpu_init
aba1030a	135	7: .long init_thread_union