sh: check for existing mappings for bolted PMB entries.
[deliverable/linux.git] / arch / sh / mm / pmb.c
CommitLineData
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1/*
2 * arch/sh/mm/pmb.c
3 *
4 * Privileged Space Mapping Buffer (PMB) Support.
5 *
3d467676
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6 * Copyright (C) 2005 - 2010 Paul Mundt
7 * Copyright (C) 2010 Matt Fleming
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8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/kernel.h>
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15#include <linux/sysdev.h>
16#include <linux/cpu.h>
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17#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/bitops.h>
20#include <linux/debugfs.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/err.h>
51becfd9 24#include <linux/io.h>
d53a0d33 25#include <linux/spinlock.h>
90e7d649 26#include <linux/vmalloc.h>
51becfd9 27#include <asm/sizes.h>
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28#include <asm/system.h>
29#include <asm/uaccess.h>
d7cdc9e8 30#include <asm/pgtable.h>
7bdda620 31#include <asm/page.h>
0c7b1df6 32#include <asm/mmu.h>
eddeeb32 33#include <asm/mmu_context.h>
0c7b1df6 34
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35struct pmb_entry;
36
37struct pmb_entry {
38 unsigned long vpn;
39 unsigned long ppn;
40 unsigned long flags;
41 unsigned long size;
42
43 spinlock_t lock;
44
45 /*
46 * 0 .. NR_PMB_ENTRIES for specific entry selection, or
47 * PMB_NO_ENTRY to search for a free one
48 */
49 int entry;
50
51 /* Adjacent entry link for contiguous multi-entry mappings */
52 struct pmb_entry *link;
53};
54
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55static struct {
56 unsigned long size;
57 int flag;
58} pmb_sizes[] = {
59 { .size = SZ_512M, .flag = PMB_SZ_512M, },
60 { .size = SZ_128M, .flag = PMB_SZ_128M, },
61 { .size = SZ_64M, .flag = PMB_SZ_64M, },
62 { .size = SZ_16M, .flag = PMB_SZ_16M, },
63};
64
d01447b3 65static void pmb_unmap_entry(struct pmb_entry *, int depth);
fc2bdefd 66
d53a0d33 67static DEFINE_RWLOCK(pmb_rwlock);
edd7de80 68static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
51becfd9 69static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
0c7b1df6 70
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71static unsigned int pmb_iomapping_enabled;
72
51becfd9 73static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
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74{
75 return (entry & PMB_E_MASK) << PMB_E_SHIFT;
76}
77
51becfd9 78static __always_inline unsigned long mk_pmb_addr(unsigned int entry)
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79{
80 return mk_pmb_entry(entry) | PMB_ADDR;
81}
82
51becfd9 83static __always_inline unsigned long mk_pmb_data(unsigned int entry)
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84{
85 return mk_pmb_entry(entry) | PMB_DATA;
86}
87
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88static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
89{
90 return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
91}
92
93/*
94 * Ensure that the PMB entries match our cache configuration.
95 *
96 * When we are in 32-bit address extended mode, CCR.CB becomes
97 * invalid, so care must be taken to manually adjust cacheable
98 * translations.
99 */
100static __always_inline unsigned long pmb_cache_flags(void)
101{
102 unsigned long flags = 0;
103
104#if defined(CONFIG_CACHE_OFF)
105 flags |= PMB_WT | PMB_UB;
106#elif defined(CONFIG_CACHE_WRITETHROUGH)
107 flags |= PMB_C | PMB_WT | PMB_UB;
108#elif defined(CONFIG_CACHE_WRITEBACK)
109 flags |= PMB_C;
110#endif
111
112 return flags;
113}
114
115/*
116 * Convert typical pgprot value to the PMB equivalent
117 */
118static inline unsigned long pgprot_to_pmb_flags(pgprot_t prot)
119{
120 unsigned long pmb_flags = 0;
121 u64 flags = pgprot_val(prot);
122
123 if (flags & _PAGE_CACHABLE)
124 pmb_flags |= PMB_C;
125 if (flags & _PAGE_WT)
126 pmb_flags |= PMB_WT | PMB_UB;
127
128 return pmb_flags;
129}
130
a1042aa2 131static inline bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
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132{
133 return (b->vpn == (a->vpn + a->size)) &&
134 (b->ppn == (a->ppn + a->size)) &&
135 (b->flags == a->flags);
136}
137
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138static bool pmb_mapping_exists(unsigned long vaddr, phys_addr_t phys,
139 unsigned long size)
140{
141 int i;
142
143 read_lock(&pmb_rwlock);
144
145 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
146 struct pmb_entry *pmbe, *iter;
147 unsigned long span;
148
149 if (!test_bit(i, pmb_map))
150 continue;
151
152 pmbe = &pmb_entry_list[i];
153
154 /*
155 * See if VPN and PPN are bounded by an existing mapping.
156 */
157 if ((vaddr < pmbe->vpn) || (vaddr >= (pmbe->vpn + pmbe->size)))
158 continue;
159 if ((phys < pmbe->ppn) || (phys >= (pmbe->ppn + pmbe->size)))
160 continue;
161
162 /*
163 * Now see if we're in range of a simple mapping.
164 */
165 if (size <= pmbe->size) {
166 read_unlock(&pmb_rwlock);
167 return true;
168 }
169
170 span = pmbe->size;
171
172 /*
173 * Finally for sizes that involve compound mappings, walk
174 * the chain.
175 */
176 for (iter = pmbe->link; iter; iter = iter->link)
177 span += iter->size;
178
179 /*
180 * Nothing else to do if the range requirements are met.
181 */
182 if (size <= span) {
183 read_unlock(&pmb_rwlock);
184 return true;
185 }
186 }
187
188 read_unlock(&pmb_rwlock);
189 return false;
190}
191
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192static bool pmb_size_valid(unsigned long size)
193{
194 int i;
195
196 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
197 if (pmb_sizes[i].size == size)
198 return true;
199
200 return false;
201}
202
203static inline bool pmb_addr_valid(unsigned long addr, unsigned long size)
204{
205 return (addr >= P1SEG && (addr + size - 1) < P3SEG);
206}
207
208static inline bool pmb_prot_valid(pgprot_t prot)
209{
210 return (pgprot_val(prot) & _PAGE_USER) == 0;
211}
212
213static int pmb_size_to_flags(unsigned long size)
214{
215 int i;
216
217 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
218 if (pmb_sizes[i].size == size)
219 return pmb_sizes[i].flag;
220
221 return 0;
222}
223
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224static int pmb_alloc_entry(void)
225{
d53a0d33 226 int pos;
067784f6 227
51becfd9 228 pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
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229 if (pos >= 0 && pos < NR_PMB_ENTRIES)
230 __set_bit(pos, pmb_map);
231 else
232 pos = -ENOSPC;
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233
234 return pos;
235}
236
8386aebb 237static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
20b5014b 238 unsigned long flags, int entry)
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239{
240 struct pmb_entry *pmbe;
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241 unsigned long irqflags;
242 void *ret = NULL;
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243 int pos;
244
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245 write_lock_irqsave(&pmb_rwlock, irqflags);
246
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247 if (entry == PMB_NO_ENTRY) {
248 pos = pmb_alloc_entry();
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249 if (unlikely(pos < 0)) {
250 ret = ERR_PTR(pos);
251 goto out;
252 }
20b5014b 253 } else {
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254 if (__test_and_set_bit(entry, pmb_map)) {
255 ret = ERR_PTR(-ENOSPC);
256 goto out;
257 }
258
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259 pos = entry;
260 }
0c7b1df6 261
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262 write_unlock_irqrestore(&pmb_rwlock, irqflags);
263
edd7de80 264 pmbe = &pmb_entry_list[pos];
d53a0d33 265
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266 memset(pmbe, 0, sizeof(struct pmb_entry));
267
d53a0d33 268 spin_lock_init(&pmbe->lock);
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269
270 pmbe->vpn = vpn;
271 pmbe->ppn = ppn;
272 pmbe->flags = flags;
067784f6 273 pmbe->entry = pos;
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274
275 return pmbe;
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276
277out:
278 write_unlock_irqrestore(&pmb_rwlock, irqflags);
279 return ret;
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280}
281
8386aebb 282static void pmb_free(struct pmb_entry *pmbe)
0c7b1df6 283{
d53a0d33 284 __clear_bit(pmbe->entry, pmb_map);
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285
286 pmbe->entry = PMB_NO_ENTRY;
287 pmbe->link = NULL;
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288}
289
290/*
51becfd9 291 * Must be run uncached.
0c7b1df6 292 */
d53a0d33 293static void __set_pmb_entry(struct pmb_entry *pmbe)
0c7b1df6 294{
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295 /* Set V-bit */
296 __raw_writel(pmbe->ppn | pmbe->flags | PMB_V, mk_pmb_data(pmbe->entry));
297 __raw_writel(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
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298}
299
d53a0d33 300static void __clear_pmb_entry(struct pmb_entry *pmbe)
0c7b1df6 301{
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302 unsigned long addr, data;
303 unsigned long addr_val, data_val;
0c7b1df6 304
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305 addr = mk_pmb_addr(pmbe->entry);
306 data = mk_pmb_data(pmbe->entry);
0c7b1df6 307
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308 addr_val = __raw_readl(addr);
309 data_val = __raw_readl(data);
0c7b1df6 310
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311 /* Clear V-bit */
312 writel_uncached(addr_val & ~PMB_V, addr);
313 writel_uncached(data_val & ~PMB_V, data);
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314}
315
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316static void set_pmb_entry(struct pmb_entry *pmbe)
317{
318 unsigned long flags;
319
320 spin_lock_irqsave(&pmbe->lock, flags);
321 __set_pmb_entry(pmbe);
322 spin_unlock_irqrestore(&pmbe->lock, flags);
323}
324
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325int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
326 unsigned long size, pgprot_t prot)
d7cdc9e8 327{
fc2bdefd 328 struct pmb_entry *pmbp, *pmbe;
a1042aa2 329 unsigned long flags, pmb_flags;
90e7d649 330 int i, mapped;
90e7d649 331
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332 if (!pmb_addr_valid(vaddr, size))
333 return -EFAULT;
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334 if (pmb_mapping_exists(vaddr, phys, size))
335 return 0;
7bdda620 336
90e7d649 337 pmb_flags = pgprot_to_pmb_flags(prot);
6eb3c735 338 pmbp = NULL;
d7cdc9e8 339
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340 do {
341 for (i = mapped = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
342 if (size < pmb_sizes[i].size)
343 continue;
d7cdc9e8 344
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345 pmbe = pmb_alloc(vaddr, phys, pmb_flags |
346 pmb_sizes[i].flag, PMB_NO_ENTRY);
347 if (IS_ERR(pmbe)) {
348 pmb_unmap_entry(pmbp, mapped);
349 return PTR_ERR(pmbe);
350 }
d53a0d33 351
a1042aa2 352 spin_lock_irqsave(&pmbe->lock, flags);
d7cdc9e8 353
a1042aa2 354 pmbe->size = pmb_sizes[i].size;
d7cdc9e8 355
a1042aa2 356 __set_pmb_entry(pmbe);
d7813bc9 357
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358 phys += pmbe->size;
359 vaddr += pmbe->size;
360 size -= pmbe->size;
d7cdc9e8 361
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362 /*
363 * Link adjacent entries that span multiple PMB
364 * entries for easier tear-down.
365 */
366 if (likely(pmbp)) {
367 spin_lock(&pmbp->lock);
368 pmbp->link = pmbe;
369 spin_unlock(&pmbp->lock);
370 }
a2767cfb 371
a1042aa2 372 pmbp = pmbe;
d53a0d33 373
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374 /*
375 * Instead of trying smaller sizes on every
376 * iteration (even if we succeed in allocating
377 * space), try using pmb_sizes[i].size again.
378 */
379 i--;
380 mapped++;
d7cdc9e8 381
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382 spin_unlock_irqrestore(&pmbe->lock, flags);
383 }
384 } while (size >= SZ_16M);
d7cdc9e8 385
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386 return 0;
387}
388
389void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
390 pgprot_t prot, void *caller)
391{
392 unsigned long orig_addr, vaddr;
393 phys_addr_t offset, last_addr;
394 phys_addr_t align_mask;
395 unsigned long aligned;
396 struct vm_struct *area;
397 int i, ret;
398
399 if (!pmb_iomapping_enabled)
400 return NULL;
401
402 /*
403 * Small mappings need to go through the TLB.
404 */
405 if (size < SZ_16M)
406 return ERR_PTR(-EINVAL);
407 if (!pmb_prot_valid(prot))
408 return ERR_PTR(-EINVAL);
409
410 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
411 if (size >= pmb_sizes[i].size)
412 break;
413
414 last_addr = phys + size;
415 align_mask = ~(pmb_sizes[i].size - 1);
416 offset = phys & ~align_mask;
417 phys &= align_mask;
418 aligned = ALIGN(last_addr, pmb_sizes[i].size) - phys;
419
420 area = __get_vm_area_caller(aligned, VM_IOREMAP, uncached_end,
421 P3SEG, caller);
422 if (!area)
423 return NULL;
424
425 area->phys_addr = phys;
426 orig_addr = vaddr = (unsigned long)area->addr;
427
428 ret = pmb_bolt_mapping(vaddr, phys, size, prot);
a1042aa2 429 if (unlikely(ret != 0))
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430 return ERR_PTR(ret);
431
90e7d649 432 return (void __iomem *)(offset + (char *)orig_addr);
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433}
434
90e7d649 435int pmb_unmap(void __iomem *addr)
d7cdc9e8 436{
d53a0d33 437 struct pmb_entry *pmbe = NULL;
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438 unsigned long vaddr = (unsigned long __force)addr;
439 int i, found = 0;
d7cdc9e8 440
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441 read_lock(&pmb_rwlock);
442
edd7de80 443 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
51becfd9 444 if (test_bit(i, pmb_map)) {
edd7de80 445 pmbe = &pmb_entry_list[i];
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446 if (pmbe->vpn == vaddr) {
447 found = 1;
edd7de80 448 break;
90e7d649 449 }
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450 }
451 }
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452
453 read_unlock(&pmb_rwlock);
454
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455 if (found) {
456 pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
457 return 0;
458 }
d7cdc9e8 459
90e7d649 460 return -EINVAL;
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461}
462
463static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
464{
d7cdc9e8
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465 do {
466 struct pmb_entry *pmblink = pmbe;
467
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468 /*
469 * We may be called before this pmb_entry has been
470 * entered into the PMB table via set_pmb_entry(), but
471 * that's OK because we've allocated a unique slot for
472 * this entry in pmb_alloc() (even if we haven't filled
473 * it yet).
474 *
d53a0d33 475 * Therefore, calling __clear_pmb_entry() is safe as no
067784f6
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476 * other mapping can be using that slot.
477 */
d53a0d33 478 __clear_pmb_entry(pmbe);
fc2bdefd 479
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480 pmbe = pmblink->link;
481
482 pmb_free(pmblink);
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483 } while (pmbe && --depth);
484}
485
486static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
487{
488 unsigned long flags;
d53a0d33 489
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490 if (unlikely(!pmbe))
491 return;
492
493 write_lock_irqsave(&pmb_rwlock, flags);
494 __pmb_unmap_entry(pmbe, depth);
d53a0d33 495 write_unlock_irqrestore(&pmb_rwlock, flags);
d7cdc9e8
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496}
497
d01447b3 498static void __init pmb_notify(void)
20b5014b 499{
d01447b3 500 int i;
20b5014b 501
efd54ea3 502 pr_info("PMB: boot mappings:\n");
20b5014b 503
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504 read_lock(&pmb_rwlock);
505
506 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
507 struct pmb_entry *pmbe;
508
509 if (!test_bit(i, pmb_map))
510 continue;
511
512 pmbe = &pmb_entry_list[i];
513
514 pr_info(" 0x%08lx -> 0x%08lx [ %4ldMB %2scached ]\n",
515 pmbe->vpn >> PAGE_SHIFT, pmbe->ppn >> PAGE_SHIFT,
516 pmbe->size >> 20, (pmbe->flags & PMB_C) ? "" : "un");
517 }
518
519 read_unlock(&pmb_rwlock);
520}
521
522/*
523 * Sync our software copy of the PMB mappings with those in hardware. The
524 * mappings in the hardware PMB were either set up by the bootloader or
525 * very early on by the kernel.
526 */
527static void __init pmb_synchronize(void)
528{
529 struct pmb_entry *pmbp = NULL;
530 int i, j;
531
3d467676 532 /*
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533 * Run through the initial boot mappings, log the established
534 * ones, and blow away anything that falls outside of the valid
535 * PPN range. Specifically, we only care about existing mappings
536 * that impact the cached/uncached sections.
3d467676 537 *
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538 * Note that touching these can be a bit of a minefield; the boot
539 * loader can establish multi-page mappings with the same caching
540 * attributes, so we need to ensure that we aren't modifying a
541 * mapping that we're presently executing from, or may execute
542 * from in the case of straddling page boundaries.
3d467676 543 *
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544 * In the future we will have to tidy up after the boot loader by
545 * jumping between the cached and uncached mappings and tearing
546 * down alternating mappings while executing from the other.
3d467676 547 */
51becfd9 548 for (i = 0; i < NR_PMB_ENTRIES; i++) {
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MF
549 unsigned long addr, data;
550 unsigned long addr_val, data_val;
efd54ea3 551 unsigned long ppn, vpn, flags;
d53a0d33 552 unsigned long irqflags;
d7813bc9 553 unsigned int size;
efd54ea3 554 struct pmb_entry *pmbe;
20b5014b 555
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556 addr = mk_pmb_addr(i);
557 data = mk_pmb_data(i);
20b5014b 558
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559 addr_val = __raw_readl(addr);
560 data_val = __raw_readl(data);
20b5014b 561
3d467676
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562 /*
563 * Skip over any bogus entries
564 */
565 if (!(data_val & PMB_V) || !(addr_val & PMB_V))
566 continue;
20b5014b 567
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568 ppn = data_val & PMB_PFN_MASK;
569 vpn = addr_val & PMB_PFN_MASK;
a0ab3668 570
3d467676
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571 /*
572 * Only preserve in-range mappings.
573 */
efd54ea3 574 if (!pmb_ppn_in_range(ppn)) {
3d467676
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575 /*
576 * Invalidate anything out of bounds.
577 */
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578 writel_uncached(addr_val & ~PMB_V, addr);
579 writel_uncached(data_val & ~PMB_V, data);
efd54ea3 580 continue;
3d467676 581 }
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582
583 /*
584 * Update the caching attributes if necessary
585 */
586 if (data_val & PMB_C) {
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587 data_val &= ~PMB_CACHE_MASK;
588 data_val |= pmb_cache_flags();
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589
590 writel_uncached(data_val, data);
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591 }
592
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593 size = data_val & PMB_SZ_MASK;
594 flags = size | (data_val & PMB_CACHE_MASK);
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595
596 pmbe = pmb_alloc(vpn, ppn, flags, i);
597 if (IS_ERR(pmbe)) {
598 WARN_ON_ONCE(1);
599 continue;
600 }
601
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602 spin_lock_irqsave(&pmbe->lock, irqflags);
603
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604 for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
605 if (pmb_sizes[j].flag == size)
606 pmbe->size = pmb_sizes[j].size;
607
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608 if (pmbp) {
609 spin_lock(&pmbp->lock);
610
611 /*
612 * Compare the previous entry against the current one to
613 * see if the entries span a contiguous mapping. If so,
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614 * setup the entry links accordingly. Compound mappings
615 * are later coalesced.
d53a0d33 616 */
d01447b3 617 if (pmb_can_merge(pmbp, pmbe))
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618 pmbp->link = pmbe;
619
620 spin_unlock(&pmbp->lock);
621 }
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622
623 pmbp = pmbe;
624
d53a0d33 625 spin_unlock_irqrestore(&pmbe->lock, irqflags);
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626 }
627}
d53a0d33 628
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629static void __init pmb_merge(struct pmb_entry *head)
630{
631 unsigned long span, newsize;
632 struct pmb_entry *tail;
633 int i = 1, depth = 0;
634
635 span = newsize = head->size;
efd54ea3 636
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637 tail = head->link;
638 while (tail) {
639 span += tail->size;
640
641 if (pmb_size_valid(span)) {
642 newsize = span;
643 depth = i;
644 }
645
646 /* This is the end of the line.. */
647 if (!tail->link)
648 break;
649
650 tail = tail->link;
651 i++;
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652 }
653
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654 /*
655 * The merged page size must be valid.
656 */
657 if (!pmb_size_valid(newsize))
658 return;
659
660 head->flags &= ~PMB_SZ_MASK;
661 head->flags |= pmb_size_to_flags(newsize);
662
663 head->size = newsize;
664
665 __pmb_unmap_entry(head->link, depth);
666 __set_pmb_entry(head);
a0ab3668 667}
a0ab3668 668
d01447b3 669static void __init pmb_coalesce(void)
a0ab3668 670{
d01447b3
PM
671 unsigned long flags;
672 int i;
673
674 write_lock_irqsave(&pmb_rwlock, flags);
675
676 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
677 struct pmb_entry *pmbe;
678
679 if (!test_bit(i, pmb_map))
680 continue;
681
682 pmbe = &pmb_entry_list[i];
683
684 /*
685 * We're only interested in compound mappings
686 */
687 if (!pmbe->link)
688 continue;
689
690 /*
691 * Nothing to do if it already uses the largest possible
692 * page size.
693 */
694 if (pmbe->size == SZ_512M)
695 continue;
696
697 pmb_merge(pmbe);
698 }
699
700 write_unlock_irqrestore(&pmb_rwlock, flags);
701}
702
703#ifdef CONFIG_UNCACHED_MAPPING
704static void __init pmb_resize(void)
705{
706 int i;
a0ab3668 707
a0ab3668 708 /*
d01447b3
PM
709 * If the uncached mapping was constructed by the kernel, it will
710 * already be a reasonable size.
a0ab3668 711 */
d01447b3
PM
712 if (uncached_size == SZ_16M)
713 return;
714
715 read_lock(&pmb_rwlock);
716
717 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
718 struct pmb_entry *pmbe;
719 unsigned long flags;
720
721 if (!test_bit(i, pmb_map))
722 continue;
723
724 pmbe = &pmb_entry_list[i];
725
726 if (pmbe->vpn != uncached_start)
727 continue;
728
729 /*
730 * Found it, now resize it.
731 */
732 spin_lock_irqsave(&pmbe->lock, flags);
733
734 pmbe->size = SZ_16M;
735 pmbe->flags &= ~PMB_SZ_MASK;
736 pmbe->flags |= pmb_size_to_flags(pmbe->size);
737
738 uncached_resize(pmbe->size);
739
740 __set_pmb_entry(pmbe);
741
742 spin_unlock_irqrestore(&pmbe->lock, flags);
743 }
744
745 read_lock(&pmb_rwlock);
746}
747#endif
748
4cfa8e75
PM
749static int __init early_pmb(char *p)
750{
751 if (!p)
752 return 0;
753
754 if (strstr(p, "iomap"))
755 pmb_iomapping_enabled = 1;
756
757 return 0;
758}
759early_param("pmb", early_pmb);
760
d01447b3
PM
761void __init pmb_init(void)
762{
763 /* Synchronize software state */
764 pmb_synchronize();
765
766 /* Attempt to combine compound mappings */
767 pmb_coalesce();
768
769#ifdef CONFIG_UNCACHED_MAPPING
770 /* Resize initial mappings, if necessary */
771 pmb_resize();
772#endif
773
774 /* Log them */
775 pmb_notify();
3d467676 776
2e450643 777 writel_uncached(0, PMB_IRMCR);
a0ab3668
PM
778
779 /* Flush out the TLB */
efd54ea3 780 __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
2e450643 781 ctrl_barrier();
20b5014b 782}
0c7b1df6 783
2efa53b2
PM
784bool __in_29bit_mode(void)
785{
786 return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
787}
788
0c7b1df6
PM
789static int pmb_seq_show(struct seq_file *file, void *iter)
790{
791 int i;
792
793 seq_printf(file, "V: Valid, C: Cacheable, WT: Write-Through\n"
794 "CB: Copy-Back, B: Buffered, UB: Unbuffered\n");
795 seq_printf(file, "ety vpn ppn size flags\n");
796
797 for (i = 0; i < NR_PMB_ENTRIES; i++) {
798 unsigned long addr, data;
799 unsigned int size;
800 char *sz_str = NULL;
801
9d56dd3b
PM
802 addr = __raw_readl(mk_pmb_addr(i));
803 data = __raw_readl(mk_pmb_data(i));
0c7b1df6
PM
804
805 size = data & PMB_SZ_MASK;
806 sz_str = (size == PMB_SZ_16M) ? " 16MB":
807 (size == PMB_SZ_64M) ? " 64MB":
808 (size == PMB_SZ_128M) ? "128MB":
809 "512MB";
810
811 /* 02: V 0x88 0x08 128MB C CB B */
812 seq_printf(file, "%02d: %c 0x%02lx 0x%02lx %s %c %s %s\n",
813 i, ((addr & PMB_V) && (data & PMB_V)) ? 'V' : ' ',
814 (addr >> 24) & 0xff, (data >> 24) & 0xff,
815 sz_str, (data & PMB_C) ? 'C' : ' ',
816 (data & PMB_WT) ? "WT" : "CB",
817 (data & PMB_UB) ? "UB" : " B");
818 }
819
820 return 0;
821}
822
823static int pmb_debugfs_open(struct inode *inode, struct file *file)
824{
825 return single_open(file, pmb_seq_show, NULL);
826}
827
5dfe4c96 828static const struct file_operations pmb_debugfs_fops = {
0c7b1df6
PM
829 .owner = THIS_MODULE,
830 .open = pmb_debugfs_open,
831 .read = seq_read,
832 .llseek = seq_lseek,
45dabf14 833 .release = single_release,
0c7b1df6
PM
834};
835
836static int __init pmb_debugfs_init(void)
837{
838 struct dentry *dentry;
839
840 dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
b9e393c2 841 sh_debugfs_root, NULL, &pmb_debugfs_fops);
25627c7f
Z
842 if (!dentry)
843 return -ENOMEM;
0c7b1df6
PM
844 if (IS_ERR(dentry))
845 return PTR_ERR(dentry);
846
847 return 0;
848}
0c7b1df6 849postcore_initcall(pmb_debugfs_init);
a83c0b73
FV
850
851#ifdef CONFIG_PM
852static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
853{
854 static pm_message_t prev_state;
edd7de80 855 int i;
a83c0b73
FV
856
857 /* Restore the PMB after a resume from hibernation */
858 if (state.event == PM_EVENT_ON &&
859 prev_state.event == PM_EVENT_FREEZE) {
860 struct pmb_entry *pmbe;
d53a0d33
PM
861
862 read_lock(&pmb_rwlock);
863
edd7de80 864 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
51becfd9 865 if (test_bit(i, pmb_map)) {
edd7de80
MF
866 pmbe = &pmb_entry_list[i];
867 set_pmb_entry(pmbe);
868 }
869 }
d53a0d33
PM
870
871 read_unlock(&pmb_rwlock);
a83c0b73 872 }
d53a0d33 873
a83c0b73 874 prev_state = state;
d53a0d33 875
a83c0b73
FV
876 return 0;
877}
878
879static int pmb_sysdev_resume(struct sys_device *dev)
880{
881 return pmb_sysdev_suspend(dev, PMSG_ON);
882}
883
884static struct sysdev_driver pmb_sysdev_driver = {
885 .suspend = pmb_sysdev_suspend,
886 .resume = pmb_sysdev_resume,
887};
888
889static int __init pmb_sysdev_init(void)
890{
891 return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
892}
a83c0b73
FV
893subsys_initcall(pmb_sysdev_init);
894#endif
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