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f5e706ad SR |
1 | #ifndef __SPARC_IO_H |
2 | #define __SPARC_IO_H | |
3 | ||
4 | #include <linux/kernel.h> | |
f5e706ad SR |
5 | #include <linux/ioport.h> /* struct resource */ |
6 | ||
e1039fb4 | 7 | #define IO_SPACE_LIMIT 0xffffffff |
f5e706ad | 8 | |
e1039fb4 SR |
9 | #define memset_io(d,c,sz) _memset_io(d,c,sz) |
10 | #define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz) | |
11 | #define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz) | |
f5e706ad | 12 | |
e1039fb4 | 13 | #include <asm-generic/io.h> |
f5e706ad | 14 | |
e1039fb4 SR |
15 | static inline void _memset_io(volatile void __iomem *dst, |
16 | int c, __kernel_size_t n) | |
f5e706ad | 17 | { |
e1039fb4 | 18 | volatile void __iomem *d = dst; |
f5e706ad | 19 | |
e1039fb4 SR |
20 | while (n--) { |
21 | writeb(c, d); | |
22 | d++; | |
23 | } | |
f5e706ad SR |
24 | } |
25 | ||
e1039fb4 SR |
26 | static inline void _memcpy_fromio(void *dst, const volatile void __iomem *src, |
27 | __kernel_size_t n) | |
f5e706ad | 28 | { |
e1039fb4 | 29 | char *d = dst; |
f5e706ad | 30 | |
e1039fb4 SR |
31 | while (n--) { |
32 | char tmp = readb(src); | |
33 | *d++ = tmp; | |
34 | src++; | |
35 | } | |
f5e706ad SR |
36 | } |
37 | ||
e1039fb4 SR |
38 | static inline void _memcpy_toio(volatile void __iomem *dst, const void *src, |
39 | __kernel_size_t n) | |
f5e706ad | 40 | { |
e1039fb4 SR |
41 | const char *s = src; |
42 | volatile void __iomem *d = dst; | |
f5e706ad | 43 | |
e1039fb4 SR |
44 | while (n--) { |
45 | char tmp = *s++; | |
46 | writeb(tmp, d); | |
47 | d++; | |
48 | } | |
f5e706ad SR |
49 | } |
50 | ||
f5e706ad SR |
51 | /* |
52 | * SBus accessors. | |
53 | * | |
54 | * SBus has only one, memory mapped, I/O space. | |
55 | * We do not need to flip bytes for SBus of course. | |
56 | */ | |
c3373da9 | 57 | static inline u8 sbus_readb(const volatile void __iomem *addr) |
f5e706ad SR |
58 | { |
59 | return *(__force volatile u8 *)addr; | |
60 | } | |
61 | ||
c3373da9 | 62 | static inline u16 sbus_readw(const volatile void __iomem *addr) |
f5e706ad SR |
63 | { |
64 | return *(__force volatile u16 *)addr; | |
65 | } | |
66 | ||
c3373da9 | 67 | static inline u32 sbus_readl(const volatile void __iomem *addr) |
f5e706ad SR |
68 | { |
69 | return *(__force volatile u32 *)addr; | |
70 | } | |
71 | ||
c3373da9 | 72 | static inline void sbus_writeb(u8 b, volatile void __iomem *addr) |
f5e706ad SR |
73 | { |
74 | *(__force volatile u8 *)addr = b; | |
75 | } | |
76 | ||
c3373da9 | 77 | static inline void sbus_writew(u16 w, volatile void __iomem *addr) |
f5e706ad SR |
78 | { |
79 | *(__force volatile u16 *)addr = w; | |
80 | } | |
81 | ||
c3373da9 | 82 | static inline void sbus_writel(u32 l, volatile void __iomem *addr) |
f5e706ad SR |
83 | { |
84 | *(__force volatile u32 *)addr = l; | |
85 | } | |
86 | ||
c3373da9 SR |
87 | static inline void sbus_memset_io(volatile void __iomem *__dst, int c, |
88 | __kernel_size_t n) | |
f5e706ad SR |
89 | { |
90 | while(n--) { | |
91 | sbus_writeb(c, __dst); | |
92 | __dst++; | |
93 | } | |
94 | } | |
95 | ||
c3373da9 SR |
96 | static inline void sbus_memcpy_fromio(void *dst, |
97 | const volatile void __iomem *src, | |
98 | __kernel_size_t n) | |
f11b478d JH |
99 | { |
100 | char *d = dst; | |
101 | ||
102 | while (n--) { | |
103 | char tmp = sbus_readb(src); | |
104 | *d++ = tmp; | |
105 | src++; | |
106 | } | |
107 | } | |
108 | ||
c3373da9 SR |
109 | static inline void sbus_memcpy_toio(volatile void __iomem *dst, |
110 | const void *src, | |
111 | __kernel_size_t n) | |
f11b478d JH |
112 | { |
113 | const char *s = src; | |
114 | volatile void __iomem *d = dst; | |
115 | ||
116 | while (n--) { | |
117 | char tmp = *s++; | |
118 | sbus_writeb(tmp, d); | |
119 | d++; | |
120 | } | |
121 | } | |
122 | ||
f5e706ad SR |
123 | #ifdef __KERNEL__ |
124 | ||
125 | /* | |
126 | * Bus number may be embedded in the higher bits of the physical address. | |
127 | * This is why we have no bus number argument to ioremap(). | |
128 | */ | |
f05a6865 | 129 | void __iomem *ioremap(unsigned long offset, unsigned long size); |
f5e706ad | 130 | #define ioremap_nocache(X,Y) ioremap((X),(Y)) |
428695b8 | 131 | #define ioremap_wc(X,Y) ioremap((X),(Y)) |
556269c1 | 132 | #define ioremap_wt(X,Y) ioremap((X),(Y)) |
f05a6865 | 133 | void iounmap(volatile void __iomem *addr); |
f5e706ad | 134 | |
f5e706ad | 135 | /* Create a virtual mapping cookie for an IO port range */ |
f05a6865 SR |
136 | void __iomem *ioport_map(unsigned long port, unsigned int nr); |
137 | void ioport_unmap(void __iomem *); | |
f5e706ad SR |
138 | |
139 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | |
140 | struct pci_dev; | |
f05a6865 | 141 | void pci_iounmap(struct pci_dev *dev, void __iomem *); |
f5e706ad | 142 | |
e1039fb4 SR |
143 | |
144 | ||
f5e706ad SR |
145 | /* |
146 | * At the moment, we do not use CMOS_READ anywhere outside of rtc.c, | |
147 | * so rtc_port is static in it. This should not change unless a new | |
148 | * hardware pops up. | |
149 | */ | |
150 | #define RTC_PORT(x) (rtc_port + (x)) | |
151 | #define RTC_ALWAYS_BCD 0 | |
152 | ||
63237eeb DM |
153 | static inline int sbus_can_dma_64bit(void) |
154 | { | |
155 | return 0; /* actually, sparc_cpu_model==sun4d */ | |
156 | } | |
157 | static inline int sbus_can_burst64(void) | |
158 | { | |
159 | return 0; /* actually, sparc_cpu_model==sun4d */ | |
160 | } | |
161 | struct device; | |
f05a6865 | 162 | void sbus_set_sbus64(struct device *, int); |
63237eeb | 163 | |
f5e706ad SR |
164 | #endif |
165 | ||
166 | #define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1 | |
167 | ||
f5e706ad SR |
168 | |
169 | #endif /* !(__SPARC_IO_H) */ |