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1 | #ifndef __SPARC64_SWITCH_TO_64_H |
2 | #define __SPARC64_SWITCH_TO_64_H | |
3 | ||
4 | #include <asm/visasm.h> | |
5 | ||
6 | #define prepare_arch_switch(next) \ | |
7 | do { \ | |
8 | flushw_all(); \ | |
9 | } while (0) | |
10 | ||
11 | /* See what happens when you design the chip correctly? | |
12 | * | |
13 | * We tell gcc we clobber all non-fixed-usage registers except | |
14 | * for l0/l1. It will use one for 'next' and the other to hold | |
15 | * the output value of 'last'. 'next' is not referenced again | |
16 | * past the invocation of switch_to in the scheduler, so we need | |
17 | * not preserve it's value. Hairy, but it lets us remove 2 loads | |
18 | * and 2 stores in this critical code path. -DaveM | |
19 | */ | |
20 | #define switch_to(prev, next, last) \ | |
21 | do { flush_tlb_pending(); \ | |
22 | save_and_clear_fpu(); \ | |
23 | /* If you are tempted to conditionalize the following */ \ | |
24 | /* so that ASI is only written if it changes, think again. */ \ | |
25 | __asm__ __volatile__("wr %%g0, %0, %%asi" \ | |
dff933da | 26 | : : "r" (task_thread_info(next)->current_ds));\ |
d550bbd4 DH |
27 | trap_block[current_thread_info()->cpu].thread = \ |
28 | task_thread_info(next); \ | |
29 | __asm__ __volatile__( \ | |
30 | "mov %%g4, %%g7\n\t" \ | |
31 | "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \ | |
32 | "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ | |
33 | "rdpr %%wstate, %%o5\n\t" \ | |
34 | "stx %%o6, [%%g6 + %6]\n\t" \ | |
35 | "stb %%o5, [%%g6 + %5]\n\t" \ | |
36 | "rdpr %%cwp, %%o5\n\t" \ | |
37 | "stb %%o5, [%%g6 + %8]\n\t" \ | |
38 | "wrpr %%g0, 15, %%pil\n\t" \ | |
39 | "mov %4, %%g6\n\t" \ | |
40 | "ldub [%4 + %8], %%g1\n\t" \ | |
41 | "wrpr %%g1, %%cwp\n\t" \ | |
42 | "ldx [%%g6 + %6], %%o6\n\t" \ | |
43 | "ldub [%%g6 + %5], %%o5\n\t" \ | |
44 | "ldub [%%g6 + %7], %%o7\n\t" \ | |
45 | "wrpr %%o5, 0x0, %%wstate\n\t" \ | |
46 | "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ | |
47 | "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ | |
48 | "ldx [%%g6 + %9], %%g4\n\t" \ | |
49 | "wrpr %%g0, 14, %%pil\n\t" \ | |
50 | "brz,pt %%o7, switch_to_pc\n\t" \ | |
51 | " mov %%g7, %0\n\t" \ | |
52 | "sethi %%hi(ret_from_syscall), %%g1\n\t" \ | |
53 | "jmpl %%g1 + %%lo(ret_from_syscall), %%g0\n\t" \ | |
54 | " nop\n\t" \ | |
55 | ".globl switch_to_pc\n\t" \ | |
56 | "switch_to_pc:\n\t" \ | |
57 | : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \ | |
58 | "=r" (__local_per_cpu_offset) \ | |
59 | : "0" (task_thread_info(next)), \ | |
60 | "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \ | |
61 | "i" (TI_CWP), "i" (TI_TASK) \ | |
62 | : "cc", \ | |
63 | "g1", "g2", "g3", "g7", \ | |
64 | "l1", "l2", "l3", "l4", "l5", "l6", "l7", \ | |
65 | "i0", "i1", "i2", "i3", "i4", "i5", \ | |
66 | "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \ | |
67 | } while(0) | |
68 | ||
69 | extern void synchronize_user_stack(void); | |
70 | extern void fault_in_user_windows(void); | |
71 | ||
72 | #endif /* __SPARC64_SWITCH_TO_64_H */ |