[deliverable/linux.git] / arch / sparc / kernel / cpu.c

/* cpu.c: Dinky routines to look for the kind of Sparc cpu
 *        we are on.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/threads.h>

#include <asm/spitfire.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/head.h>
#include <asm/psr.h>
#include <asm/mbus.h>
#include <asm/cpudata.h>

#include "kernel.h"

DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
EXPORT_PER_CPU_SYMBOL(__cpu_data);

struct cpu_info {
	int psr_vers;
	const char *name;
	const char *pmu_name;
};

struct fpu_info {
	int fp_vers;
	const char *name;
};

#define NOCPU 8
#define NOFPU 8

struct manufacturer_info {
	int psr_impl;
	struct cpu_info cpu_info[NOCPU];
	struct fpu_info fpu_info[NOFPU];
};

#define CPU(ver, _name) \
{ .psr_vers = ver, .name = _name }

#define CPU_PMU(ver, _name, _pmu_name)	\
{ .psr_vers = ver, .name = _name, .pmu_name = _pmu_name }

#define FPU(ver, _name) \
{ .fp_vers = ver, .name = _name }

static const struct manufacturer_info __initconst manufacturer_info[] = {
{
	0,
	/* Sun4/100, 4/200, SLC */
	.cpu_info = {
		CPU(0, "Fujitsu  MB86900/1A or LSI L64831 SparcKIT-40"),
		/* borned STP1012PGA */
		CPU(4,  "Fujitsu  MB86904"),
		CPU(5, "Fujitsu TurboSparc MB86907"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"),
		FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"),
		FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"),
		/* SparcStation SLC, SparcStation1 */
		FPU(3, "Weitek WTL3170/2"),
		/* SPARCstation-5 */
		FPU(4, "Lsi Logic/Meiko L64804 or compatible"),
		FPU(-1, NULL)
	}
},{
	1,
	.cpu_info = {
		/* SparcStation2, SparcServer 490 & 690 */
		CPU(0, "LSI Logic Corporation - L64811"),
		/* SparcStation2 */
		CPU(1, "Cypress/ROSS CY7C601"),
		/* Embedded controller */
		CPU(3, "Cypress/ROSS CY7C611"),
		/* Ross Technologies HyperSparc */
		CPU(0xf, "ROSS HyperSparc RT620"),
		CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(0, "ROSS HyperSparc combined IU/FPU"),
		FPU(1, "Lsi Logic L64814"),
		FPU(2, "Texas Instruments TMS390-C602A"),
		FPU(3, "Cypress CY7C602 FPU"),
		FPU(-1, NULL)
	}
},{
	2,
	.cpu_info = {
		/* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */
		/* Someone please write the code to support this beast! ;) */
		CPU(0, "Bipolar Integrated Technology - B5010"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(-1, NULL)
	}
},{
	3,
	.cpu_info = {
		CPU(0, "LSI Logic Corporation - unknown-type"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(-1, NULL)
	}
},{
	4,
	.cpu_info = {
		CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"),
		/* SparcClassic  --  borned STP1010TAB-50*/
		CPU(1, "Texas Instruments, Inc. - MicroSparc"),
		CPU(2, "Texas Instruments, Inc. - MicroSparc II"),
		CPU(3, "Texas Instruments, Inc. - SuperSparc 51"),
		CPU(4, "Texas Instruments, Inc. - SuperSparc 61"),
		CPU(5, "Texas Instruments, Inc. - unknown"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		/* SuperSparc 50 module */
		FPU(0, "SuperSparc on-chip FPU"),
		/* SparcClassic */
		FPU(4, "TI MicroSparc on chip FPU"),
		FPU(-1, NULL)
	}
},{
	5,
	.cpu_info = {
		CPU(0, "Matsushita - MN10501"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(0, "Matsushita MN10501"),
		FPU(-1, NULL)
	}
},{
	6,
	.cpu_info = {
		CPU(0, "Philips Corporation - unknown"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(-1, NULL)
	}
},{
	7,
	.cpu_info = {
		CPU(0, "Harvest VLSI Design Center, Inc. - unknown"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(-1, NULL)
	}
},{
	8,
	.cpu_info = {
		CPU(0, "Systems and Processes Engineering Corporation (SPEC)"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(-1, NULL)
	}
},{
	9,
	.cpu_info = {
		/* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */
		CPU(0, "Fujitsu or Weitek Power-UP"),
		CPU(1, "Fujitsu or Weitek Power-UP"),
		CPU(2, "Fujitsu or Weitek Power-UP"),
		CPU(3, "Fujitsu or Weitek Power-UP"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(3, "Fujitsu or Weitek on-chip FPU"),
		FPU(-1, NULL)
	}
},{
	0xF,		/* Aeroflex Gaisler */
	.cpu_info = {
		CPU(3, "LEON"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(2, "GRFPU"),
		FPU(3, "GRFPU-Lite"),
		FPU(-1, NULL)
	}
},{
	0x17,
	.cpu_info = {
		CPU_PMU(0x10, "TI UltraSparc I   (SpitFire)", "ultra12"),
		CPU_PMU(0x11, "TI UltraSparc II  (BlackBird)", "ultra12"),
		CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"),
		CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(0x10, "UltraSparc I integrated FPU"),
		FPU(0x11, "UltraSparc II integrated FPU"),
		FPU(0x12, "UltraSparc IIi integrated FPU"),
		FPU(0x13, "UltraSparc IIe integrated FPU"),
		FPU(-1, NULL)
	}
},{
	0x22,
	.cpu_info = {
		CPU_PMU(0x10, "TI UltraSparc I   (SpitFire)", "ultra12"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(0x10, "UltraSparc I integrated FPU"),
		FPU(-1, NULL)
	}
},{
	0x3e,
	.cpu_info = {
		CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"),
		CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"),
		CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"),
		CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"),
		CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"),
		CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"),
		CPU(-1, NULL)
	},
	.fpu_info = {
		FPU(0x14, "UltraSparc III integrated FPU"),
		FPU(0x15, "UltraSparc III+ integrated FPU"),
		FPU(0x16, "UltraSparc IIIi integrated FPU"),
		FPU(0x18, "UltraSparc IV integrated FPU"),
		FPU(0x19, "UltraSparc IV+ integrated FPU"),
		FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
		FPU(-1, NULL)
	}
}};

/* In order to get the fpu type correct, you need to take the IDPROM's
 * machine type value into consideration too.  I will fix this.
 */

const char *sparc_cpu_type;
const char *sparc_fpu_type;
const char *sparc_pmu_type;

unsigned int fsr_storage;

static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
{
	const struct manufacturer_info *manuf;
	int i;

	sparc_cpu_type = NULL;
	sparc_fpu_type = NULL;
	sparc_pmu_type = NULL;
	manuf = NULL;

	for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++)
	{
		if (psr_impl == manufacturer_info[i].psr_impl) {
			manuf = &manufacturer_info[i];
			break;
		}
	}
	if (manuf != NULL)
	{
		const struct cpu_info *cpu;
		const struct fpu_info *fpu;

		cpu = &manuf->cpu_info[0];
		while (cpu->psr_vers != -1)
		{
			if (cpu->psr_vers == psr_vers) {
				sparc_cpu_type = cpu->name;
				sparc_pmu_type = cpu->pmu_name;
				sparc_fpu_type = "No FPU";
				break;
			}
			cpu++;
		}
		fpu =  &manuf->fpu_info[0];
		while (fpu->fp_vers != -1)
		{
			if (fpu->fp_vers == fpu_vers) {
				sparc_fpu_type = fpu->name;
				break;
			}
			fpu++;
		}
	}
	if (sparc_cpu_type == NULL)
	{
		printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
		       psr_impl, psr_vers);
		sparc_cpu_type = "Unknown CPU";
	}
	if (sparc_fpu_type == NULL)
	{
		printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
		       psr_impl, fpu_vers);
		sparc_fpu_type = "Unknown FPU";
	}
	if (sparc_pmu_type == NULL)
		sparc_pmu_type = "Unknown PMU";
}

#ifdef CONFIG_SPARC32
void __cpuinit cpu_probe(void)
{
	int psr_impl, psr_vers, fpu_vers;
	int psr;

	psr_impl = ((get_psr() >> 28) & 0xf);
	psr_vers = ((get_psr() >> 24) & 0xf);

	psr = get_psr();
	put_psr(psr | PSR_EF);
#ifdef CONFIG_SPARC_LEON
	fpu_vers = 7;
#else
	fpu_vers = ((get_fsr() >> 17) & 0x7);
#endif

	put_psr(psr);

	set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
}
#else
static void __init sun4v_cpu_probe(void)
{
	switch (sun4v_chip_type) {
	case SUN4V_CHIP_NIAGARA1:
		sparc_cpu_type = "UltraSparc T1 (Niagara)";
		sparc_fpu_type = "UltraSparc T1 integrated FPU";
		sparc_pmu_type = "niagara";
		break;

	case SUN4V_CHIP_NIAGARA2:
		sparc_cpu_type = "UltraSparc T2 (Niagara2)";
		sparc_fpu_type = "UltraSparc T2 integrated FPU";
		sparc_pmu_type = "niagara2";
		break;

	default:
		printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
		       prom_cpu_compatible);
		sparc_cpu_type = "Unknown SUN4V CPU";
		sparc_fpu_type = "Unknown SUN4V FPU";
		break;
	}
}

static int __init cpu_type_probe(void)
{
	if (tlb_type == hypervisor) {
		sun4v_cpu_probe();
	} else {
		unsigned long ver;
		int manuf, impl;

		__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));

		manuf = ((ver >> 48) & 0xffff);
		impl = ((ver >> 32) & 0xffff);
		set_cpu_and_fpu(manuf, impl, impl);
	}
	return 0;
}

arch_initcall(cpu_type_probe);
#endif
Commit	Line	Data
1da177e4 LT	1	/* cpu.c: Dinky routines to look for the kind of Sparc cpu
	2	* we are on.
	3	*
	4	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	5	*/
	6
1da177e4	7	#include <linux/kernel.h>
6943f3da	8	#include <linux/module.h>
1da177e4 LT	9	#include <linux/init.h>
	10	#include <linux/smp.h>
	11	#include <linux/threads.h>
d34dd829 SR	12
d34dd829 SR	13	#include <asm/spitfire.h>
1da177e4 LT	14	#include <asm/oplib.h>
	15	#include <asm/page.h>
	16	#include <asm/head.h>
	17	#include <asm/psr.h>
	18	#include <asm/mbus.h>
	19	#include <asm/cpudata.h>
	20
53ae3419 SR	21	#include "kernel.h"
53ae3419 SR	22
1da177e4	23	DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
6943f3da	24	EXPORT_PER_CPU_SYMBOL(__cpu_data);
1da177e4	25
2bf05fa0	26	struct cpu_info {
8a563f01	27	int psr_vers;
2bf05fa0	28	const char *name;
c3cf5e8c	29	const char *pmu_name;
1da177e4 LT	30	};
1da177e4 LT	31
2bf05fa0	32	struct fpu_info {
8a563f01	33	int fp_vers;
2bf05fa0	34	const char *name;
1da177e4 LT	35	};
1da177e4 LT	36
2bf05fa0 SR	37	#define NOCPU 8
	38	#define NOFPU 8
	39
	40	struct manufacturer_info {
	41	int psr_impl;
	42	struct cpu_info cpu_info[NOCPU];
	43	struct fpu_info fpu_info[NOFPU];
1da177e4 LT	44	};
1da177e4 LT	45
2bf05fa0 SR	46	#define CPU(ver, _name) \
	47	{ .psr_vers = ver, .name = _name }
	48
c3cf5e8c DM	49	#define CPU_PMU(ver, _name, _pmu_name) \
	50	{ .psr_vers = ver, .name = _name, .pmu_name = _pmu_name }
	51
2bf05fa0 SR	52	#define FPU(ver, _name) \
2bf05fa0 SR	53	{ .fp_vers = ver, .name = _name }
1da177e4	54
2bf05fa0 SR	55	static const struct manufacturer_info __initconst manufacturer_info[] = {
	56	{
	57	0,
8a563f01	58	/* Sun4/100, 4/200, SLC */
2bf05fa0 SR	59	.cpu_info = {
	60	CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
	61	/* borned STP1012PGA */
	62	CPU(4, "Fujitsu MB86904"),
	63	CPU(5, "Fujitsu TurboSparc MB86907"),
	64	CPU(-1, NULL)
	65	},
	66	.fpu_info = {
	67	FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"),
	68	FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"),
	69	FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"),
	70	/* SparcStation SLC, SparcStation1 */
	71	FPU(3, "Weitek WTL3170/2"),
	72	/* SPARCstation-5 */
	73	FPU(4, "Lsi Logic/Meiko L64804 or compatible"),
	74	FPU(-1, NULL)
	75	}
	76	},{
	77	1,
	78	.cpu_info = {
	79	/* SparcStation2, SparcServer 490 & 690 */
	80	CPU(0, "LSI Logic Corporation - L64811"),
	81	/* SparcStation2 */
	82	CPU(1, "Cypress/ROSS CY7C601"),
	83	/* Embedded controller */
	84	CPU(3, "Cypress/ROSS CY7C611"),
	85	/* Ross Technologies HyperSparc */
	86	CPU(0xf, "ROSS HyperSparc RT620"),
	87	CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
	88	CPU(-1, NULL)
	89	},
	90	.fpu_info = {
	91	FPU(0, "ROSS HyperSparc combined IU/FPU"),
	92	FPU(1, "Lsi Logic L64814"),
	93	FPU(2, "Texas Instruments TMS390-C602A"),
	94	FPU(3, "Cypress CY7C602 FPU"),
	95	FPU(-1, NULL)
	96	}
	97	},{
	98	2,
	99	.cpu_info = {
	100	/* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */
	101	/* Someone please write the code to support this beast! ;) */
	102	CPU(0, "Bipolar Integrated Technology - B5010"),
	103	CPU(-1, NULL)
	104	},
	105	.fpu_info = {
	106	FPU(-1, NULL)
	107	}
	108	},{
	109	3,
	110	.cpu_info = {
	111	CPU(0, "LSI Logic Corporation - unknown-type"),
	112	CPU(-1, NULL)
	113	},
	114	.fpu_info = {
	115	FPU(-1, NULL)
	116	}
	117	},{
	118	4,
	119	.cpu_info = {
	120	CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"),
	121	/* SparcClassic -- borned STP1010TAB-50*/
	122	CPU(1, "Texas Instruments, Inc. - MicroSparc"),
123	CPU(2, "Texas Instruments, Inc. - MicroSparc II"),
124	CPU(3, "Texas Instruments, Inc. - SuperSparc 51"),
125	CPU(4, "Texas Instruments, Inc. - SuperSparc 61"),
126	CPU(5, "Texas Instruments, Inc. - unknown"),
127	CPU(-1, NULL)
128	},
129	.fpu_info = {
130	/* SuperSparc 50 module */
131	FPU(0, "SuperSparc on-chip FPU"),
132	/* SparcClassic */
133	FPU(4, "TI MicroSparc on chip FPU"),
134	FPU(-1, NULL)
135	}
136	},{
137	5,
138	.cpu_info = {
139	CPU(0, "Matsushita - MN10501"),
140	CPU(-1, NULL)
141	},
142	.fpu_info = {
143	FPU(0, "Matsushita MN10501"),
144	FPU(-1, NULL)
145	}
146	},{
147	6,
148	.cpu_info = {
149	CPU(0, "Philips Corporation - unknown"),
150	CPU(-1, NULL)
151	},
152	.fpu_info = {
153	FPU(-1, NULL)
154	}
155	},{
156	7,
157	.cpu_info = {
158	CPU(0, "Harvest VLSI Design Center, Inc. - unknown"),
159	CPU(-1, NULL)
160	},
161	.fpu_info = {
162	FPU(-1, NULL)
163	}
164	},{
165	8,
166	.cpu_info = {
167	CPU(0, "Systems and Processes Engineering Corporation (SPEC)"),
168	CPU(-1, NULL)
169	},
170	.fpu_info = {
171	FPU(-1, NULL)
172	}
173	},{
174	9,
175	.cpu_info = {
176	/* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */
177	CPU(0, "Fujitsu or Weitek Power-UP"),
178	CPU(1, "Fujitsu or Weitek Power-UP"),
179	CPU(2, "Fujitsu or Weitek Power-UP"),
180	CPU(3, "Fujitsu or Weitek Power-UP"),
181	CPU(-1, NULL)
182	},
183	.fpu_info = {
184	FPU(3, "Fujitsu or Weitek on-chip FPU"),
185	FPU(-1, NULL)
186	}
3560f788 KG	187	},{
	188	0xF, /* Aeroflex Gaisler */
	189	.cpu_info = {
	190	CPU(3, "LEON"),
	191	CPU(-1, NULL)
	192	},
	193	.fpu_info = {
	194	FPU(2, "GRFPU"),
	195	FPU(3, "GRFPU-Lite"),
	196	FPU(-1, NULL)
	197	}
d34dd829 SR	198	},{
	199	0x17,
	200	.cpu_info = {
c3cf5e8c DM	201	CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
	202	CPU_PMU(0x11, "TI UltraSparc II (BlackBird)", "ultra12"),
	203	CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"),
	204	CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"),
d34dd829 SR	205	CPU(-1, NULL)
	206	},
	207	.fpu_info = {
	208	FPU(0x10, "UltraSparc I integrated FPU"),
	209	FPU(0x11, "UltraSparc II integrated FPU"),
	210	FPU(0x12, "UltraSparc IIi integrated FPU"),
	211	FPU(0x13, "UltraSparc IIe integrated FPU"),
	212	FPU(-1, NULL)
	213	}
	214	},{
	215	0x22,
	216	.cpu_info = {
c3cf5e8c	217	CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
d34dd829 SR	218	CPU(-1, NULL)
	219	},
	220	.fpu_info = {
	221	FPU(0x10, "UltraSparc I integrated FPU"),
	222	FPU(-1, NULL)
	223	}
	224	},{
	225	0x3e,
	226	.cpu_info = {
c3cf5e8c DM	227	CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"),
	228	CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"),
	229	CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"),
	230	CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"),
	231	CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"),
	232	CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"),
d34dd829 SR	233	CPU(-1, NULL)
	234	},
	235	.fpu_info = {
	236	FPU(0x14, "UltraSparc III integrated FPU"),
	237	FPU(0x15, "UltraSparc III+ integrated FPU"),
	238	FPU(0x16, "UltraSparc IIIi integrated FPU"),
	239	FPU(0x18, "UltraSparc IV integrated FPU"),
	240	FPU(0x19, "UltraSparc IV+ integrated FPU"),
	241	FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
	242	FPU(-1, NULL)
	243	}
2bf05fa0	244	}};
1da177e4	245
2bf05fa0 SR	246	/* In order to get the fpu type correct, you need to take the IDPROM's
	247	* machine type value into consideration too. I will fix this.
	248	*/
1da177e4	249
53ae3419 SR	250	const char *sparc_cpu_type;
53ae3419 SR	251	const char *sparc_fpu_type;
c3cf5e8c	252	const char *sparc_pmu_type;
1da177e4 LT	253
	254	unsigned int fsr_storage;
	255
2bf05fa0	256	static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
1da177e4	257	{
c275ce44 SR	258	const struct manufacturer_info *manuf;
	259	int i;
	260
2bf05fa0 SR	261	sparc_cpu_type = NULL;
2bf05fa0 SR	262	sparc_fpu_type = NULL;
c3cf5e8c	263	sparc_pmu_type = NULL;
c275ce44 SR	264	manuf = NULL;
	265
	266	for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++)
	267	{
	268	if (psr_impl == manufacturer_info[i].psr_impl) {
	269	manuf = &manufacturer_info[i];
	270	break;
	271	}
	272	}
	273	if (manuf != NULL)
2bf05fa0 SR	274	{
	275	const struct cpu_info *cpu;
	276	const struct fpu_info *fpu;
	277
c275ce44	278	cpu = &manuf->cpu_info[0];
2bf05fa0 SR	279	while (cpu->psr_vers != -1)
	280	{
	281	if (cpu->psr_vers == psr_vers) {
	282	sparc_cpu_type = cpu->name;
c3cf5e8c	283	sparc_pmu_type = cpu->pmu_name;
2bf05fa0 SR	284	sparc_fpu_type = "No FPU";
	285	break;
	286	}
	287	cpu++;
	288	}
c275ce44	289	fpu = &manuf->fpu_info[0];
2bf05fa0 SR	290	while (fpu->fp_vers != -1)
	291	{
	292	if (fpu->fp_vers == fpu_vers) {
	293	sparc_fpu_type = fpu->name;
1da177e4 LT	294	break;
1da177e4 LT	295	}
2bf05fa0 SR	296	fpu++;
2bf05fa0 SR	297	}
1da177e4	298	}
2bf05fa0	299	if (sparc_cpu_type == NULL)
6c6bd8b6 SR	300	{
6c6bd8b6 SR	301	printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
8a563f01	302	psr_impl, psr_vers);
6c6bd8b6 SR	303	sparc_cpu_type = "Unknown CPU";
6c6bd8b6 SR	304	}
2bf05fa0 SR	305	if (sparc_fpu_type == NULL)
2bf05fa0 SR	306	{
6c6bd8b6	307	printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
8a563f01	308	psr_impl, fpu_vers);
6c6bd8b6	309	sparc_fpu_type = "Unknown FPU";
1da177e4	310	}
c3cf5e8c DM	311	if (sparc_pmu_type == NULL)
c3cf5e8c DM	312	sparc_pmu_type = "Unknown PMU";
1da177e4	313	}
2bf05fa0	314
d34dd829	315	#ifdef CONFIG_SPARC32
2bf05fa0 SR	316	void __cpuinit cpu_probe(void)
	317	{
	318	int psr_impl, psr_vers, fpu_vers;
	319	int psr;
	320
	321	psr_impl = ((get_psr() >> 28) & 0xf);
	322	psr_vers = ((get_psr() >> 24) & 0xf);
	323
	324	psr = get_psr();
	325	put_psr(psr \| PSR_EF);
0fd7ef1f KE	326	#ifdef CONFIG_SPARC_LEON
	327	fpu_vers = 7;
	328	#else
2bf05fa0	329	fpu_vers = ((get_fsr() >> 17) & 0x7);
0fd7ef1f KE	330	#endif
0fd7ef1f KE	331
2bf05fa0 SR	332	put_psr(psr);
	333
	334	set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
	335	}
d34dd829 SR	336	#else
	337	static void __init sun4v_cpu_probe(void)
	338	{
	339	switch (sun4v_chip_type) {
	340	case SUN4V_CHIP_NIAGARA1:
	341	sparc_cpu_type = "UltraSparc T1 (Niagara)";
	342	sparc_fpu_type = "UltraSparc T1 integrated FPU";
c3cf5e8c	343	sparc_pmu_type = "niagara";
d34dd829 SR	344	break;
	345
	346	case SUN4V_CHIP_NIAGARA2:
	347	sparc_cpu_type = "UltraSparc T2 (Niagara2)";
	348	sparc_fpu_type = "UltraSparc T2 integrated FPU";
c3cf5e8c	349	sparc_pmu_type = "niagara2";
d34dd829 SR	350	break;
	351
	352	default:
	353	printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
	354	prom_cpu_compatible);
	355	sparc_cpu_type = "Unknown SUN4V CPU";
	356	sparc_fpu_type = "Unknown SUN4V FPU";
	357	break;
	358	}
	359	}
	360
	361	static int __init cpu_type_probe(void)
	362	{
	363	if (tlb_type == hypervisor) {
	364	sun4v_cpu_probe();
	365	} else {
	366	unsigned long ver;
	367	int manuf, impl;
	368
	369	__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
	370
	371	manuf = ((ver >> 48) & 0xffff);
	372	impl = ((ver >> 32) & 0xffff);
	373	set_cpu_and_fpu(manuf, impl, impl);
	374	}
	375	return 0;
	376	}
	377
	378	arch_initcall(cpu_type_probe);
	379	#endif