[deliverable/linux.git] / arch / sparc / kernel / etrap_64.S

/*
 * etrap.S: Preparing for entry into the kernel on Sparc V9.
 *
 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/page.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/processor.h>
#include <asm/mmu.h>

#define		TASK_REGOFF		(THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
#define		ETRAP_PSTATE1		(PSTATE_TSO | PSTATE_PRIV)
#define		ETRAP_PSTATE2		\
		(PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)

/*
 * On entry, %g7 is return address - 0x4.
 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
 */

		.text		
		.align	64
		.globl	etrap_syscall, etrap, etrap_irq, etraptl1
etrap:		rdpr	%pil, %g2
etrap_irq:	clr	%g3
etrap_syscall:	TRAP_LOAD_THREAD_REG(%g6, %g1)
		rdpr	%tstate, %g1
		or	%g1, %g3, %g1
		sllx	%g2, 20, %g3
		andcc	%g1, TSTATE_PRIV, %g0
		or	%g1, %g3, %g1
		bne,pn	%xcc, 1f
		 sub	%sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
		wrpr	%g0, 7, %cleanwin

		sethi	%hi(TASK_REGOFF), %g2
		sethi	%hi(TSTATE_PEF), %g3
		or	%g2, %lo(TASK_REGOFF), %g2
		and	%g1, %g3, %g3
		brnz,pn	%g3, 1f
		 add	%g6, %g2, %g2
		wr	%g0, 0, %fprs
1:		rdpr	%tpc, %g3

		stx	%g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
		rdpr	%tnpc, %g1
		stx	%g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
		rd	%y, %g3
		stx	%g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
		rdpr	%tt, %g1
		st	%g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
		sethi	%hi(PT_REGS_MAGIC), %g3
		or	%g3, %g1, %g1
		st	%g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]

		rdpr	%cansave, %g1
		brnz,pt %g1, etrap_save
		 nop

		rdpr	%cwp, %g1
		add	%g1, 2, %g1
		wrpr	%g1, %cwp
		be,pt	%xcc, etrap_user_spill
		 mov	ASI_AIUP, %g3

		rdpr	%otherwin, %g3
		brz	%g3, etrap_kernel_spill
		 mov	ASI_AIUS, %g3

etrap_user_spill:

		wr	%g3, 0x0, %asi
		ldx	[%g6 + TI_FLAGS], %g3
		and	%g3, _TIF_32BIT, %g3
		brnz,pt	%g3, etrap_user_spill_32bit
		 nop
		ba,a,pt	%xcc, etrap_user_spill_64bit

etrap_save:	save	%g2, -STACK_BIAS, %sp
		mov	%g6, %l6

		bne,pn	%xcc, 3f
		 mov	PRIMARY_CONTEXT, %l4
		rdpr	%canrestore, %g3
		rdpr	%wstate, %g2
		wrpr	%g0, 0, %canrestore
		sll	%g2, 3, %g2

		/* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR.  */
		mov	1, %l5
		sth	%l5, [%l6 + TI_SYS_NOERROR]

		wrpr	%g3, 0, %otherwin
		wrpr	%g2, 0, %wstate
		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g3

661:		stxa	%g3, [%l4] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g3, [%l4] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %l4
		flush	%l4
		mov	ASI_AIUS, %l7
2:		mov	%g4, %l4
		mov	%g5, %l5
		add	%g7, 4, %l2

		/* Go to trap time globals so we can save them.  */
661:		wrpr	%g0, ETRAP_PSTATE1, %pstate
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		SET_GL(0)
		.previous

		stx	%g1, [%sp + PTREGS_OFF + PT_V9_G1]
		stx	%g2, [%sp + PTREGS_OFF + PT_V9_G2]
		sllx	%l7, 24, %l7
		stx	%g3, [%sp + PTREGS_OFF + PT_V9_G3]
		rdpr	%cwp, %l0
		stx	%g4, [%sp + PTREGS_OFF + PT_V9_G4]
		stx	%g5, [%sp + PTREGS_OFF + PT_V9_G5]
		stx	%g6, [%sp + PTREGS_OFF + PT_V9_G6]
		stx	%g7, [%sp + PTREGS_OFF + PT_V9_G7]
		or	%l7, %l0, %l7
		sethi	%hi(TSTATE_TSO | TSTATE_PEF), %l0
		or	%l7, %l0, %l7
		wrpr	%l2, %tnpc
		wrpr	%l7, (TSTATE_PRIV | TSTATE_IE), %tstate
		stx	%i0, [%sp + PTREGS_OFF + PT_V9_I0]
		stx	%i1, [%sp + PTREGS_OFF + PT_V9_I1]
		stx	%i2, [%sp + PTREGS_OFF + PT_V9_I2]
		stx	%i3, [%sp + PTREGS_OFF + PT_V9_I3]
		stx	%i4, [%sp + PTREGS_OFF + PT_V9_I4]
		stx	%i5, [%sp + PTREGS_OFF + PT_V9_I5]
		stx	%i6, [%sp + PTREGS_OFF + PT_V9_I6]
		mov	%l6, %g6
		stx	%i7, [%sp + PTREGS_OFF + PT_V9_I7]
		LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
		ldx	[%g6 + TI_TASK], %g4
		done

3:		mov	ASI_P, %l7
		ldub	[%l6 + TI_FPDEPTH], %l5
		add	%l6, TI_FPSAVED + 1, %l4
		srl	%l5, 1, %l3
		add	%l5, 2, %l5

		/* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR.  */
		sth	%l5, [%l6 + TI_SYS_NOERROR]
		ba,pt	%xcc, 2b
		 stb	%g0, [%l4 + %l3]
		nop

etraptl1:	/* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
		 * We place this right after pt_regs on the trap stack.
		 * The layout is:
		 *	0x00	TL1's TSTATE
		 *	0x08	TL1's TPC
		 *	0x10	TL1's TNPC
		 *	0x18	TL1's TT
		 *	 ...
		 *	0x58	TL4's TT
		 *	0x60	TL
		 */
		TRAP_LOAD_THREAD_REG(%g6, %g1)
		sub	%sp, ((4 * 8) * 4) + 8, %g2
		rdpr	%tl, %g1

		wrpr	%g0, 1, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x00]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x08]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x10]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x18]

		wrpr	%g0, 2, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x20]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x28]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x30]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x38]

		sethi	%hi(is_sun4v), %g3
		lduw	[%g3 + %lo(is_sun4v)], %g3
		brnz,pn	%g3, finish_tl1_capture
		 nop

		wrpr	%g0, 3, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x40]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x48]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x50]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x58]

		wrpr	%g0, 4, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x60]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x68]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x70]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x78]

		stx	%g1, [%g2 + STACK_BIAS + 0x80]

finish_tl1_capture:
		wrpr	%g0, 1, %tl
661:		nop
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		SET_GL(1)
		.previous

		rdpr	%tstate, %g1
		sub	%g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
		ba,pt	%xcc, 1b
		 andcc	%g1, TSTATE_PRIV, %g0

#undef TASK_REGOFF
#undef ETRAP_PSTATE1
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* etrap.S: Preparing for entry into the kernel on Sparc V9.
	3	*
	4	* Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/page.h>
	13	#include <asm/spitfire.h>
	14	#include <asm/head.h>
	15	#include <asm/processor.h>
	16	#include <asm/mmu.h>
	17
	18	#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
64f2dde3	19	#define ETRAP_PSTATE1 (PSTATE_TSO \| PSTATE_PRIV)
1da177e4	20	#define ETRAP_PSTATE2 \
64f2dde3	21	(PSTATE_TSO \| PSTATE_PEF \| PSTATE_PRIV \| PSTATE_IE)
1da177e4 LT	22
	23	/*
	24	* On entry, %g7 is return address - 0x4.
	25	* %g4 and %g5 will be preserved %l4 and %l5 respectively.
	26	*/
	27
	28	.text
	29	.align 64
28e61036	30	.globl etrap_syscall, etrap, etrap_irq, etraptl1
1da177e4	31	etrap: rdpr %pil, %g2
28e61036 DM	32	etrap_irq: clr %g3
28e61036 DM	33	etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
1da177e4	34	rdpr %tstate, %g1
28e61036	35	or %g1, %g3, %g1
1da177e4 LT	36	sllx %g2, 20, %g3
	37	andcc %g1, TSTATE_PRIV, %g0
	38	or %g1, %g3, %g1
	39	bne,pn %xcc, 1f
	40	sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
	41	wrpr %g0, 7, %cleanwin
	42
	43	sethi %hi(TASK_REGOFF), %g2
	44	sethi %hi(TSTATE_PEF), %g3
	45	or %g2, %lo(TASK_REGOFF), %g2
	46	and %g1, %g3, %g3
	47	brnz,pn %g3, 1f
	48	add %g6, %g2, %g2
	49	wr %g0, 0, %fprs
	50	1: rdpr %tpc, %g3
	51
	52	stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
	53	rdpr %tnpc, %g1
	54	stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
	55	rd %y, %g3
	56	stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
8243e40a	57	rdpr %tt, %g1
1da177e4	58	st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
8243e40a DM	59	sethi %hi(PT_REGS_MAGIC), %g3
	60	or %g3, %g1, %g1
	61	st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
314ef685 DM	62
	63	rdpr %cansave, %g1
	64	brnz,pt %g1, etrap_save
	65	nop
	66
	67	rdpr %cwp, %g1
	68	add %g1, 2, %g1
	69	wrpr %g1, %cwp
	70	be,pt %xcc, etrap_user_spill
	71	mov ASI_AIUP, %g3
	72
	73	rdpr %otherwin, %g3
	74	brz %g3, etrap_kernel_spill
	75	mov ASI_AIUS, %g3
	76
	77	etrap_user_spill:
	78
	79	wr %g3, 0x0, %asi
	80	ldx [%g6 + TI_FLAGS], %g3
	81	and %g3, _TIF_32BIT, %g3
	82	brnz,pt %g3, etrap_user_spill_32bit
	83	nop
	84	ba,a,pt %xcc, etrap_user_spill_64bit
	85
	86	etrap_save: save %g2, -STACK_BIAS, %sp
1da177e4 LT	87	mov %g6, %l6
	88
	89	bne,pn %xcc, 3f
	90	mov PRIMARY_CONTEXT, %l4
	91	rdpr %canrestore, %g3
	92	rdpr %wstate, %g2
	93	wrpr %g0, 0, %canrestore
	94	sll %g2, 3, %g2
dff933da AV	95
dff933da AV	96	/* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR. */
1da177e4	97	mov 1, %l5
dff933da	98	sth %l5, [%l6 + TI_SYS_NOERROR]
1da177e4 LT	99
	100	wrpr %g3, 0, %otherwin
	101	wrpr %g2, 0, %wstate
0835ae0f DM	102	sethi %hi(sparc64_kern_pri_context), %g2
0835ae0f DM	103	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
8b11bd12 DM	104
	105	661: stxa %g3, [%l4] ASI_DMMU
	106	.section .sun4v_1insn_patch, "ax"
	107	.word 661b
	108	stxa %g3, [%l4] ASI_MMU
	109	.previous
	110
4da808c3 DM	111	sethi %hi(KERNBASE), %l4
4da808c3 DM	112	flush %l4
6e02493a DM	113	mov ASI_AIUS, %l7
6e02493a DM	114	2: mov %g4, %l4
1da177e4	115	mov %g5, %l5
6e02493a	116	add %g7, 4, %l2
936f482a DM	117
	118	/* Go to trap time globals so we can save them. */
	119	661: wrpr %g0, ETRAP_PSTATE1, %pstate
df7d6aec	120	.section .sun4v_1insn_patch, "ax"
936f482a DM	121	.word 661b
	122	SET_GL(0)
	123	.previous
	124
1da177e4 LT	125	stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
1da177e4 LT	126	stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
6e02493a	127	sllx %l7, 24, %l7
1da177e4	128	stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
6e02493a	129	rdpr %cwp, %l0
1da177e4 LT	130	stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
	131	stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
	132	stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
1da177e4	133	stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
6e02493a	134	or %l7, %l0, %l7
64f2dde3	135	sethi %hi(TSTATE_TSO \| TSTATE_PEF), %l0
6e02493a DM	136	or %l7, %l0, %l7
	137	wrpr %l2, %tnpc
	138	wrpr %l7, (TSTATE_PRIV \| TSTATE_IE), %tstate
1da177e4 LT	139	stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
	140	stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
	141	stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
	142	stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
	143	stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
	144	stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
1da177e4	145	stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
1da177e4	146	mov %l6, %g6
6e02493a	147	stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
ffe483d5	148	LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
6e02493a DM	149	ldx [%g6 + TI_TASK], %g4
6e02493a DM	150	done
1da177e4	151
6e02493a DM	152	3: mov ASI_P, %l7
6e02493a DM	153	ldub [%l6 + TI_FPDEPTH], %l5
1da177e4 LT	154	add %l6, TI_FPSAVED + 1, %l4
	155	srl %l5, 1, %l3
	156	add %l5, 2, %l5
dff933da AV	157
	158	/* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */
	159	sth %l5, [%l6 + TI_SYS_NOERROR]
1da177e4 LT	160	ba,pt %xcc, 2b
	161	stb %g0, [%l4 + %l3]
	162	nop
	163
	164	etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
	165	* We place this right after pt_regs on the trap stack.
	166	* The layout is:
	167	* 0x00 TL1's TSTATE
	168	* 0x08 TL1's TPC
	169	* 0x10 TL1's TNPC
	170	* 0x18 TL1's TT
	171	* ...
	172	* 0x58 TL4's TT
	173	* 0x60 TL
	174	*/
ffe483d5	175	TRAP_LOAD_THREAD_REG(%g6, %g1)
1da177e4 LT	176	sub %sp, ((4 * 8) * 4) + 8, %g2
	177	rdpr %tl, %g1
	178
	179	wrpr %g0, 1, %tl
	180	rdpr %tstate, %g3
	181	stx %g3, [%g2 + STACK_BIAS + 0x00]
	182	rdpr %tpc, %g3
	183	stx %g3, [%g2 + STACK_BIAS + 0x08]
	184	rdpr %tnpc, %g3
	185	stx %g3, [%g2 + STACK_BIAS + 0x10]
	186	rdpr %tt, %g3
	187	stx %g3, [%g2 + STACK_BIAS + 0x18]
	188
	189	wrpr %g0, 2, %tl
	190	rdpr %tstate, %g3
	191	stx %g3, [%g2 + STACK_BIAS + 0x20]
	192	rdpr %tpc, %g3
	193	stx %g3, [%g2 + STACK_BIAS + 0x28]
	194	rdpr %tnpc, %g3
	195	stx %g3, [%g2 + STACK_BIAS + 0x30]
	196	rdpr %tt, %g3
	197	stx %g3, [%g2 + STACK_BIAS + 0x38]
	198
3d6395cb DM	199	sethi %hi(is_sun4v), %g3
	200	lduw [%g3 + %lo(is_sun4v)], %g3
	201	brnz,pn %g3, finish_tl1_capture
	202	nop
	203
1da177e4 LT	204	wrpr %g0, 3, %tl
	205	rdpr %tstate, %g3
	206	stx %g3, [%g2 + STACK_BIAS + 0x40]
	207	rdpr %tpc, %g3
	208	stx %g3, [%g2 + STACK_BIAS + 0x48]
	209	rdpr %tnpc, %g3
	210	stx %g3, [%g2 + STACK_BIAS + 0x50]
	211	rdpr %tt, %g3
	212	stx %g3, [%g2 + STACK_BIAS + 0x58]
	213
	214	wrpr %g0, 4, %tl
	215	rdpr %tstate, %g3
	216	stx %g3, [%g2 + STACK_BIAS + 0x60]
	217	rdpr %tpc, %g3
	218	stx %g3, [%g2 + STACK_BIAS + 0x68]
	219	rdpr %tnpc, %g3
	220	stx %g3, [%g2 + STACK_BIAS + 0x70]
	221	rdpr %tt, %g3
	222	stx %g3, [%g2 + STACK_BIAS + 0x78]
	223
1da177e4 LT	224	stx %g1, [%g2 + STACK_BIAS + 0x80]
1da177e4 LT	225
3d6395cb	226	finish_tl1_capture:
936f482a DM	227	wrpr %g0, 1, %tl
936f482a DM	228	661: nop
df7d6aec	229	.section .sun4v_1insn_patch, "ax"
936f482a DM	230	.word 661b
	231	SET_GL(1)
	232	.previous
	233
1da177e4 LT	234	rdpr %tstate, %g1
	235	sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
	236	ba,pt %xcc, 1b
	237	andcc %g1, TSTATE_PRIV, %g0
	238
1da177e4 LT	239	#undef TASK_REGOFF
1da177e4 LT	240	#undef ETRAP_PSTATE1