Merge branch 'x86-headers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / sparc / kernel / pci_impl.h
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9fd8b647 1/* pci_impl.h: Helper definitions for PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
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4 */
5
6#ifndef PCI_IMPL_H
7#define PCI_IMPL_H
8
9#include <linux/types.h>
10#include <linux/spinlock.h>
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11#include <linux/pci.h>
12#include <linux/msi.h>
22fecbae 13#include <linux/of_device.h>
1da177e4 14#include <asm/io.h>
de8d28b1 15#include <asm/prom.h>
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16#include <asm/iommu.h>
17
18/* The abstraction used here is that there are PCI controllers,
19 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
21 * PBMs of a controller, or per-PBM), and if a streaming buffer
22 * is present, each PCI bus module has it's own. (ie. the IOMMU
23 * might be shared between PBMs, the STC is never shared)
24 * Furthermore, each PCI bus module controls it's own autonomous
25 * PCI bus.
26 */
27
28#define PCI_STC_FLUSHFLAG_INIT(STC) \
29 (*((STC)->strbuf_flushflag) = 0UL)
30#define PCI_STC_FLUSHFLAG_SET(STC) \
31 (*((STC)->strbuf_flushflag) != 0UL)
32
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33#ifdef CONFIG_PCI_MSI
34struct pci_pbm_info;
35struct sparc64_msiq_ops {
36 int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
37 unsigned long *head);
38 int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
39 unsigned long *head, unsigned long *msi);
40 int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
41 unsigned long head);
42 int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
43 unsigned long msi, int is_msi64);
44 int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
45 int (*msiq_alloc)(struct pci_pbm_info *pbm);
46 void (*msiq_free)(struct pci_pbm_info *pbm);
47 int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
48 unsigned long devino);
49};
50
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51void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
52 const struct sparc64_msiq_ops *ops);
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53
54struct sparc64_msiq_cookie {
55 struct pci_pbm_info *pbm;
56 unsigned long msiqid;
57};
58#endif
59
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60struct pci_pbm_info {
61 struct pci_pbm_info *next;
d3ae4b5b 62 struct pci_pbm_info *sibling;
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63 int index;
64
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65 /* Physical address base of controller registers. */
66 unsigned long controller_regs;
67
68 /* Physical address base of PBM registers. */
69 unsigned long pbm_regs;
70
71 /* Physical address of DMA sync register, if any. */
72 unsigned long sync_reg;
73
74 /* Opaque 32-bit system bus Port ID. */
75 u32 portid;
76
77 /* Opaque 32-bit handle used for hypervisor calls. */
78 u32 devhandle;
79
80 /* Chipset version information. */
81 int chip_type;
82#define PBM_CHIP_TYPE_SABRE 1
83#define PBM_CHIP_TYPE_PSYCHO 2
84#define PBM_CHIP_TYPE_SCHIZO 3
85#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
86#define PBM_CHIP_TYPE_TOMATILLO 5
87 int chip_version;
88 int chip_revision;
89
90 /* Name used for top-level resources. */
c22618a1 91 const char *name;
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92
93 /* OBP specific information. */
cd4cd730 94 struct platform_device *op;
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95 u64 ino_bitmap;
96
97 /* PBM I/O and Memory space resources. */
98 struct resource io_space;
99 struct resource mem_space;
af86fa40 100 struct resource mem64_space;
3f1b540d 101 struct resource busn;
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102
103 /* Base of PCI Config space, can be per-PBM or shared. */
104 unsigned long config_space;
105
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106 /* This will be 12 on PCI-E controllers, 8 elsewhere. */
107 unsigned long config_space_reg_bits;
108
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109 unsigned long pci_afsr;
110 unsigned long pci_afar;
111 unsigned long pci_csr;
112
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113 /* State of 66MHz capabilities on this PBM. */
114 int is_66mhz_capable;
115 int all_devs_66mhz;
116
117#ifdef CONFIG_PCI_MSI
118 /* MSI info. */
119 u32 msiq_num;
120 u32 msiq_ent_count;
121 u32 msiq_first;
122 u32 msiq_first_devino;
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123 u32 msiq_rotor;
124 struct sparc64_msiq_cookie *msiq_irq_cookies;
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125 u32 msi_num;
126 u32 msi_first;
127 u32 msi_data_mask;
128 u32 msix_data_width;
129 u64 msi32_start;
130 u64 msi64_start;
131 u32 msi32_len;
132 u32 msi64_len;
133 void *msi_queues;
134 unsigned long *msi_bitmap;
759f89e0 135 unsigned int *msi_irq_table;
44ed3c0c 136 int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev,
c57c2ffb 137 struct msi_desc *entry);
44ed3c0c 138 void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev);
759f89e0 139 const struct sparc64_msiq_ops *msi_ops;
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140#endif /* !(CONFIG_PCI_MSI) */
141
142 /* This PBM's streaming buffer. */
143 struct strbuf stc;
144
145 /* IOMMU state, potentially shared by both PBM segments. */
146 struct iommu *iommu;
147
148 /* Now things for the actual PCI bus probes. */
149 unsigned int pci_first_busno;
150 unsigned int pci_last_busno;
151 struct pci_bus *pci_bus;
c57c2ffb 152 struct pci_ops *pci_ops;
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153
154 int numa_node;
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155};
156
34768bc8 157extern struct pci_pbm_info *pci_pbm_root;
1da177e4 158
6c108f12 159extern int pci_num_pbms;
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160
161/* PCI bus scanning and fixup support. */
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162void pci_get_pbm_props(struct pci_pbm_info *pbm);
163struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
164 struct device *parent);
165void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
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166
167/* Error reporting support. */
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168void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
169void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
170void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
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171
172/* Configuration space access. */
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173void pci_config_read8(u8 *addr, u8 *ret);
174void pci_config_read16(u16 *addr, u16 *ret);
175void pci_config_read32(u32 *addr, u32 *ret);
176void pci_config_write8(u8 *addr, u8 val);
177void pci_config_write16(u16 *addr, u16 val);
178void pci_config_write32(u32 *addr, u32 val);
1da177e4 179
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180extern struct pci_ops sun4u_pci_ops;
181extern struct pci_ops sun4v_pci_ops;
182
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183extern volatile int pci_poke_in_progress;
184extern volatile int pci_poke_cpu;
185extern volatile int pci_poke_faulted;
186
1da177e4 187#endif /* !(PCI_IMPL_H) */
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