Commit | Line | Data |
---|---|---|
8f6a93a1 DM |
1 | /* pci_sun4v.c: SUN4V specific PCI controller support. |
2 | * | |
d284142c | 3 | * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net) |
8f6a93a1 DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/types.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/interrupt.h> | |
18397944 | 12 | #include <linux/percpu.h> |
35a17eb6 DM |
13 | #include <linux/irq.h> |
14 | #include <linux/msi.h> | |
59db8102 | 15 | #include <linux/log2.h> |
3822b509 | 16 | #include <linux/of_device.h> |
8f6a93a1 | 17 | |
8f6a93a1 DM |
18 | #include <asm/iommu.h> |
19 | #include <asm/irq.h> | |
8f6a93a1 | 20 | #include <asm/hypervisor.h> |
e87dc350 | 21 | #include <asm/prom.h> |
8f6a93a1 DM |
22 | |
23 | #include "pci_impl.h" | |
24 | #include "iommu_common.h" | |
25 | ||
bade5622 DM |
26 | #include "pci_sun4v.h" |
27 | ||
3822b509 DM |
28 | #define DRIVER_NAME "pci_sun4v" |
29 | #define PFX DRIVER_NAME ": " | |
30 | ||
e01c0d6d DM |
31 | static unsigned long vpci_major = 1; |
32 | static unsigned long vpci_minor = 1; | |
33 | ||
7c8f486a | 34 | #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64)) |
18397944 | 35 | |
16ce82d8 | 36 | struct iommu_batch { |
ad7ad57c | 37 | struct device *dev; /* Device mapping is for. */ |
6a32fd4d DM |
38 | unsigned long prot; /* IOMMU page protections */ |
39 | unsigned long entry; /* Index into IOTSB. */ | |
40 | u64 *pglist; /* List of physical pages */ | |
41 | unsigned long npages; /* Number of pages in list. */ | |
18397944 DM |
42 | }; |
43 | ||
ad7ad57c | 44 | static DEFINE_PER_CPU(struct iommu_batch, iommu_batch); |
d3ae4b5b | 45 | static int iommu_batch_initialized; |
6a32fd4d DM |
46 | |
47 | /* Interrupts must be disabled. */ | |
ad7ad57c | 48 | static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry) |
6a32fd4d | 49 | { |
ad7ad57c | 50 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d | 51 | |
ad7ad57c | 52 | p->dev = dev; |
6a32fd4d DM |
53 | p->prot = prot; |
54 | p->entry = entry; | |
55 | p->npages = 0; | |
56 | } | |
57 | ||
58 | /* Interrupts must be disabled. */ | |
ad7ad57c | 59 | static long iommu_batch_flush(struct iommu_batch *p) |
6a32fd4d | 60 | { |
ad7ad57c | 61 | struct pci_pbm_info *pbm = p->dev->archdata.host_controller; |
a2fb23af | 62 | unsigned long devhandle = pbm->devhandle; |
6a32fd4d DM |
63 | unsigned long prot = p->prot; |
64 | unsigned long entry = p->entry; | |
65 | u64 *pglist = p->pglist; | |
66 | unsigned long npages = p->npages; | |
67 | ||
d82965c1 | 68 | while (npages != 0) { |
6a32fd4d DM |
69 | long num; |
70 | ||
71 | num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry), | |
72 | npages, prot, __pa(pglist)); | |
73 | if (unlikely(num < 0)) { | |
74 | if (printk_ratelimit()) | |
ad7ad57c | 75 | printk("iommu_batch_flush: IOMMU map of " |
90181136 | 76 | "[%08lx:%08llx:%lx:%lx:%lx] failed with " |
6a32fd4d DM |
77 | "status %ld\n", |
78 | devhandle, HV_PCI_TSBID(0, entry), | |
79 | npages, prot, __pa(pglist), num); | |
80 | return -1; | |
81 | } | |
82 | ||
83 | entry += num; | |
84 | npages -= num; | |
85 | pglist += num; | |
d82965c1 | 86 | } |
6a32fd4d DM |
87 | |
88 | p->entry = entry; | |
89 | p->npages = 0; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
13fa14e1 DM |
94 | static inline void iommu_batch_new_entry(unsigned long entry) |
95 | { | |
96 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); | |
97 | ||
98 | if (p->entry + p->npages == entry) | |
99 | return; | |
100 | if (p->entry != ~0UL) | |
101 | iommu_batch_flush(p); | |
102 | p->entry = entry; | |
103 | } | |
104 | ||
6a32fd4d | 105 | /* Interrupts must be disabled. */ |
ad7ad57c | 106 | static inline long iommu_batch_add(u64 phys_page) |
6a32fd4d | 107 | { |
ad7ad57c | 108 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d DM |
109 | |
110 | BUG_ON(p->npages >= PGLIST_NENTS); | |
111 | ||
112 | p->pglist[p->npages++] = phys_page; | |
113 | if (p->npages == PGLIST_NENTS) | |
ad7ad57c | 114 | return iommu_batch_flush(p); |
6a32fd4d DM |
115 | |
116 | return 0; | |
117 | } | |
118 | ||
119 | /* Interrupts must be disabled. */ | |
ad7ad57c | 120 | static inline long iommu_batch_end(void) |
6a32fd4d | 121 | { |
ad7ad57c | 122 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d DM |
123 | |
124 | BUG_ON(p->npages >= PGLIST_NENTS); | |
125 | ||
ad7ad57c | 126 | return iommu_batch_flush(p); |
6a32fd4d | 127 | } |
18397944 | 128 | |
ad7ad57c DM |
129 | static void *dma_4v_alloc_coherent(struct device *dev, size_t size, |
130 | dma_addr_t *dma_addrp, gfp_t gfp) | |
8f6a93a1 | 131 | { |
7c8f486a | 132 | unsigned long flags, order, first_page, npages, n; |
c1b1a5f1 DM |
133 | struct iommu *iommu; |
134 | struct page *page; | |
18397944 DM |
135 | void *ret; |
136 | long entry; | |
c1b1a5f1 | 137 | int nid; |
18397944 DM |
138 | |
139 | size = IO_PAGE_ALIGN(size); | |
140 | order = get_order(size); | |
6a32fd4d | 141 | if (unlikely(order >= MAX_ORDER)) |
18397944 DM |
142 | return NULL; |
143 | ||
144 | npages = size >> IO_PAGE_SHIFT; | |
18397944 | 145 | |
c1b1a5f1 DM |
146 | nid = dev->archdata.numa_node; |
147 | page = alloc_pages_node(nid, gfp, order); | |
148 | if (unlikely(!page)) | |
18397944 | 149 | return NULL; |
e7a0453e | 150 | |
c1b1a5f1 | 151 | first_page = (unsigned long) page_address(page); |
18397944 DM |
152 | memset((char *)first_page, 0, PAGE_SIZE << order); |
153 | ||
ad7ad57c | 154 | iommu = dev->archdata.iommu; |
18397944 DM |
155 | |
156 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 157 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
18397944 DM |
158 | spin_unlock_irqrestore(&iommu->lock, flags); |
159 | ||
d284142c DM |
160 | if (unlikely(entry == DMA_ERROR_CODE)) |
161 | goto range_alloc_fail; | |
18397944 DM |
162 | |
163 | *dma_addrp = (iommu->page_table_map_base + | |
164 | (entry << IO_PAGE_SHIFT)); | |
165 | ret = (void *) first_page; | |
166 | first_page = __pa(first_page); | |
167 | ||
6a32fd4d | 168 | local_irq_save(flags); |
18397944 | 169 | |
ad7ad57c DM |
170 | iommu_batch_start(dev, |
171 | (HV_PCI_MAP_ATTR_READ | | |
172 | HV_PCI_MAP_ATTR_WRITE), | |
173 | entry); | |
18397944 | 174 | |
6a32fd4d | 175 | for (n = 0; n < npages; n++) { |
ad7ad57c | 176 | long err = iommu_batch_add(first_page + (n * PAGE_SIZE)); |
6a32fd4d DM |
177 | if (unlikely(err < 0L)) |
178 | goto iommu_map_fail; | |
179 | } | |
18397944 | 180 | |
ad7ad57c | 181 | if (unlikely(iommu_batch_end() < 0L)) |
6a32fd4d | 182 | goto iommu_map_fail; |
18397944 | 183 | |
6a32fd4d | 184 | local_irq_restore(flags); |
18397944 DM |
185 | |
186 | return ret; | |
6a32fd4d DM |
187 | |
188 | iommu_map_fail: | |
189 | /* Interrupts are disabled. */ | |
190 | spin_lock(&iommu->lock); | |
d284142c | 191 | iommu_range_free(iommu, *dma_addrp, npages); |
6a32fd4d DM |
192 | spin_unlock_irqrestore(&iommu->lock, flags); |
193 | ||
d284142c | 194 | range_alloc_fail: |
6a32fd4d DM |
195 | free_pages(first_page, order); |
196 | return NULL; | |
8f6a93a1 DM |
197 | } |
198 | ||
ad7ad57c DM |
199 | static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu, |
200 | dma_addr_t dvma) | |
8f6a93a1 | 201 | { |
a2fb23af | 202 | struct pci_pbm_info *pbm; |
16ce82d8 | 203 | struct iommu *iommu; |
7c8f486a DM |
204 | unsigned long flags, order, npages, entry; |
205 | u32 devhandle; | |
18397944 DM |
206 | |
207 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c DM |
208 | iommu = dev->archdata.iommu; |
209 | pbm = dev->archdata.host_controller; | |
a2fb23af | 210 | devhandle = pbm->devhandle; |
18397944 DM |
211 | entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); |
212 | ||
213 | spin_lock_irqsave(&iommu->lock, flags); | |
214 | ||
d284142c | 215 | iommu_range_free(iommu, dvma, npages); |
18397944 DM |
216 | |
217 | do { | |
218 | unsigned long num; | |
219 | ||
220 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
221 | npages); | |
222 | entry += num; | |
223 | npages -= num; | |
224 | } while (npages != 0); | |
225 | ||
226 | spin_unlock_irqrestore(&iommu->lock, flags); | |
227 | ||
228 | order = get_order(size); | |
229 | if (order < 10) | |
230 | free_pages((unsigned long)cpu, order); | |
8f6a93a1 DM |
231 | } |
232 | ||
797a7568 FT |
233 | static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page, |
234 | unsigned long offset, size_t sz, | |
235 | enum dma_data_direction direction) | |
8f6a93a1 | 236 | { |
16ce82d8 | 237 | struct iommu *iommu; |
18397944 | 238 | unsigned long flags, npages, oaddr; |
7c8f486a | 239 | unsigned long i, base_paddr; |
6a32fd4d | 240 | u32 bus_addr, ret; |
18397944 DM |
241 | unsigned long prot; |
242 | long entry; | |
18397944 | 243 | |
ad7ad57c | 244 | iommu = dev->archdata.iommu; |
18397944 | 245 | |
ad7ad57c | 246 | if (unlikely(direction == DMA_NONE)) |
18397944 DM |
247 | goto bad; |
248 | ||
797a7568 | 249 | oaddr = (unsigned long)(page_address(page) + offset); |
18397944 DM |
250 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); |
251 | npages >>= IO_PAGE_SHIFT; | |
18397944 DM |
252 | |
253 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 254 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
18397944 DM |
255 | spin_unlock_irqrestore(&iommu->lock, flags); |
256 | ||
d284142c | 257 | if (unlikely(entry == DMA_ERROR_CODE)) |
18397944 DM |
258 | goto bad; |
259 | ||
260 | bus_addr = (iommu->page_table_map_base + | |
261 | (entry << IO_PAGE_SHIFT)); | |
262 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
263 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
264 | prot = HV_PCI_MAP_ATTR_READ; | |
ad7ad57c | 265 | if (direction != DMA_TO_DEVICE) |
18397944 DM |
266 | prot |= HV_PCI_MAP_ATTR_WRITE; |
267 | ||
6a32fd4d | 268 | local_irq_save(flags); |
18397944 | 269 | |
ad7ad57c | 270 | iommu_batch_start(dev, prot, entry); |
18397944 | 271 | |
6a32fd4d | 272 | for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) { |
ad7ad57c | 273 | long err = iommu_batch_add(base_paddr); |
6a32fd4d DM |
274 | if (unlikely(err < 0L)) |
275 | goto iommu_map_fail; | |
276 | } | |
ad7ad57c | 277 | if (unlikely(iommu_batch_end() < 0L)) |
6a32fd4d | 278 | goto iommu_map_fail; |
18397944 | 279 | |
6a32fd4d | 280 | local_irq_restore(flags); |
18397944 DM |
281 | |
282 | return ret; | |
283 | ||
284 | bad: | |
285 | if (printk_ratelimit()) | |
286 | WARN_ON(1); | |
ad7ad57c | 287 | return DMA_ERROR_CODE; |
6a32fd4d DM |
288 | |
289 | iommu_map_fail: | |
290 | /* Interrupts are disabled. */ | |
291 | spin_lock(&iommu->lock); | |
d284142c | 292 | iommu_range_free(iommu, bus_addr, npages); |
6a32fd4d DM |
293 | spin_unlock_irqrestore(&iommu->lock, flags); |
294 | ||
ad7ad57c | 295 | return DMA_ERROR_CODE; |
8f6a93a1 DM |
296 | } |
297 | ||
797a7568 FT |
298 | static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr, |
299 | size_t sz, enum dma_data_direction direction) | |
8f6a93a1 | 300 | { |
a2fb23af | 301 | struct pci_pbm_info *pbm; |
16ce82d8 | 302 | struct iommu *iommu; |
7c8f486a | 303 | unsigned long flags, npages; |
18397944 | 304 | long entry; |
7c8f486a | 305 | u32 devhandle; |
18397944 | 306 | |
ad7ad57c | 307 | if (unlikely(direction == DMA_NONE)) { |
18397944 DM |
308 | if (printk_ratelimit()) |
309 | WARN_ON(1); | |
310 | return; | |
311 | } | |
312 | ||
ad7ad57c DM |
313 | iommu = dev->archdata.iommu; |
314 | pbm = dev->archdata.host_controller; | |
a2fb23af | 315 | devhandle = pbm->devhandle; |
18397944 DM |
316 | |
317 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
318 | npages >>= IO_PAGE_SHIFT; | |
319 | bus_addr &= IO_PAGE_MASK; | |
320 | ||
321 | spin_lock_irqsave(&iommu->lock, flags); | |
322 | ||
d284142c | 323 | iommu_range_free(iommu, bus_addr, npages); |
18397944 | 324 | |
d284142c | 325 | entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT; |
18397944 DM |
326 | do { |
327 | unsigned long num; | |
328 | ||
329 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
330 | npages); | |
331 | entry += num; | |
332 | npages -= num; | |
333 | } while (npages != 0); | |
334 | ||
335 | spin_unlock_irqrestore(&iommu->lock, flags); | |
336 | } | |
337 | ||
ad7ad57c DM |
338 | static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist, |
339 | int nelems, enum dma_data_direction direction) | |
8f6a93a1 | 340 | { |
13fa14e1 DM |
341 | struct scatterlist *s, *outs, *segstart; |
342 | unsigned long flags, handle, prot; | |
343 | dma_addr_t dma_next = 0, dma_addr; | |
344 | unsigned int max_seg_size; | |
f0880257 | 345 | unsigned long seg_boundary_size; |
13fa14e1 | 346 | int outcount, incount, i; |
16ce82d8 | 347 | struct iommu *iommu; |
f0880257 | 348 | unsigned long base_shift; |
13fa14e1 DM |
349 | long err; |
350 | ||
351 | BUG_ON(direction == DMA_NONE); | |
18397944 | 352 | |
ad7ad57c | 353 | iommu = dev->archdata.iommu; |
13fa14e1 DM |
354 | if (nelems == 0 || !iommu) |
355 | return 0; | |
18397944 | 356 | |
13fa14e1 DM |
357 | prot = HV_PCI_MAP_ATTR_READ; |
358 | if (direction != DMA_TO_DEVICE) | |
359 | prot |= HV_PCI_MAP_ATTR_WRITE; | |
18397944 | 360 | |
13fa14e1 DM |
361 | outs = s = segstart = &sglist[0]; |
362 | outcount = 1; | |
363 | incount = nelems; | |
364 | handle = 0; | |
18397944 | 365 | |
13fa14e1 DM |
366 | /* Init first segment length for backout at failure */ |
367 | outs->dma_length = 0; | |
18397944 | 368 | |
13fa14e1 | 369 | spin_lock_irqsave(&iommu->lock, flags); |
18397944 | 370 | |
13fa14e1 | 371 | iommu_batch_start(dev, prot, ~0UL); |
18397944 | 372 | |
13fa14e1 | 373 | max_seg_size = dma_get_max_seg_size(dev); |
f0880257 FT |
374 | seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
375 | IO_PAGE_SIZE) >> IO_PAGE_SHIFT; | |
376 | base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT; | |
13fa14e1 | 377 | for_each_sg(sglist, s, nelems, i) { |
f0880257 | 378 | unsigned long paddr, npages, entry, out_entry = 0, slen; |
38192d52 | 379 | |
13fa14e1 DM |
380 | slen = s->length; |
381 | /* Sanity check */ | |
382 | if (slen == 0) { | |
383 | dma_next = 0; | |
384 | continue; | |
385 | } | |
386 | /* Allocate iommu entries for that segment */ | |
387 | paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); | |
0fcff28f | 388 | npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE); |
13fa14e1 | 389 | entry = iommu_range_alloc(dev, iommu, npages, &handle); |
38192d52 | 390 | |
13fa14e1 DM |
391 | /* Handle failure */ |
392 | if (unlikely(entry == DMA_ERROR_CODE)) { | |
393 | if (printk_ratelimit()) | |
394 | printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx" | |
395 | " npages %lx\n", iommu, paddr, npages); | |
396 | goto iommu_map_failed; | |
397 | } | |
38192d52 | 398 | |
13fa14e1 | 399 | iommu_batch_new_entry(entry); |
38192d52 | 400 | |
13fa14e1 DM |
401 | /* Convert entry to a dma_addr_t */ |
402 | dma_addr = iommu->page_table_map_base + | |
403 | (entry << IO_PAGE_SHIFT); | |
404 | dma_addr |= (s->offset & ~IO_PAGE_MASK); | |
38192d52 | 405 | |
13fa14e1 | 406 | /* Insert into HW table */ |
38192d52 | 407 | paddr &= IO_PAGE_MASK; |
13fa14e1 | 408 | while (npages--) { |
38192d52 | 409 | err = iommu_batch_add(paddr); |
13fa14e1 | 410 | if (unlikely(err < 0L)) |
38192d52 | 411 | goto iommu_map_failed; |
13fa14e1 DM |
412 | paddr += IO_PAGE_SIZE; |
413 | } | |
414 | ||
415 | /* If we are in an open segment, try merging */ | |
416 | if (segstart != s) { | |
417 | /* We cannot merge if: | |
418 | * - allocated dma_addr isn't contiguous to previous allocation | |
419 | */ | |
420 | if ((dma_addr != dma_next) || | |
f0880257 FT |
421 | (outs->dma_length + s->length > max_seg_size) || |
422 | (is_span_boundary(out_entry, base_shift, | |
423 | seg_boundary_size, outs, s))) { | |
13fa14e1 DM |
424 | /* Can't merge: create a new segment */ |
425 | segstart = s; | |
426 | outcount++; | |
427 | outs = sg_next(outs); | |
428 | } else { | |
429 | outs->dma_length += s->length; | |
38192d52 | 430 | } |
13fa14e1 | 431 | } |
38192d52 | 432 | |
13fa14e1 DM |
433 | if (segstart == s) { |
434 | /* This is a new segment, fill entries */ | |
435 | outs->dma_address = dma_addr; | |
436 | outs->dma_length = slen; | |
f0880257 | 437 | out_entry = entry; |
38192d52 | 438 | } |
13fa14e1 DM |
439 | |
440 | /* Calculate next page pointer for contiguous check */ | |
441 | dma_next = dma_addr + slen; | |
38192d52 DM |
442 | } |
443 | ||
444 | err = iommu_batch_end(); | |
445 | ||
6a32fd4d DM |
446 | if (unlikely(err < 0L)) |
447 | goto iommu_map_failed; | |
18397944 | 448 | |
13fa14e1 | 449 | spin_unlock_irqrestore(&iommu->lock, flags); |
18397944 | 450 | |
13fa14e1 DM |
451 | if (outcount < incount) { |
452 | outs = sg_next(outs); | |
453 | outs->dma_address = DMA_ERROR_CODE; | |
454 | outs->dma_length = 0; | |
455 | } | |
456 | ||
457 | return outcount; | |
6a32fd4d DM |
458 | |
459 | iommu_map_failed: | |
13fa14e1 DM |
460 | for_each_sg(sglist, s, nelems, i) { |
461 | if (s->dma_length != 0) { | |
462 | unsigned long vaddr, npages; | |
463 | ||
464 | vaddr = s->dma_address & IO_PAGE_MASK; | |
0fcff28f JR |
465 | npages = iommu_num_pages(s->dma_address, s->dma_length, |
466 | IO_PAGE_SIZE); | |
13fa14e1 DM |
467 | iommu_range_free(iommu, vaddr, npages); |
468 | /* XXX demap? XXX */ | |
469 | s->dma_address = DMA_ERROR_CODE; | |
470 | s->dma_length = 0; | |
471 | } | |
472 | if (s == outs) | |
473 | break; | |
474 | } | |
6a32fd4d DM |
475 | spin_unlock_irqrestore(&iommu->lock, flags); |
476 | ||
477 | return 0; | |
8f6a93a1 DM |
478 | } |
479 | ||
ad7ad57c DM |
480 | static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist, |
481 | int nelems, enum dma_data_direction direction) | |
8f6a93a1 | 482 | { |
a2fb23af | 483 | struct pci_pbm_info *pbm; |
13fa14e1 | 484 | struct scatterlist *sg; |
16ce82d8 | 485 | struct iommu *iommu; |
13fa14e1 DM |
486 | unsigned long flags; |
487 | u32 devhandle; | |
18397944 | 488 | |
13fa14e1 | 489 | BUG_ON(direction == DMA_NONE); |
18397944 | 490 | |
ad7ad57c DM |
491 | iommu = dev->archdata.iommu; |
492 | pbm = dev->archdata.host_controller; | |
a2fb23af | 493 | devhandle = pbm->devhandle; |
18397944 | 494 | |
18397944 DM |
495 | spin_lock_irqsave(&iommu->lock, flags); |
496 | ||
13fa14e1 DM |
497 | sg = sglist; |
498 | while (nelems--) { | |
499 | dma_addr_t dma_handle = sg->dma_address; | |
500 | unsigned int len = sg->dma_length; | |
501 | unsigned long npages, entry; | |
502 | ||
503 | if (!len) | |
504 | break; | |
0fcff28f | 505 | npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE); |
13fa14e1 DM |
506 | iommu_range_free(iommu, dma_handle, npages); |
507 | ||
508 | entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
509 | while (npages) { | |
510 | unsigned long num; | |
511 | ||
512 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
513 | npages); | |
514 | entry += num; | |
515 | npages -= num; | |
516 | } | |
18397944 | 517 | |
13fa14e1 DM |
518 | sg = sg_next(sg); |
519 | } | |
18397944 DM |
520 | |
521 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8f6a93a1 DM |
522 | } |
523 | ||
ad7ad57c DM |
524 | static void dma_4v_sync_single_for_cpu(struct device *dev, |
525 | dma_addr_t bus_addr, size_t sz, | |
526 | enum dma_data_direction direction) | |
8f6a93a1 | 527 | { |
18397944 | 528 | /* Nothing to do... */ |
8f6a93a1 DM |
529 | } |
530 | ||
ad7ad57c DM |
531 | static void dma_4v_sync_sg_for_cpu(struct device *dev, |
532 | struct scatterlist *sglist, int nelems, | |
533 | enum dma_data_direction direction) | |
8f6a93a1 | 534 | { |
18397944 | 535 | /* Nothing to do... */ |
8f6a93a1 DM |
536 | } |
537 | ||
908f5162 | 538 | static const struct dma_ops sun4v_dma_ops = { |
ad7ad57c DM |
539 | .alloc_coherent = dma_4v_alloc_coherent, |
540 | .free_coherent = dma_4v_free_coherent, | |
797a7568 FT |
541 | .map_page = dma_4v_map_page, |
542 | .unmap_page = dma_4v_unmap_page, | |
ad7ad57c DM |
543 | .map_sg = dma_4v_map_sg, |
544 | .unmap_sg = dma_4v_unmap_sg, | |
545 | .sync_single_for_cpu = dma_4v_sync_single_for_cpu, | |
546 | .sync_sg_for_cpu = dma_4v_sync_sg_for_cpu, | |
8f6a93a1 DM |
547 | }; |
548 | ||
9a2ed5cc DM |
549 | static void __devinit pci_sun4v_scan_bus(struct pci_pbm_info *pbm, |
550 | struct device *parent) | |
bade5622 | 551 | { |
e87dc350 DM |
552 | struct property *prop; |
553 | struct device_node *dp; | |
554 | ||
22fecbae | 555 | dp = pbm->op->node; |
34768bc8 DM |
556 | prop = of_find_property(dp, "66mhz-capable", NULL); |
557 | pbm->is_66mhz_capable = (prop != NULL); | |
e822358a | 558 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
c2609267 DM |
559 | |
560 | /* XXX register error interrupt handlers XXX */ | |
bade5622 DM |
561 | } |
562 | ||
9a2ed5cc DM |
563 | static unsigned long __devinit probe_existing_entries(struct pci_pbm_info *pbm, |
564 | struct iommu *iommu) | |
18397944 | 565 | { |
9b3627f3 | 566 | struct iommu_arena *arena = &iommu->arena; |
e7a0453e | 567 | unsigned long i, cnt = 0; |
7c8f486a | 568 | u32 devhandle; |
18397944 DM |
569 | |
570 | devhandle = pbm->devhandle; | |
571 | for (i = 0; i < arena->limit; i++) { | |
572 | unsigned long ret, io_attrs, ra; | |
573 | ||
574 | ret = pci_sun4v_iommu_getmap(devhandle, | |
575 | HV_PCI_TSBID(0, i), | |
576 | &io_attrs, &ra); | |
e7a0453e | 577 | if (ret == HV_EOK) { |
c2a5a46b DM |
578 | if (page_in_phys_avail(ra)) { |
579 | pci_sun4v_iommu_demap(devhandle, | |
580 | HV_PCI_TSBID(0, i), 1); | |
581 | } else { | |
582 | cnt++; | |
583 | __set_bit(i, arena->map); | |
584 | } | |
e7a0453e | 585 | } |
18397944 | 586 | } |
e7a0453e DM |
587 | |
588 | return cnt; | |
18397944 DM |
589 | } |
590 | ||
9a2ed5cc | 591 | static int __devinit pci_sun4v_iommu_init(struct pci_pbm_info *pbm) |
bade5622 | 592 | { |
8aef7278 | 593 | static const u32 vdma_default[] = { 0x80000000, 0x80000000 }; |
16ce82d8 | 594 | struct iommu *iommu = pbm->iommu; |
59db8102 | 595 | unsigned long num_tsb_entries, sz, tsbsize; |
8aef7278 DM |
596 | u32 dma_mask, dma_offset; |
597 | const u32 *vdma; | |
598 | ||
22fecbae | 599 | vdma = of_get_property(pbm->op->node, "virtual-dma", NULL); |
8aef7278 DM |
600 | if (!vdma) |
601 | vdma = vdma_default; | |
18397944 | 602 | |
59db8102 | 603 | if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) { |
3822b509 DM |
604 | printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n", |
605 | vdma[0], vdma[1]); | |
606 | return -EINVAL; | |
18397944 DM |
607 | }; |
608 | ||
59db8102 DM |
609 | dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); |
610 | num_tsb_entries = vdma[1] / IO_PAGE_SIZE; | |
611 | tsbsize = num_tsb_entries * sizeof(iopte_t); | |
18397944 DM |
612 | |
613 | dma_offset = vdma[0]; | |
614 | ||
615 | /* Setup initial software IOMMU state. */ | |
616 | spin_lock_init(&iommu->lock); | |
617 | iommu->ctx_lowest_free = 1; | |
618 | iommu->page_table_map_base = dma_offset; | |
619 | iommu->dma_addr_mask = dma_mask; | |
620 | ||
621 | /* Allocate and initialize the free area map. */ | |
59db8102 | 622 | sz = (num_tsb_entries + 7) / 8; |
18397944 | 623 | sz = (sz + 7UL) & ~7UL; |
982c2064 | 624 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
18397944 | 625 | if (!iommu->arena.map) { |
3822b509 DM |
626 | printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n"); |
627 | return -ENOMEM; | |
18397944 | 628 | } |
18397944 DM |
629 | iommu->arena.limit = num_tsb_entries; |
630 | ||
e7a0453e | 631 | sz = probe_existing_entries(pbm, iommu); |
c2a5a46b DM |
632 | if (sz) |
633 | printk("%s: Imported %lu TSB entries from OBP\n", | |
634 | pbm->name, sz); | |
3822b509 DM |
635 | |
636 | return 0; | |
bade5622 DM |
637 | } |
638 | ||
35a17eb6 DM |
639 | #ifdef CONFIG_PCI_MSI |
640 | struct pci_sun4v_msiq_entry { | |
641 | u64 version_type; | |
642 | #define MSIQ_VERSION_MASK 0xffffffff00000000UL | |
643 | #define MSIQ_VERSION_SHIFT 32 | |
644 | #define MSIQ_TYPE_MASK 0x00000000000000ffUL | |
645 | #define MSIQ_TYPE_SHIFT 0 | |
646 | #define MSIQ_TYPE_NONE 0x00 | |
647 | #define MSIQ_TYPE_MSG 0x01 | |
648 | #define MSIQ_TYPE_MSI32 0x02 | |
649 | #define MSIQ_TYPE_MSI64 0x03 | |
650 | #define MSIQ_TYPE_INTX 0x08 | |
651 | #define MSIQ_TYPE_NONE2 0xff | |
652 | ||
653 | u64 intx_sysino; | |
654 | u64 reserved1; | |
655 | u64 stick; | |
656 | u64 req_id; /* bus/device/func */ | |
657 | #define MSIQ_REQID_BUS_MASK 0xff00UL | |
658 | #define MSIQ_REQID_BUS_SHIFT 8 | |
659 | #define MSIQ_REQID_DEVICE_MASK 0x00f8UL | |
660 | #define MSIQ_REQID_DEVICE_SHIFT 3 | |
661 | #define MSIQ_REQID_FUNC_MASK 0x0007UL | |
662 | #define MSIQ_REQID_FUNC_SHIFT 0 | |
663 | ||
664 | u64 msi_address; | |
665 | ||
e5dd42e4 | 666 | /* The format of this value is message type dependent. |
35a17eb6 DM |
667 | * For MSI bits 15:0 are the data from the MSI packet. |
668 | * For MSI-X bits 31:0 are the data from the MSI packet. | |
669 | * For MSG, the message code and message routing code where: | |
670 | * bits 39:32 is the bus/device/fn of the msg target-id | |
671 | * bits 18:16 is the message routing code | |
672 | * bits 7:0 is the message code | |
673 | * For INTx the low order 2-bits are: | |
674 | * 00 - INTA | |
675 | * 01 - INTB | |
676 | * 10 - INTC | |
677 | * 11 - INTD | |
678 | */ | |
679 | u64 msi_data; | |
680 | ||
681 | u64 reserved2; | |
682 | }; | |
683 | ||
759f89e0 DM |
684 | static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
685 | unsigned long *head) | |
35a17eb6 | 686 | { |
759f89e0 | 687 | unsigned long err, limit; |
35a17eb6 | 688 | |
759f89e0 | 689 | err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head); |
35a17eb6 | 690 | if (unlikely(err)) |
759f89e0 | 691 | return -ENXIO; |
35a17eb6 | 692 | |
759f89e0 DM |
693 | limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); |
694 | if (unlikely(*head >= limit)) | |
695 | return -EFBIG; | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm, | |
701 | unsigned long msiqid, unsigned long *head, | |
702 | unsigned long *msi) | |
703 | { | |
704 | struct pci_sun4v_msiq_entry *ep; | |
705 | unsigned long err, type; | |
706 | ||
707 | /* Note: void pointer arithmetic, 'head' is a byte offset */ | |
708 | ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * | |
709 | (pbm->msiq_ent_count * | |
710 | sizeof(struct pci_sun4v_msiq_entry))) + | |
711 | *head); | |
712 | ||
713 | if ((ep->version_type & MSIQ_TYPE_MASK) == 0) | |
714 | return 0; | |
35a17eb6 | 715 | |
759f89e0 DM |
716 | type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT; |
717 | if (unlikely(type != MSIQ_TYPE_MSI32 && | |
718 | type != MSIQ_TYPE_MSI64)) | |
719 | return -EINVAL; | |
35a17eb6 | 720 | |
759f89e0 DM |
721 | *msi = ep->msi_data; |
722 | ||
723 | err = pci_sun4v_msi_setstate(pbm->devhandle, | |
724 | ep->msi_data /* msi_num */, | |
725 | HV_MSISTATE_IDLE); | |
726 | if (unlikely(err)) | |
727 | return -ENXIO; | |
35a17eb6 | 728 | |
759f89e0 DM |
729 | /* Clear the entry. */ |
730 | ep->version_type &= ~MSIQ_TYPE_MASK; | |
35a17eb6 | 731 | |
759f89e0 DM |
732 | (*head) += sizeof(struct pci_sun4v_msiq_entry); |
733 | if (*head >= | |
734 | (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))) | |
735 | *head = 0; | |
35a17eb6 | 736 | |
759f89e0 | 737 | return 1; |
35a17eb6 DM |
738 | } |
739 | ||
759f89e0 DM |
740 | static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
741 | unsigned long head) | |
35a17eb6 | 742 | { |
759f89e0 | 743 | unsigned long err; |
35a17eb6 | 744 | |
759f89e0 DM |
745 | err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head); |
746 | if (unlikely(err)) | |
747 | return -EINVAL; | |
35a17eb6 | 748 | |
759f89e0 DM |
749 | return 0; |
750 | } | |
35a17eb6 | 751 | |
759f89e0 DM |
752 | static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, |
753 | unsigned long msi, int is_msi64) | |
754 | { | |
755 | if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid, | |
756 | (is_msi64 ? | |
757 | HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32))) | |
758 | return -ENXIO; | |
759 | if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE)) | |
760 | return -ENXIO; | |
761 | if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID)) | |
762 | return -ENXIO; | |
35a17eb6 DM |
763 | return 0; |
764 | } | |
765 | ||
759f89e0 | 766 | static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) |
35a17eb6 | 767 | { |
759f89e0 DM |
768 | unsigned long err, msiqid; |
769 | ||
770 | err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid); | |
771 | if (err) | |
772 | return -ENXIO; | |
773 | ||
774 | pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID); | |
775 | ||
776 | return 0; | |
35a17eb6 DM |
777 | } |
778 | ||
759f89e0 | 779 | static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm) |
35a17eb6 DM |
780 | { |
781 | unsigned long q_size, alloc_size, pages, order; | |
782 | int i; | |
783 | ||
784 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); | |
785 | alloc_size = (pbm->msiq_num * q_size); | |
786 | order = get_order(alloc_size); | |
787 | pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order); | |
788 | if (pages == 0UL) { | |
789 | printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n", | |
790 | order); | |
791 | return -ENOMEM; | |
792 | } | |
793 | memset((char *)pages, 0, PAGE_SIZE << order); | |
794 | pbm->msi_queues = (void *) pages; | |
795 | ||
796 | for (i = 0; i < pbm->msiq_num; i++) { | |
797 | unsigned long err, base = __pa(pages + (i * q_size)); | |
798 | unsigned long ret1, ret2; | |
799 | ||
800 | err = pci_sun4v_msiq_conf(pbm->devhandle, | |
801 | pbm->msiq_first + i, | |
802 | base, pbm->msiq_ent_count); | |
803 | if (err) { | |
804 | printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n", | |
805 | err); | |
806 | goto h_error; | |
807 | } | |
808 | ||
809 | err = pci_sun4v_msiq_info(pbm->devhandle, | |
810 | pbm->msiq_first + i, | |
811 | &ret1, &ret2); | |
812 | if (err) { | |
813 | printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n", | |
814 | err); | |
815 | goto h_error; | |
816 | } | |
817 | if (ret1 != base || ret2 != pbm->msiq_ent_count) { | |
818 | printk(KERN_ERR "MSI: Bogus qconf " | |
819 | "expected[%lx:%x] got[%lx:%lx]\n", | |
820 | base, pbm->msiq_ent_count, | |
821 | ret1, ret2); | |
822 | goto h_error; | |
823 | } | |
824 | } | |
825 | ||
826 | return 0; | |
827 | ||
828 | h_error: | |
829 | free_pages(pages, order); | |
830 | return -EINVAL; | |
831 | } | |
832 | ||
759f89e0 | 833 | static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm) |
35a17eb6 | 834 | { |
759f89e0 | 835 | unsigned long q_size, alloc_size, pages, order; |
35a17eb6 DM |
836 | int i; |
837 | ||
759f89e0 DM |
838 | for (i = 0; i < pbm->msiq_num; i++) { |
839 | unsigned long msiqid = pbm->msiq_first + i; | |
35a17eb6 | 840 | |
759f89e0 | 841 | (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0); |
35a17eb6 | 842 | } |
7fe3730d | 843 | |
759f89e0 DM |
844 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); |
845 | alloc_size = (pbm->msiq_num * q_size); | |
846 | order = get_order(alloc_size); | |
35a17eb6 | 847 | |
759f89e0 | 848 | pages = (unsigned long) pbm->msi_queues; |
35a17eb6 | 849 | |
759f89e0 | 850 | free_pages(pages, order); |
35a17eb6 | 851 | |
759f89e0 | 852 | pbm->msi_queues = NULL; |
35a17eb6 DM |
853 | } |
854 | ||
759f89e0 DM |
855 | static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm, |
856 | unsigned long msiqid, | |
857 | unsigned long devino) | |
35a17eb6 | 858 | { |
759f89e0 | 859 | unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino); |
35a17eb6 | 860 | |
759f89e0 DM |
861 | if (!virt_irq) |
862 | return -ENOMEM; | |
35a17eb6 | 863 | |
759f89e0 DM |
864 | if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) |
865 | return -EINVAL; | |
866 | if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) | |
867 | return -EINVAL; | |
35a17eb6 | 868 | |
759f89e0 | 869 | return virt_irq; |
35a17eb6 | 870 | } |
e9870c4c | 871 | |
759f89e0 DM |
872 | static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = { |
873 | .get_head = pci_sun4v_get_head, | |
874 | .dequeue_msi = pci_sun4v_dequeue_msi, | |
875 | .set_head = pci_sun4v_set_head, | |
876 | .msi_setup = pci_sun4v_msi_setup, | |
877 | .msi_teardown = pci_sun4v_msi_teardown, | |
878 | .msiq_alloc = pci_sun4v_msiq_alloc, | |
879 | .msiq_free = pci_sun4v_msiq_free, | |
880 | .msiq_build_irq = pci_sun4v_msiq_build_irq, | |
881 | }; | |
882 | ||
e9870c4c DM |
883 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) |
884 | { | |
759f89e0 | 885 | sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops); |
e9870c4c | 886 | } |
35a17eb6 DM |
887 | #else /* CONFIG_PCI_MSI */ |
888 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) | |
889 | { | |
890 | } | |
891 | #endif /* !(CONFIG_PCI_MSI) */ | |
892 | ||
9a2ed5cc DM |
893 | static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm, |
894 | struct of_device *op, u32 devhandle) | |
bade5622 | 895 | { |
e822358a | 896 | struct device_node *dp = op->node; |
3822b509 | 897 | int err; |
bade5622 | 898 | |
c1b1a5f1 DM |
899 | pbm->numa_node = of_node_to_nid(dp); |
900 | ||
ca3dd88e DM |
901 | pbm->pci_ops = &sun4v_pci_ops; |
902 | pbm->config_space_reg_bits = 12; | |
34768bc8 | 903 | |
6c108f12 DM |
904 | pbm->index = pci_num_pbms++; |
905 | ||
22fecbae | 906 | pbm->op = op; |
bade5622 | 907 | |
3833789b | 908 | pbm->devhandle = devhandle; |
bade5622 | 909 | |
e87dc350 | 910 | pbm->name = dp->full_name; |
bade5622 | 911 | |
e87dc350 | 912 | printk("%s: SUN4V PCI Bus Module\n", pbm->name); |
c1b1a5f1 | 913 | printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node); |
bade5622 | 914 | |
9fd8b647 | 915 | pci_determine_mem_io_space(pbm); |
bade5622 | 916 | |
cfa0652c | 917 | pci_get_pbm_props(pbm); |
3822b509 DM |
918 | |
919 | err = pci_sun4v_iommu_init(pbm); | |
920 | if (err) | |
921 | return err; | |
922 | ||
35a17eb6 | 923 | pci_sun4v_msi_init(pbm); |
3822b509 | 924 | |
e822358a | 925 | pci_sun4v_scan_bus(pbm, &op->dev); |
3822b509 | 926 | |
d3ae4b5b DM |
927 | pbm->next = pci_pbm_root; |
928 | pci_pbm_root = pbm; | |
929 | ||
3822b509 | 930 | return 0; |
bade5622 DM |
931 | } |
932 | ||
33b07db9 | 933 | static int __devinit pci_sun4v_probe(struct of_device *op, |
3822b509 | 934 | const struct of_device_id *match) |
8f6a93a1 | 935 | { |
3822b509 | 936 | const struct linux_prom64_registers *regs; |
e01c0d6d | 937 | static int hvapi_negotiated = 0; |
34768bc8 | 938 | struct pci_pbm_info *pbm; |
3822b509 | 939 | struct device_node *dp; |
16ce82d8 | 940 | struct iommu *iommu; |
7c8f486a | 941 | u32 devhandle; |
d7472c38 | 942 | int i, err; |
3833789b | 943 | |
3822b509 DM |
944 | dp = op->node; |
945 | ||
e01c0d6d | 946 | if (!hvapi_negotiated++) { |
8d2aec51 DM |
947 | err = sun4v_hvapi_register(HV_GRP_PCI, |
948 | vpci_major, | |
949 | &vpci_minor); | |
e01c0d6d DM |
950 | |
951 | if (err) { | |
3822b509 DM |
952 | printk(KERN_ERR PFX "Could not register hvapi, " |
953 | "err=%d\n", err); | |
954 | return err; | |
e01c0d6d | 955 | } |
3822b509 | 956 | printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n", |
e01c0d6d | 957 | vpci_major, vpci_minor); |
ad7ad57c DM |
958 | |
959 | dma_ops = &sun4v_dma_ops; | |
e01c0d6d DM |
960 | } |
961 | ||
3822b509 | 962 | regs = of_get_property(dp, "reg", NULL); |
d7472c38 | 963 | err = -ENODEV; |
3822b509 DM |
964 | if (!regs) { |
965 | printk(KERN_ERR PFX "Could not find config registers\n"); | |
d7472c38 | 966 | goto out_err; |
75c6d141 | 967 | } |
e87dc350 | 968 | devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; |
3833789b | 969 | |
d7472c38 | 970 | err = -ENOMEM; |
d3ae4b5b DM |
971 | if (!iommu_batch_initialized) { |
972 | for_each_possible_cpu(i) { | |
973 | unsigned long page = get_zeroed_page(GFP_KERNEL); | |
7c8f486a | 974 | |
d3ae4b5b DM |
975 | if (!page) |
976 | goto out_err; | |
7c8f486a | 977 | |
d3ae4b5b DM |
978 | per_cpu(iommu_batch, i).pglist = (u64 *) page; |
979 | } | |
980 | iommu_batch_initialized = 1; | |
bade5622 | 981 | } |
7c8f486a | 982 | |
d3ae4b5b DM |
983 | pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
984 | if (!pbm) { | |
985 | printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n"); | |
d7472c38 | 986 | goto out_err; |
3822b509 | 987 | } |
7c8f486a | 988 | |
d3ae4b5b | 989 | iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); |
3822b509 | 990 | if (!iommu) { |
d3ae4b5b | 991 | printk(KERN_ERR PFX "Could not allocate pbm iommu\n"); |
d7472c38 | 992 | goto out_free_controller; |
3822b509 | 993 | } |
7c8f486a | 994 | |
d3ae4b5b | 995 | pbm->iommu = iommu; |
bade5622 | 996 | |
d3ae4b5b DM |
997 | err = pci_sun4v_pbm_init(pbm, op, devhandle); |
998 | if (err) | |
999 | goto out_free_iommu; | |
7c8f486a | 1000 | |
d3ae4b5b | 1001 | dev_set_drvdata(&op->dev, pbm); |
bade5622 | 1002 | |
d3ae4b5b | 1003 | return 0; |
7c8f486a | 1004 | |
d3ae4b5b DM |
1005 | out_free_iommu: |
1006 | kfree(pbm->iommu); | |
d7472c38 DM |
1007 | |
1008 | out_free_controller: | |
d3ae4b5b | 1009 | kfree(pbm); |
d7472c38 DM |
1010 | |
1011 | out_err: | |
1012 | return err; | |
8f6a93a1 | 1013 | } |
3822b509 | 1014 | |
fd098316 | 1015 | static struct of_device_id __initdata pci_sun4v_match[] = { |
3822b509 DM |
1016 | { |
1017 | .name = "pci", | |
1018 | .compatible = "SUNW,sun4v-pci", | |
1019 | }, | |
1020 | {}, | |
1021 | }; | |
1022 | ||
1023 | static struct of_platform_driver pci_sun4v_driver = { | |
1024 | .name = DRIVER_NAME, | |
1025 | .match_table = pci_sun4v_match, | |
1026 | .probe = pci_sun4v_probe, | |
1027 | }; | |
1028 | ||
1029 | static int __init pci_sun4v_init(void) | |
1030 | { | |
1031 | return of_register_driver(&pci_sun4v_driver, &of_bus_type); | |
1032 | } | |
1033 | ||
1034 | subsys_initcall(pci_sun4v_init); |