[deliverable/linux.git] / arch / sparc / kernel / sun4m_irq.c

/*
 * sun4m irq support
 *
 *  djhr: Hacked out of irq.c into a CPU dependent version.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
 *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
 *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
 */

#include <asm/timer.h>
#include <asm/traps.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/cacheflush.h>

#include "irq.h"
#include "kernel.h"

/* Sample sun4m IRQ layout:
 *
 * 0x22 - Power
 * 0x24 - ESP SCSI
 * 0x26 - Lance ethernet
 * 0x2b - Floppy
 * 0x2c - Zilog uart
 * 0x32 - SBUS level 0
 * 0x33 - Parallel port, SBUS level 1
 * 0x35 - SBUS level 2
 * 0x37 - SBUS level 3
 * 0x39 - Audio, Graphics card, SBUS level 4
 * 0x3b - SBUS level 5
 * 0x3d - SBUS level 6
 *
 * Each interrupt source has a mask bit in the interrupt registers.
 * When the mask bit is set, this blocks interrupt deliver.  So you
 * clear the bit to enable the interrupt.
 *
 * Interrupts numbered less than 0x10 are software triggered interrupts
 * and unused by Linux.
 *
 * Interrupt level assignment on sun4m:
 *
 *	level		source
 * ------------------------------------------------------------
 *	  1		softint-1
 *	  2		softint-2, VME/SBUS level 1
 *	  3		softint-3, VME/SBUS level 2
 *	  4		softint-4, onboard SCSI
 *	  5		softint-5, VME/SBUS level 3
 *	  6		softint-6, onboard ETHERNET
 *	  7		softint-7, VME/SBUS level 4
 *	  8		softint-8, onboard VIDEO
 *	  9		softint-9, VME/SBUS level 5, Module Interrupt
 *	 10		softint-10, system counter/timer
 *	 11		softint-11, VME/SBUS level 6, Floppy
 *	 12		softint-12, Keyboard/Mouse, Serial
 *	 13		softint-13, VME/SBUS level 7, ISDN Audio
 *	 14		softint-14, per-processor counter/timer
 *	 15		softint-15, Asynchronous Errors (broadcast)
 *
 * Each interrupt source is masked distinctly in the sun4m interrupt
 * registers.  The PIL level alone is therefore ambiguous, since multiple
 * interrupt sources map to a single PIL.
 *
 * This ambiguity is resolved in the 'intr' property for device nodes
 * in the OF device tree.  Each 'intr' property entry is composed of
 * two 32-bit words.  The first word is the IRQ priority value, which
 * is what we're intersted in.  The second word is the IRQ vector, which
 * is unused.
 *
 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled.  0x20
 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
 *
 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
 * whereas a value of 0x33 is SBUS level 2.  Here are some sample
 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
 * Tadpole S3 GX systems.
 *
 * esp:		0x24	onboard ESP SCSI
 * le:		0x26	onboard Lance ETHERNET
 * p9100:	0x32	SBUS level 1 P9100 video
 * bpp:		0x33	SBUS level 2 BPP parallel port device
 * DBRI:	0x39	SBUS level 5 DBRI ISDN audio
 * SUNW,leo:	0x39	SBUS level 5 LEO video
 * pcmcia:	0x3b	SBUS level 6 PCMCIA controller
 * uctrl:	0x3b	SBUS level 6 UCTRL device
 * modem:	0x3d	SBUS level 7 MODEM
 * zs:		0x2c	onboard keyboard/mouse/serial
 * floppy:	0x2b	onboard Floppy
 * power:	0x22	onboard power device (XXX unknown mask bit XXX)
 */


/* Code in entry.S needs to get at these register mappings.  */
struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
struct sun4m_irq_global __iomem *sun4m_irq_global;

struct sun4m_handler_data {
	bool    percpu;
	long    mask;
};

/* Dave Redman (djhr@tadpole.co.uk)
 * The sun4m interrupt registers.
 */
#define SUN4M_INT_ENABLE	0x80000000
#define SUN4M_INT_E14		0x00000080
#define SUN4M_INT_E10		0x00080000

#define SUN4M_HARD_INT(x)	(0x000000001 << (x))
#define SUN4M_SOFT_INT(x)	(0x000010000 << (x))

#define	SUN4M_INT_MASKALL	0x80000000	  /* mask all interrupts */
#define	SUN4M_INT_MODULE_ERR	0x40000000	  /* module error */
#define	SUN4M_INT_M2S_WRITE_ERR	0x20000000	  /* write buffer error */
#define	SUN4M_INT_ECC_ERR	0x10000000	  /* ecc memory error */
#define	SUN4M_INT_VME_ERR	0x08000000	  /* vme async error */
#define	SUN4M_INT_FLOPPY	0x00400000	  /* floppy disk */
#define	SUN4M_INT_MODULE	0x00200000	  /* module interrupt */
#define	SUN4M_INT_VIDEO		0x00100000	  /* onboard video */
#define	SUN4M_INT_REALTIME	0x00080000	  /* system timer */
#define	SUN4M_INT_SCSI		0x00040000	  /* onboard scsi */
#define	SUN4M_INT_AUDIO		0x00020000	  /* audio/isdn */
#define	SUN4M_INT_ETHERNET	0x00010000	  /* onboard ethernet */
#define	SUN4M_INT_SERIAL	0x00008000	  /* serial ports */
#define	SUN4M_INT_KBDMS		0x00004000	  /* keyboard/mouse */
#define	SUN4M_INT_SBUSBITS	0x00003F80	  /* sbus int bits */
#define	SUN4M_INT_VMEBITS	0x0000007F	  /* vme int bits */

#define	SUN4M_INT_ERROR		(SUN4M_INT_MODULE_ERR |    \
				 SUN4M_INT_M2S_WRITE_ERR | \
				 SUN4M_INT_ECC_ERR |       \
				 SUN4M_INT_VME_ERR)

#define SUN4M_INT_SBUS(x)	(1 << (x+7))
#define SUN4M_INT_VME(x)	(1 << (x))

/* Interrupt levels used by OBP */
#define	OBP_INT_LEVEL_SOFT	0x10
#define	OBP_INT_LEVEL_ONBOARD	0x20
#define	OBP_INT_LEVEL_SBUS	0x30
#define	OBP_INT_LEVEL_VME	0x40

#define SUN4M_TIMER_IRQ         (OBP_INT_LEVEL_ONBOARD | 10)
#define SUN4M_PROFILE_IRQ       (OBP_INT_LEVEL_ONBOARD | 14)

static unsigned long sun4m_imask[0x50] = {
	/* 0x00 - SMP */
	0,  SUN4M_SOFT_INT(1),
	SUN4M_SOFT_INT(2),  SUN4M_SOFT_INT(3),
	SUN4M_SOFT_INT(4),  SUN4M_SOFT_INT(5),
	SUN4M_SOFT_INT(6),  SUN4M_SOFT_INT(7),
	SUN4M_SOFT_INT(8),  SUN4M_SOFT_INT(9),
	SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
	SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
	SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
	/* 0x10 - soft */
	0,  SUN4M_SOFT_INT(1),
	SUN4M_SOFT_INT(2),  SUN4M_SOFT_INT(3),
	SUN4M_SOFT_INT(4),  SUN4M_SOFT_INT(5),
	SUN4M_SOFT_INT(6),  SUN4M_SOFT_INT(7),
	SUN4M_SOFT_INT(8),  SUN4M_SOFT_INT(9),
	SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
	SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
	SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
	/* 0x20 - onboard */
	0, 0, 0, 0,
	SUN4M_INT_SCSI,  0, SUN4M_INT_ETHERNET, 0,
	SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
	SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
	(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
	SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
	/* 0x30 - sbus */
	0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
	0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
	0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
	0, SUN4M_INT_SBUS(6), 0, 0,
	/* 0x40 - vme */
	0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
	0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
	0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
	0, SUN4M_INT_VME(6), 0, 0
};

static void sun4m_mask_irq(struct irq_data *data)
{
	struct sun4m_handler_data *handler_data = data->handler_data;
	int cpu = smp_processor_id();

	if (handler_data->mask) {
		unsigned long flags;

		local_irq_save(flags);
		if (handler_data->percpu) {
			sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
		} else {
			sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
		}
		local_irq_restore(flags);
	}
}

static void sun4m_unmask_irq(struct irq_data *data)
{
	struct sun4m_handler_data *handler_data = data->handler_data;
	int cpu = smp_processor_id();

	if (handler_data->mask) {
		unsigned long flags;

		local_irq_save(flags);
		if (handler_data->percpu) {
			sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
		} else {
			sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
		}
		local_irq_restore(flags);
	}
}

static unsigned int sun4m_startup_irq(struct irq_data *data)
{
	irq_link(data->irq);
	sun4m_unmask_irq(data);
	return 0;
}

static void sun4m_shutdown_irq(struct irq_data *data)
{
	sun4m_mask_irq(data);
	irq_unlink(data->irq);
}

static struct irq_chip sun4m_irq = {
	.name		= "sun4m",
	.irq_startup	= sun4m_startup_irq,
	.irq_shutdown	= sun4m_shutdown_irq,
	.irq_mask	= sun4m_mask_irq,
	.irq_unmask	= sun4m_unmask_irq,
};


static unsigned int sun4m_build_device_irq(struct platform_device *op,
					   unsigned int real_irq)
{
	struct sun4m_handler_data *handler_data;
	unsigned int irq;
	unsigned int pil;

	if (real_irq >= OBP_INT_LEVEL_VME) {
		prom_printf("Bogus sun4m IRQ %u\n", real_irq);
		prom_halt();
	}
	pil = (real_irq & 0xf);
	irq = irq_alloc(real_irq, pil);

	if (irq == 0)
		goto out;

	handler_data = irq_get_handler_data(irq);
	if (unlikely(handler_data))
		goto out;

	handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
	if (unlikely(!handler_data)) {
		prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
		prom_halt();
	}

	handler_data->mask = sun4m_imask[real_irq];
	handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
	irq_set_chip_and_handler_name(irq, &sun4m_irq,
	                              handle_level_irq, "level");
	irq_set_handler_data(irq, handler_data);

out:
	return irq;
}

#ifdef CONFIG_SMP
static void sun4m_send_ipi(int cpu, int level)
{
	sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
}

static void sun4m_clear_ipi(int cpu, int level)
{
	sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->clear);
}

static void sun4m_set_udt(int cpu)
{
	sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
}
#endif

struct sun4m_timer_percpu {
	u32		l14_limit;
	u32		l14_count;
	u32		l14_limit_noclear;
	u32		user_timer_start_stop;
};

static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];

struct sun4m_timer_global {
	u32		l10_limit;
	u32		l10_count;
	u32		l10_limit_noclear;
	u32		reserved;
	u32		timer_config;
};

static struct sun4m_timer_global __iomem *timers_global;


unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);

static void sun4m_clear_clock_irq(void)
{
	sbus_readl(&timers_global->l10_limit);
}

void sun4m_nmi(struct pt_regs *regs)
{
	unsigned long afsr, afar, si;

	printk(KERN_ERR "Aieee: sun4m NMI received!\n");
	/* XXX HyperSparc hack XXX */
	__asm__ __volatile__("mov 0x500, %%g1\n\t"
			     "lda [%%g1] 0x4, %0\n\t"
			     "mov 0x600, %%g1\n\t"
			     "lda [%%g1] 0x4, %1\n\t" :
			     "=r" (afsr), "=r" (afar));
	printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
	si = sbus_readl(&sun4m_irq_global->pending);
	printk(KERN_ERR "si=%08lx\n", si);
	if (si & SUN4M_INT_MODULE_ERR)
		printk(KERN_ERR "Module async error\n");
	if (si & SUN4M_INT_M2S_WRITE_ERR)
		printk(KERN_ERR "MBus/SBus async error\n");
	if (si & SUN4M_INT_ECC_ERR)
		printk(KERN_ERR "ECC memory error\n");
	if (si & SUN4M_INT_VME_ERR)
		printk(KERN_ERR "VME async error\n");
	printk(KERN_ERR "you lose buddy boy...\n");
	show_regs(regs);
	prom_halt();
}

void sun4m_unmask_profile_irq(void)
{
	unsigned long flags;

	local_irq_save(flags);
	sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
	local_irq_restore(flags);
}

void sun4m_clear_profile_irq(int cpu)
{
	sbus_readl(&timers_percpu[cpu]->l14_limit);
}

static void sun4m_load_profile_irq(int cpu, unsigned int limit)
{
	sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
}

static void __init sun4m_init_timers(irq_handler_t counter_fn)
{
	struct device_node *dp = of_find_node_by_name(NULL, "counter");
	int i, err, len, num_cpu_timers;
	unsigned int irq;
	const u32 *addr;

	if (!dp) {
		printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
		return;
	}

	addr = of_get_property(dp, "address", &len);
	of_node_put(dp);
	if (!addr) {
		printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
		return;
	}

	num_cpu_timers = (len / sizeof(u32)) - 1;
	for (i = 0; i < num_cpu_timers; i++) {
		timers_percpu[i] = (void __iomem *)
			(unsigned long) addr[i];
	}
	timers_global = (void __iomem *)
		(unsigned long) addr[num_cpu_timers];

	/* Every per-cpu timer works in timer mode */
	sbus_writel(0x00000000, &timers_global->timer_config);

	sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);

	master_l10_counter = &timers_global->l10_count;

	irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);

	err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
	if (err) {
		printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
			err);
		return;
	}

	for (i = 0; i < num_cpu_timers; i++)
		sbus_writel(0, &timers_percpu[i]->l14_limit);
	if (num_cpu_timers == 4)
		sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);

#ifdef CONFIG_SMP
	{
		unsigned long flags;
		struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];

		/* For SMP we use the level 14 ticker, however the bootup code
		 * has copied the firmware's level 14 vector into the boot cpu's
		 * trap table, we must fix this now or we get squashed.
		 */
		local_irq_save(flags);
		trap_table->inst_one = lvl14_save[0];
		trap_table->inst_two = lvl14_save[1];
		trap_table->inst_three = lvl14_save[2];
		trap_table->inst_four = lvl14_save[3];
		local_flush_cache_all();
		local_irq_restore(flags);
	}
#endif
}

void __init sun4m_init_IRQ(void)
{
	struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
	int len, i, mid, num_cpu_iregs;
	const u32 *addr;

	if (!dp) {
		printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
		return;
	}

	addr = of_get_property(dp, "address", &len);
	of_node_put(dp);
	if (!addr) {
		printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
		return;
	}

	num_cpu_iregs = (len / sizeof(u32)) - 1;
	for (i = 0; i < num_cpu_iregs; i++) {
		sun4m_irq_percpu[i] = (void __iomem *)
			(unsigned long) addr[i];
	}
	sun4m_irq_global = (void __iomem *)
		(unsigned long) addr[num_cpu_iregs];

	local_irq_disable();

	sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
	for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
		sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);

	if (num_cpu_iregs == 4)
		sbus_writel(0, &sun4m_irq_global->interrupt_target);

	BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);

	sparc_irq_config.init_timers = sun4m_init_timers;
	sparc_irq_config.build_device_irq = sun4m_build_device_irq;

#ifdef CONFIG_SMP
	BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
#endif

	/* Cannot enable interrupts until OBP ticker is disabled. */
}
Commit	Line	Data
aba20a82 SR	1	/*
aba20a82 SR	2	* sun4m irq support
1da177e4 LT	3	*
	4	* djhr: Hacked out of irq.c into a CPU dependent version.
	5	*
	6	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	7	* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
	8	* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
	9	* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
	10	*/
	11
1da177e4	12	#include <asm/timer.h>
1da177e4 LT	13	#include <asm/traps.h>
	14	#include <asm/pgalloc.h>
	15	#include <asm/pgtable.h>
1da177e4 LT	16	#include <asm/irq.h>
1da177e4 LT	17	#include <asm/io.h>
1da177e4 LT	18	#include <asm/cacheflush.h>
1da177e4 LT	19
32231a66	20	#include "irq.h"
aba20a82 SR	21	#include "kernel.h"
	22
	23	/* Sample sun4m IRQ layout:
	24	*
	25	* 0x22 - Power
	26	* 0x24 - ESP SCSI
	27	* 0x26 - Lance ethernet
	28	* 0x2b - Floppy
	29	* 0x2c - Zilog uart
	30	* 0x32 - SBUS level 0
	31	* 0x33 - Parallel port, SBUS level 1
	32	* 0x35 - SBUS level 2
	33	* 0x37 - SBUS level 3
	34	* 0x39 - Audio, Graphics card, SBUS level 4
	35	* 0x3b - SBUS level 5
	36	* 0x3d - SBUS level 6
	37	*
	38	* Each interrupt source has a mask bit in the interrupt registers.
	39	* When the mask bit is set, this blocks interrupt deliver. So you
	40	* clear the bit to enable the interrupt.
	41	*
	42	* Interrupts numbered less than 0x10 are software triggered interrupts
	43	* and unused by Linux.
	44	*
	45	* Interrupt level assignment on sun4m:
	46	*
	47	* level source
	48	* ------------------------------------------------------------
	49	* 1 softint-1
	50	* 2 softint-2, VME/SBUS level 1
	51	* 3 softint-3, VME/SBUS level 2
	52	* 4 softint-4, onboard SCSI
	53	* 5 softint-5, VME/SBUS level 3
	54	* 6 softint-6, onboard ETHERNET
	55	* 7 softint-7, VME/SBUS level 4
	56	* 8 softint-8, onboard VIDEO
	57	* 9 softint-9, VME/SBUS level 5, Module Interrupt
	58	* 10 softint-10, system counter/timer
	59	* 11 softint-11, VME/SBUS level 6, Floppy
	60	* 12 softint-12, Keyboard/Mouse, Serial
	61	* 13 softint-13, VME/SBUS level 7, ISDN Audio
	62	* 14 softint-14, per-processor counter/timer
	63	* 15 softint-15, Asynchronous Errors (broadcast)
	64	*
	65	* Each interrupt source is masked distinctly in the sun4m interrupt
	66	* registers. The PIL level alone is therefore ambiguous, since multiple
	67	* interrupt sources map to a single PIL.
	68	*
	69	* This ambiguity is resolved in the 'intr' property for device nodes
	70	* in the OF device tree. Each 'intr' property entry is composed of
	71	* two 32-bit words. The first word is the IRQ priority value, which
	72	* is what we're intersted in. The second word is the IRQ vector, which
	73	* is unused.
	74	*
	75	* The low 4 bits of the IRQ priority indicate the PIL, and the upper
	76	* 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
	77	* means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
	78	*
	79	* For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
	80	* whereas a value of 0x33 is SBUS level 2. Here are some sample
	81	* 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
	82	* Tadpole S3 GX systems.
	83	*
	84	* esp: 0x24 onboard ESP SCSI
85	* le: 0x26 onboard Lance ETHERNET
86	* p9100: 0x32 SBUS level 1 P9100 video
87	* bpp: 0x33 SBUS level 2 BPP parallel port device
88	* DBRI: 0x39 SBUS level 5 DBRI ISDN audio
89	* SUNW,leo: 0x39 SBUS level 5 LEO video
90	* pcmcia: 0x3b SBUS level 6 PCMCIA controller
91	* uctrl: 0x3b SBUS level 6 UCTRL device
92	* modem: 0x3d SBUS level 7 MODEM
93	* zs: 0x2c onboard keyboard/mouse/serial
94	* floppy: 0x2b onboard Floppy
95	* power: 0x22 onboard power device (XXX unknown mask bit XXX)
96	*/
97
32231a66	98
69c010b2 DM	99	/* Code in entry.S needs to get at these register mappings. */
	100	struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
	101	struct sun4m_irq_global __iomem *sun4m_irq_global;
1da177e4	102
6baa9b20 SR	103	struct sun4m_handler_data {
	104	bool percpu;
	105	long mask;
	106	};
	107
32231a66 AV	108	/* Dave Redman (djhr@tadpole.co.uk)
	109	* The sun4m interrupt registers.
	110	*/
aba20a82 SR	111	#define SUN4M_INT_ENABLE 0x80000000
	112	#define SUN4M_INT_E14 0x00000080
	113	#define SUN4M_INT_E10 0x00080000
32231a66 AV	114
	115	#define SUN4M_HARD_INT(x) (0x000000001 << (x))
	116	#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
	117
	118	#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
	119	#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
6cf4a924 RR	120	#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
	121	#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
	122	#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
32231a66 AV	123	#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
	124	#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
	125	#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
	126	#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
	127	#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
	128	#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
	129	#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
	130	#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
	131	#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
	132	#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
6cf4a924 RR	133	#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
	134
	135	#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR \| \
	136	SUN4M_INT_M2S_WRITE_ERR \| \
	137	SUN4M_INT_ECC_ERR \| \
	138	SUN4M_INT_VME_ERR)
32231a66 AV	139
	140	#define SUN4M_INT_SBUS(x) (1 << (x+7))
	141	#define SUN4M_INT_VME(x) (1 << (x))
	142
6cf4a924 RR	143	/* Interrupt levels used by OBP */
	144	#define OBP_INT_LEVEL_SOFT 0x10
	145	#define OBP_INT_LEVEL_ONBOARD 0x20
	146	#define OBP_INT_LEVEL_SBUS 0x30
	147	#define OBP_INT_LEVEL_VME 0x40
	148
0399bb5b	149	#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD \| 10)
6baa9b20	150	#define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD \| 14)
0399bb5b	151
6baa9b20	152	static unsigned long sun4m_imask[0x50] = {
0399bb5b	153	/* 0x00 - SMP */
6cf4a924 RR	154	0, SUN4M_SOFT_INT(1),
	155	SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
	156	SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
	157	SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
	158	SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
	159	SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
	160	SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
	161	SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
0399bb5b	162	/* 0x10 - soft */
6cf4a924 RR	163	0, SUN4M_SOFT_INT(1),
	164	SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
	165	SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
	166	SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
	167	SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
	168	SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
	169	SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
	170	SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
0399bb5b	171	/* 0x20 - onboard */
6cf4a924 RR	172	0, 0, 0, 0,
	173	SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
	174	SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
	175	SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
	176	(SUN4M_INT_SERIAL \| SUN4M_INT_KBDMS),
6baa9b20	177	SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
0399bb5b	178	/* 0x30 - sbus */
6cf4a924 RR	179	0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
	180	0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
	181	0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
	182	0, SUN4M_INT_SBUS(6), 0, 0,
0399bb5b	183	/* 0x40 - vme */
6cf4a924 RR	184	0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
	185	0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
	186	0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
	187	0, SUN4M_INT_VME(6), 0, 0
1da177e4 LT	188	};
1da177e4 LT	189
6baa9b20	190	static void sun4m_mask_irq(struct irq_data *data)
1da177e4	191	{
6baa9b20 SR	192	struct sun4m_handler_data *handler_data = data->handler_data;
6baa9b20 SR	193	int cpu = smp_processor_id();
6cf4a924	194
6baa9b20 SR	195	if (handler_data->mask) {
6baa9b20 SR	196	unsigned long flags;
6cf4a924	197
6baa9b20 SR	198	local_irq_save(flags);
	199	if (handler_data->percpu) {
	200	sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
	201	} else {
	202	sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
	203	}
	204	local_irq_restore(flags);
	205	}
1da177e4 LT	206	}
1da177e4 LT	207
6baa9b20	208	static void sun4m_unmask_irq(struct irq_data *data)
1da177e4	209	{
6baa9b20	210	struct sun4m_handler_data *handler_data = data->handler_data;
1da177e4 LT	211	int cpu = smp_processor_id();
1da177e4 LT	212
6baa9b20 SR	213	if (handler_data->mask) {
6baa9b20 SR	214	unsigned long flags;
1da177e4	215
1da177e4	216	local_irq_save(flags);
6baa9b20 SR	217	if (handler_data->percpu) {
	218	sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
	219	} else {
	220	sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
	221	}
1da177e4 LT	222	local_irq_restore(flags);
	223	}
	224	}
	225
6baa9b20 SR	226	static unsigned int sun4m_startup_irq(struct irq_data *data)
	227	{
	228	irq_link(data->irq);
	229	sun4m_unmask_irq(data);
	230	return 0;
	231	}
1da177e4	232
6baa9b20	233	static void sun4m_shutdown_irq(struct irq_data *data)
1da177e4	234	{
6baa9b20 SR	235	sun4m_mask_irq(data);
6baa9b20 SR	236	irq_unlink(data->irq);
1da177e4 LT	237	}
1da177e4 LT	238
6baa9b20 SR	239	static struct irq_chip sun4m_irq = {
	240	.name = "sun4m",
	241	.irq_startup = sun4m_startup_irq,
	242	.irq_shutdown = sun4m_shutdown_irq,
	243	.irq_mask = sun4m_mask_irq,
	244	.irq_unmask = sun4m_unmask_irq,
	245	};
	246
	247
	248	static unsigned int sun4m_build_device_irq(struct platform_device *op,
	249	unsigned int real_irq)
1da177e4	250	{
6baa9b20 SR	251	struct sun4m_handler_data *handler_data;
	252	unsigned int irq;
	253	unsigned int pil;
	254
	255	if (real_irq >= OBP_INT_LEVEL_VME) {
	256	prom_printf("Bogus sun4m IRQ %u\n", real_irq);
	257	prom_halt();
	258	}
	259	pil = (real_irq & 0xf);
	260	irq = irq_alloc(real_irq, pil);
	261
	262	if (irq == 0)
	263	goto out;
	264
	265	handler_data = irq_get_handler_data(irq);
	266	if (unlikely(handler_data))
	267	goto out;
	268
	269	handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
	270	if (unlikely(!handler_data)) {
	271	prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
	272	prom_halt();
	273	}
	274
	275	handler_data->mask = sun4m_imask[real_irq];
	276	handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
	277	irq_set_chip_and_handler_name(irq, &sun4m_irq,
	278	handle_level_irq, "level");
	279	irq_set_handler_data(irq, handler_data);
	280
	281	out:
	282	return irq;
1da177e4 LT	283	}
	284
	285	#ifdef CONFIG_SMP
	286	static void sun4m_send_ipi(int cpu, int level)
	287	{
6baa9b20	288	sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
1da177e4 LT	289	}
	290
	291	static void sun4m_clear_ipi(int cpu, int level)
	292	{
6baa9b20	293	sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->clear);
1da177e4 LT	294	}
	295
	296	static void sun4m_set_udt(int cpu)
	297	{
69c010b2	298	sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
1da177e4 LT	299	}
	300	#endif
	301
9b2e43ae DM	302	struct sun4m_timer_percpu {
	303	u32 l14_limit;
	304	u32 l14_count;
	305	u32 l14_limit_noclear;
	306	u32 user_timer_start_stop;
	307	};
	308
	309	static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
	310
	311	struct sun4m_timer_global {
	312	u32 l10_limit;
	313	u32 l10_count;
	314	u32 l10_limit_noclear;
	315	u32 reserved;
	316	u32 timer_config;
	317	};
	318
	319	static struct sun4m_timer_global __iomem *timers_global;
	320
1da177e4	321
1da177e4 LT	322	unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
	323
	324	static void sun4m_clear_clock_irq(void)
	325	{
9b2e43ae	326	sbus_readl(&timers_global->l10_limit);
1da177e4 LT	327	}
1da177e4 LT	328
6cf4a924 RR	329	void sun4m_nmi(struct pt_regs *regs)
	330	{
	331	unsigned long afsr, afar, si;
	332
	333	printk(KERN_ERR "Aieee: sun4m NMI received!\n");
	334	/* XXX HyperSparc hack XXX */
	335	__asm__ __volatile__("mov 0x500, %%g1\n\t"
	336	"lda [%%g1] 0x4, %0\n\t"
	337	"mov 0x600, %%g1\n\t"
	338	"lda [%%g1] 0x4, %1\n\t" :
	339	"=r" (afsr), "=r" (afar));
	340	printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
	341	si = sbus_readl(&sun4m_irq_global->pending);
	342	printk(KERN_ERR "si=%08lx\n", si);
	343	if (si & SUN4M_INT_MODULE_ERR)
	344	printk(KERN_ERR "Module async error\n");
	345	if (si & SUN4M_INT_M2S_WRITE_ERR)
	346	printk(KERN_ERR "MBus/SBus async error\n");
	347	if (si & SUN4M_INT_ECC_ERR)
	348	printk(KERN_ERR "ECC memory error\n");
	349	if (si & SUN4M_INT_VME_ERR)
	350	printk(KERN_ERR "VME async error\n");
	351	printk(KERN_ERR "you lose buddy boy...\n");
	352	show_regs(regs);
	353	prom_halt();
	354	}
	355
6baa9b20 SR	356	void sun4m_unmask_profile_irq(void)
	357	{
	358	unsigned long flags;
	359
	360	local_irq_save(flags);
	361	sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
	362	local_irq_restore(flags);
	363	}
	364
1de937a5	365	void sun4m_clear_profile_irq(int cpu)
1da177e4	366	{
9b2e43ae	367	sbus_readl(&timers_percpu[cpu]->l14_limit);
1da177e4 LT	368	}
	369
	370	static void sun4m_load_profile_irq(int cpu, unsigned int limit)
	371	{
9b2e43ae	372	sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
1da177e4 LT	373	}
1da177e4 LT	374
40220c1a	375	static void __init sun4m_init_timers(irq_handler_t counter_fn)
1da177e4	376	{
9b2e43ae DM	377	struct device_node *dp = of_find_node_by_name(NULL, "counter");
9b2e43ae DM	378	int i, err, len, num_cpu_timers;
6baa9b20	379	unsigned int irq;
9b2e43ae DM	380	const u32 *addr;
	381
	382	if (!dp) {
	383	printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
	384	return;
1da177e4	385	}
9b2e43ae DM	386
9b2e43ae DM	387	addr = of_get_property(dp, "address", &len);
c2e27c35	388	of_node_put(dp);
9b2e43ae DM	389	if (!addr) {
	390	printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
	391	return;
1da177e4 LT	392	}
1da177e4 LT	393
9b2e43ae DM	394	num_cpu_timers = (len / sizeof(u32)) - 1;
	395	for (i = 0; i < num_cpu_timers; i++) {
	396	timers_percpu[i] = (void __iomem *)
	397	(unsigned long) addr[i];
1da177e4	398	}
9b2e43ae DM	399	timers_global = (void __iomem *)
	400	(unsigned long) addr[num_cpu_timers];
	401
e51e07e0 TK	402	/* Every per-cpu timer works in timer mode */
	403	sbus_writel(0x00000000, &timers_global->timer_config);
	404
9b2e43ae DM	405	sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
	406
	407	master_l10_counter = &timers_global->l10_count;
9b2e43ae	408
6baa9b20 SR	409	irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
	410
	411	err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
9b2e43ae DM	412	if (err) {
	413	printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
	414	err);
	415	return;
1da177e4	416	}
9b2e43ae DM	417
	418	for (i = 0; i < num_cpu_timers; i++)
	419	sbus_writel(0, &timers_percpu[i]->l14_limit);
	420	if (num_cpu_timers == 4)
69c010b2	421	sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
9b2e43ae	422
1da177e4 LT	423	#ifdef CONFIG_SMP
	424	{
	425	unsigned long flags;
1da177e4 LT	426	struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
	427
	428	/* For SMP we use the level 14 ticker, however the bootup code
d1a78c32	429	* has copied the firmware's level 14 vector into the boot cpu's
1da177e4 LT	430	* trap table, we must fix this now or we get squashed.
	431	*/
	432	local_irq_save(flags);
	433	trap_table->inst_one = lvl14_save[0];
	434	trap_table->inst_two = lvl14_save[1];
	435	trap_table->inst_three = lvl14_save[2];
	436	trap_table->inst_four = lvl14_save[3];
	437	local_flush_cache_all();
	438	local_irq_restore(flags);
	439	}
	440	#endif
	441	}
	442
	443	void __init sun4m_init_IRQ(void)
	444	{
69c010b2 DM	445	struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
	446	int len, i, mid, num_cpu_iregs;
	447	const u32 *addr;
	448
	449	if (!dp) {
	450	printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
	451	return;
1da177e4	452	}
69c010b2 DM	453
69c010b2 DM	454	addr = of_get_property(dp, "address", &len);
c2e27c35	455	of_node_put(dp);
69c010b2 DM	456	if (!addr) {
	457	printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
	458	return;
1da177e4 LT	459	}
1da177e4 LT	460
69c010b2 DM	461	num_cpu_iregs = (len / sizeof(u32)) - 1;
	462	for (i = 0; i < num_cpu_iregs; i++) {
	463	sun4m_irq_percpu[i] = (void __iomem *)
	464	(unsigned long) addr[i];
	465	}
	466	sun4m_irq_global = (void __iomem *)
	467	(unsigned long) addr[num_cpu_iregs];
1da177e4	468
69c010b2	469	local_irq_disable();
1da177e4	470
69c010b2	471	sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
1da177e4	472	for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
69c010b2 DM	473	sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
69c010b2 DM	474
e7913de9	475	if (num_cpu_iregs == 4)
69c010b2	476	sbus_writel(0, &sun4m_irq_global->interrupt_target);
e7913de9	477
1da177e4	478	BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
1da177e4	479	BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
bbdc2661 SR	480
bbdc2661 SR	481	sparc_irq_config.init_timers = sun4m_init_timers;
6baa9b20	482	sparc_irq_config.build_device_irq = sun4m_build_device_irq;
bbdc2661	483
1da177e4 LT	484	#ifdef CONFIG_SMP
	485	BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
	486	BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
	487	BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
	488	#endif
69c010b2	489
1da177e4 LT	490	/* Cannot enable interrupts until OBP ticker is disabled. */
1da177e4 LT	491	}