Commit | Line | Data |
---|---|---|
aba20a82 SR |
1 | /* |
2 | * sun4m SMP support. | |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | */ | |
6 | ||
62f08283 | 7 | #include <linux/clockchips.h> |
1da177e4 | 8 | #include <linux/interrupt.h> |
1da177e4 | 9 | #include <linux/profile.h> |
6c81c32f | 10 | #include <linux/delay.h> |
5d83d666 | 11 | #include <linux/sched.h> |
4245e59d | 12 | #include <linux/cpu.h> |
6c81c32f | 13 | |
1da177e4 | 14 | #include <asm/cacheflush.h> |
bde4d8b2 | 15 | #include <asm/switch_to.h> |
1da177e4 | 16 | #include <asm/tlbflush.h> |
62f08283 | 17 | #include <asm/timer.h> |
5d83d666 | 18 | #include <asm/oplib.h> |
1da177e4 | 19 | |
32231a66 | 20 | #include "irq.h" |
aba20a82 | 21 | #include "kernel.h" |
32231a66 | 22 | |
ecbc42b7 DH |
23 | #define IRQ_IPI_SINGLE 12 |
24 | #define IRQ_IPI_MASK 13 | |
25 | #define IRQ_IPI_RESCHED 14 | |
1da177e4 LT |
26 | #define IRQ_CROSS_CALL 15 |
27 | ||
1a8a27c9 WF |
28 | static inline unsigned long |
29 | swap_ulong(volatile unsigned long *ptr, unsigned long val) | |
1da177e4 LT |
30 | { |
31 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
32 | "=&r" (val), "=&r" (ptr) : | |
33 | "0" (val), "1" (ptr)); | |
34 | return val; | |
35 | } | |
36 | ||
2066aadd | 37 | void sun4m_cpu_pre_starting(void *arg) |
1da177e4 | 38 | { |
f9fd3488 | 39 | } |
1da177e4 | 40 | |
2066aadd | 41 | void sun4m_cpu_pre_online(void *arg) |
f9fd3488 SR |
42 | { |
43 | int cpuid = hard_smp_processor_id(); | |
1da177e4 | 44 | |
f9fd3488 SR |
45 | /* Allow master to continue. The master will then give us the |
46 | * go-ahead by setting the smp_commenced_mask and will wait without | |
47 | * timeouts until our setup is completed fully (signified by | |
48 | * our bit being set in the cpu_online_mask). | |
1da177e4 | 49 | */ |
1a8a27c9 | 50 | swap_ulong(&cpu_callin_map[cpuid], 1); |
1da177e4 | 51 | |
a54123e2 | 52 | /* XXX: What's up with all the flushes? */ |
5d83d666 DM |
53 | local_ops->cache_all(); |
54 | local_ops->tlb_all(); | |
aba20a82 | 55 | |
1da177e4 LT |
56 | /* Fix idle thread fields. */ |
57 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
58 | : : "r" (¤t_set[cpuid]) | |
59 | : "memory" /* paranoid */); | |
60 | ||
61 | /* Attach to the address space of init_task. */ | |
62 | atomic_inc(&init_mm.mm_count); | |
63 | current->active_mm = &init_mm; | |
64 | ||
fb1fece5 | 65 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
a54123e2 | 66 | mb(); |
1da177e4 LT |
67 | } |
68 | ||
1da177e4 LT |
69 | /* |
70 | * Cycle through the processors asking the PROM to start each one. | |
71 | */ | |
1da177e4 LT |
72 | void __init smp4m_boot_cpus(void) |
73 | { | |
62f08283 | 74 | sun4m_unmask_profile_irq(); |
5d83d666 | 75 | local_ops->cache_all(); |
a54123e2 | 76 | } |
1da177e4 | 77 | |
2066aadd | 78 | int smp4m_boot_one_cpu(int i, struct task_struct *idle) |
a54123e2 | 79 | { |
a54123e2 | 80 | unsigned long *entry = &sun4m_cpu_startup; |
a54123e2 BB |
81 | int timeout; |
82 | int cpu_node; | |
1da177e4 | 83 | |
a54123e2 | 84 | cpu_find_by_mid(i, &cpu_node); |
f0a2bc7e | 85 | current_set[i] = task_thread_info(idle); |
a54123e2 | 86 | |
a54123e2 | 87 | /* See trampoline.S for details... */ |
aba20a82 | 88 | entry += ((i - 1) * 3); |
1da177e4 | 89 | |
a54123e2 BB |
90 | /* |
91 | * Initialize the contexts table | |
92 | * Since the call to prom_startcpu() trashes the structure, | |
93 | * we need to re-initialize it for each cpu | |
94 | */ | |
95 | smp_penguin_ctable.which_io = 0; | |
96 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
97 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 98 | |
a54123e2 | 99 | /* whirrr, whirrr, whirrrrrrrrr... */ |
aba20a82 | 100 | printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); |
5d83d666 | 101 | local_ops->cache_all(); |
aba20a82 | 102 | prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); |
a54123e2 BB |
103 | |
104 | /* wheee... it's going... */ | |
aba20a82 SR |
105 | for (timeout = 0; timeout < 10000; timeout++) { |
106 | if (cpu_callin_map[i]) | |
a54123e2 BB |
107 | break; |
108 | udelay(200); | |
1da177e4 LT |
109 | } |
110 | ||
a54123e2 | 111 | if (!(cpu_callin_map[i])) { |
aba20a82 | 112 | printk(KERN_ERR "Processor %d is stuck.\n", i); |
a54123e2 BB |
113 | return -ENODEV; |
114 | } | |
1da177e4 | 115 | |
5d83d666 | 116 | local_ops->cache_all(); |
a54123e2 BB |
117 | return 0; |
118 | } | |
119 | ||
120 | void __init smp4m_smp_done(void) | |
121 | { | |
122 | int i, first; | |
123 | int *prev; | |
124 | ||
125 | /* setup cpu list for irq rotation */ | |
126 | first = 0; | |
127 | prev = &first; | |
ec7c14bd RR |
128 | for_each_online_cpu(i) { |
129 | *prev = i; | |
130 | prev = &cpu_data(i).next; | |
1da177e4 | 131 | } |
a54123e2 | 132 | *prev = first; |
5d83d666 | 133 | local_ops->cache_all(); |
1da177e4 | 134 | |
1da177e4 | 135 | /* Ok, they are spinning and ready to go. */ |
1da177e4 LT |
136 | } |
137 | ||
4ba22b16 | 138 | static void sun4m_send_ipi(int cpu, int level) |
ecbc42b7 | 139 | { |
4ba22b16 | 140 | sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set); |
ecbc42b7 DH |
141 | } |
142 | ||
4ba22b16 | 143 | static void sun4m_ipi_resched(int cpu) |
ecbc42b7 | 144 | { |
4ba22b16 | 145 | sun4m_send_ipi(cpu, IRQ_IPI_RESCHED); |
ecbc42b7 DH |
146 | } |
147 | ||
4ba22b16 | 148 | static void sun4m_ipi_single(int cpu) |
ecbc42b7 | 149 | { |
4ba22b16 | 150 | sun4m_send_ipi(cpu, IRQ_IPI_SINGLE); |
ecbc42b7 DH |
151 | } |
152 | ||
4ba22b16 | 153 | static void sun4m_ipi_mask_one(int cpu) |
ecbc42b7 | 154 | { |
4ba22b16 | 155 | sun4m_send_ipi(cpu, IRQ_IPI_MASK); |
ecbc42b7 DH |
156 | } |
157 | ||
1da177e4 LT |
158 | static struct smp_funcall { |
159 | smpfunc_t func; | |
160 | unsigned long arg1; | |
161 | unsigned long arg2; | |
162 | unsigned long arg3; | |
163 | unsigned long arg4; | |
164 | unsigned long arg5; | |
a54123e2 BB |
165 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
166 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
167 | } ccall_info; |
168 | ||
169 | static DEFINE_SPINLOCK(cross_call_lock); | |
170 | ||
171 | /* Cross calls must be serialized, at least currently. */ | |
4ba22b16 | 172 | static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 173 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 174 | unsigned long arg4) |
1da177e4 | 175 | { |
a54123e2 | 176 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
177 | unsigned long flags; |
178 | ||
179 | spin_lock_irqsave(&cross_call_lock, flags); | |
180 | ||
181 | /* Init function glue. */ | |
182 | ccall_info.func = func; | |
183 | ccall_info.arg1 = arg1; | |
184 | ccall_info.arg2 = arg2; | |
185 | ccall_info.arg3 = arg3; | |
186 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 187 | ccall_info.arg5 = 0; |
1da177e4 LT |
188 | |
189 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
190 | { | |
1da177e4 LT |
191 | register int i; |
192 | ||
fb1fece5 KM |
193 | cpumask_clear_cpu(smp_processor_id(), &mask); |
194 | cpumask_and(&mask, cpu_online_mask, &mask); | |
aba20a82 | 195 | for (i = 0; i < ncpus; i++) { |
fb1fece5 | 196 | if (cpumask_test_cpu(i, &mask)) { |
1da177e4 LT |
197 | ccall_info.processors_in[i] = 0; |
198 | ccall_info.processors_out[i] = 0; | |
4ba22b16 | 199 | sun4m_send_ipi(i, IRQ_CROSS_CALL); |
1da177e4 LT |
200 | } else { |
201 | ccall_info.processors_in[i] = 1; | |
202 | ccall_info.processors_out[i] = 1; | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
207 | { | |
208 | register int i; | |
209 | ||
210 | i = 0; | |
211 | do { | |
fb1fece5 | 212 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 213 | continue; |
aba20a82 | 214 | while (!ccall_info.processors_in[i]) |
1da177e4 | 215 | barrier(); |
aba20a82 | 216 | } while (++i < ncpus); |
1da177e4 LT |
217 | |
218 | i = 0; | |
219 | do { | |
fb1fece5 | 220 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 221 | continue; |
aba20a82 | 222 | while (!ccall_info.processors_out[i]) |
1da177e4 | 223 | barrier(); |
aba20a82 | 224 | } while (++i < ncpus); |
1da177e4 | 225 | } |
1da177e4 | 226 | spin_unlock_irqrestore(&cross_call_lock, flags); |
1da177e4 LT |
227 | } |
228 | ||
229 | /* Running cross calls. */ | |
230 | void smp4m_cross_call_irq(void) | |
231 | { | |
232 | int i = smp_processor_id(); | |
233 | ||
234 | ccall_info.processors_in[i] = 1; | |
235 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
236 | ccall_info.arg4, ccall_info.arg5); | |
237 | ccall_info.processors_out[i] = 1; | |
238 | } | |
239 | ||
240 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) | |
241 | { | |
0d84438d | 242 | struct pt_regs *old_regs; |
62f08283 | 243 | struct clock_event_device *ce; |
1da177e4 LT |
244 | int cpu = smp_processor_id(); |
245 | ||
0d84438d AV |
246 | old_regs = set_irq_regs(regs); |
247 | ||
62f08283 | 248 | ce = &per_cpu(sparc32_clockevent, cpu); |
1da177e4 | 249 | |
ff4aea45 | 250 | if (clockevent_state_periodic(ce)) |
62f08283 TK |
251 | sun4m_clear_profile_irq(cpu); |
252 | else | |
08c9388f | 253 | sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */ |
1da177e4 | 254 | |
62f08283 TK |
255 | irq_enter(); |
256 | ce->event_handler(ce); | |
257 | irq_exit(); | |
1da177e4 | 258 | |
0d84438d | 259 | set_irq_regs(old_regs); |
1da177e4 LT |
260 | } |
261 | ||
4ba22b16 SR |
262 | static const struct sparc32_ipi_ops sun4m_ipi_ops = { |
263 | .cross_call = sun4m_cross_call, | |
264 | .resched = sun4m_ipi_resched, | |
265 | .single = sun4m_ipi_single, | |
266 | .mask_one = sun4m_ipi_mask_one, | |
267 | }; | |
268 | ||
1da177e4 LT |
269 | void __init sun4m_init_smp(void) |
270 | { | |
4ba22b16 | 271 | sparc32_ipi_ops = &sun4m_ipi_ops; |
1da177e4 | 272 | } |