Commit | Line | Data |
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64d329ee | 1 | /* linux/arch/sparc/kernel/time.c |
1da177e4 | 2 | * |
64d329ee | 3 | * Copyright (C) 1995 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) |
5 | * | |
6 | * Chris Davis (cdavis@cois.on.ca) 03/27/1998 | |
7 | * Added support for the intersil on the sun4/4200 | |
8 | * | |
9 | * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998 | |
10 | * Support for MicroSPARC-IIep, PCI CPU. | |
11 | * | |
12 | * This file handles the Sparc specific time handling details. | |
13 | * | |
14 | * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 | |
15 | * "A Kernel Model for Precision Timekeeping" by Dave Mills | |
16 | */ | |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/param.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/time.h> | |
c4cbe6f9 | 26 | #include <linux/rtc/m48t59.h> |
1da177e4 | 27 | #include <linux/timex.h> |
62f08283 TK |
28 | #include <linux/clocksource.h> |
29 | #include <linux/clockchips.h> | |
1da177e4 LT |
30 | #include <linux/init.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/profile.h> | |
454eeb2d | 34 | #include <linux/of.h> |
764f2579 | 35 | #include <linux/of_device.h> |
c4cbe6f9 | 36 | #include <linux/platform_device.h> |
1da177e4 | 37 | |
fcea8b27 | 38 | #include <asm/mc146818rtc.h> |
1da177e4 | 39 | #include <asm/oplib.h> |
0299b137 | 40 | #include <asm/timex.h> |
1da177e4 | 41 | #include <asm/timer.h> |
1da177e4 LT |
42 | #include <asm/irq.h> |
43 | #include <asm/io.h> | |
44 | #include <asm/idprom.h> | |
1da177e4 LT |
45 | #include <asm/page.h> |
46 | #include <asm/pcic.h> | |
0d84438d | 47 | #include <asm/irq_regs.h> |
62f08283 | 48 | #include <asm/setup.h> |
1da177e4 | 49 | |
fcea8b27 | 50 | #include "kernel.h" |
32231a66 AV |
51 | #include "irq.h" |
52 | ||
62f08283 TK |
53 | static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock); |
54 | static __volatile__ u64 timer_cs_internal_counter = 0; | |
55 | static char timer_cs_enabled = 0; | |
56 | ||
57 | static struct clock_event_device timer_ce; | |
58 | static char timer_ce_enabled = 0; | |
59 | ||
60 | #ifdef CONFIG_SMP | |
61 | DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent); | |
62 | #endif | |
63 | ||
1da177e4 | 64 | DEFINE_SPINLOCK(rtc_lock); |
6943f3da SR |
65 | EXPORT_SYMBOL(rtc_lock); |
66 | ||
1da177e4 LT |
67 | unsigned long profile_pc(struct pt_regs *regs) |
68 | { | |
69 | extern char __copy_user_begin[], __copy_user_end[]; | |
1da177e4 | 70 | extern char __bzero_begin[], __bzero_end[]; |
1da177e4 LT |
71 | |
72 | unsigned long pc = regs->pc; | |
73 | ||
74 | if (in_lock_functions(pc) || | |
75 | (pc >= (unsigned long) __copy_user_begin && | |
76 | pc < (unsigned long) __copy_user_end) || | |
1da177e4 | 77 | (pc >= (unsigned long) __bzero_begin && |
8a8b836b | 78 | pc < (unsigned long) __bzero_end)) |
1da177e4 LT |
79 | pc = regs->u_regs[UREG_RETPC]; |
80 | return pc; | |
81 | } | |
82 | ||
9550e59c MH |
83 | EXPORT_SYMBOL(profile_pc); |
84 | ||
fcea8b27 | 85 | volatile u32 __iomem *master_l10_counter; |
1da177e4 | 86 | |
62f08283 TK |
87 | irqreturn_t notrace timer_interrupt(int dummy, void *dev_id) |
88 | { | |
89 | if (timer_cs_enabled) { | |
90 | write_seqlock(&timer_cs_lock); | |
91 | timer_cs_internal_counter++; | |
08c9388f | 92 | sparc_config.clear_clock_irq(); |
62f08283 TK |
93 | write_sequnlock(&timer_cs_lock); |
94 | } else { | |
08c9388f | 95 | sparc_config.clear_clock_irq(); |
62f08283 | 96 | } |
1da177e4 | 97 | |
62f08283 TK |
98 | if (timer_ce_enabled) |
99 | timer_ce.event_handler(&timer_ce); | |
1da177e4 | 100 | |
62f08283 TK |
101 | return IRQ_HANDLED; |
102 | } | |
103 | ||
ff4aea45 | 104 | static int timer_ce_shutdown(struct clock_event_device *evt) |
1da177e4 | 105 | { |
ff4aea45 VK |
106 | timer_ce_enabled = 0; |
107 | smp_mb(); | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static int timer_ce_set_periodic(struct clock_event_device *evt) | |
112 | { | |
113 | timer_ce_enabled = 1; | |
62f08283 | 114 | smp_mb(); |
ff4aea45 | 115 | return 0; |
62f08283 TK |
116 | } |
117 | ||
118 | static __init void setup_timer_ce(void) | |
119 | { | |
120 | struct clock_event_device *ce = &timer_ce; | |
121 | ||
122 | BUG_ON(smp_processor_id() != boot_cpu_id); | |
123 | ||
124 | ce->name = "timer_ce"; | |
125 | ce->rating = 100; | |
126 | ce->features = CLOCK_EVT_FEAT_PERIODIC; | |
ff4aea45 VK |
127 | ce->set_state_shutdown = timer_ce_shutdown; |
128 | ce->set_state_periodic = timer_ce_set_periodic; | |
129 | ce->tick_resume = timer_ce_set_periodic; | |
62f08283 TK |
130 | ce->cpumask = cpu_possible_mask; |
131 | ce->shift = 32; | |
132 | ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC, | |
133 | ce->shift); | |
134 | clockevents_register_device(ce); | |
135 | } | |
1da177e4 | 136 | |
62f08283 TK |
137 | static unsigned int sbus_cycles_offset(void) |
138 | { | |
fcea8b27 | 139 | u32 val, offset; |
1da177e4 | 140 | |
fcea8b27 | 141 | val = sbus_readl(master_l10_counter); |
62f08283 | 142 | offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK; |
1da177e4 | 143 | |
62f08283 TK |
144 | /* Limit hit? */ |
145 | if (val & TIMER_LIMIT_BIT) | |
146 | offset += sparc_config.cs_period; | |
147 | ||
148 | return offset; | |
1da177e4 LT |
149 | } |
150 | ||
62f08283 TK |
151 | static cycle_t timer_cs_read(struct clocksource *cs) |
152 | { | |
153 | unsigned int seq, offset; | |
154 | u64 cycles; | |
155 | ||
156 | do { | |
157 | seq = read_seqbegin(&timer_cs_lock); | |
158 | ||
159 | cycles = timer_cs_internal_counter; | |
160 | offset = sparc_config.get_cycles_offset(); | |
161 | } while (read_seqretry(&timer_cs_lock, seq)); | |
162 | ||
163 | /* Count absolute cycles */ | |
164 | cycles *= sparc_config.cs_period; | |
165 | cycles += offset; | |
166 | ||
167 | return cycles; | |
168 | } | |
169 | ||
170 | static struct clocksource timer_cs = { | |
171 | .name = "timer_cs", | |
172 | .rating = 100, | |
173 | .read = timer_cs_read, | |
174 | .mask = CLOCKSOURCE_MASK(64), | |
62f08283 TK |
175 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
176 | }; | |
177 | ||
178 | static __init int setup_timer_cs(void) | |
179 | { | |
180 | timer_cs_enabled = 1; | |
3142f760 | 181 | return clocksource_register_hz(&timer_cs, sparc_config.clock_rate); |
62f08283 TK |
182 | } |
183 | ||
184 | #ifdef CONFIG_SMP | |
ff4aea45 | 185 | static int percpu_ce_shutdown(struct clock_event_device *evt) |
62f08283 | 186 | { |
e4afa120 | 187 | int cpu = cpumask_first(evt->cpumask); |
62f08283 | 188 | |
ff4aea45 VK |
189 | sparc_config.load_profile_irq(cpu, 0); |
190 | return 0; | |
191 | } | |
192 | ||
193 | static int percpu_ce_set_periodic(struct clock_event_device *evt) | |
194 | { | |
195 | int cpu = cpumask_first(evt->cpumask); | |
196 | ||
197 | sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ); | |
198 | return 0; | |
62f08283 TK |
199 | } |
200 | ||
201 | static int percpu_ce_set_next_event(unsigned long delta, | |
202 | struct clock_event_device *evt) | |
203 | { | |
e4afa120 | 204 | int cpu = cpumask_first(evt->cpumask); |
62f08283 TK |
205 | unsigned int next = (unsigned int)delta; |
206 | ||
08c9388f | 207 | sparc_config.load_profile_irq(cpu, next); |
62f08283 TK |
208 | return 0; |
209 | } | |
210 | ||
211 | void register_percpu_ce(int cpu) | |
212 | { | |
213 | struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu); | |
214 | unsigned int features = CLOCK_EVT_FEAT_PERIODIC; | |
215 | ||
216 | if (sparc_config.features & FEAT_L14_ONESHOT) | |
217 | features |= CLOCK_EVT_FEAT_ONESHOT; | |
218 | ||
219 | ce->name = "percpu_ce"; | |
220 | ce->rating = 200; | |
221 | ce->features = features; | |
ff4aea45 VK |
222 | ce->set_state_shutdown = percpu_ce_shutdown; |
223 | ce->set_state_periodic = percpu_ce_set_periodic; | |
224 | ce->set_state_oneshot = percpu_ce_shutdown; | |
62f08283 TK |
225 | ce->set_next_event = percpu_ce_set_next_event; |
226 | ce->cpumask = cpumask_of(cpu); | |
227 | ce->shift = 32; | |
228 | ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC, | |
229 | ce->shift); | |
230 | ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce); | |
231 | ce->min_delta_ns = clockevent_delta2ns(100, ce); | |
232 | ||
233 | clockevents_register_device(ce); | |
234 | } | |
235 | #endif | |
236 | ||
c4cbe6f9 | 237 | static unsigned char mostek_read_byte(struct device *dev, u32 ofs) |
1da177e4 | 238 | { |
c4cbe6f9 DM |
239 | struct platform_device *pdev = to_platform_device(dev); |
240 | struct m48t59_plat_data *pdata = pdev->dev.platform_data; | |
12a9ee3c KH |
241 | |
242 | return readb(pdata->ioaddr + ofs); | |
1da177e4 LT |
243 | } |
244 | ||
c4cbe6f9 | 245 | static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) |
1da177e4 | 246 | { |
c4cbe6f9 DM |
247 | struct platform_device *pdev = to_platform_device(dev); |
248 | struct m48t59_plat_data *pdata = pdev->dev.platform_data; | |
12a9ee3c KH |
249 | |
250 | writeb(val, pdata->ioaddr + ofs); | |
1da177e4 LT |
251 | } |
252 | ||
c4cbe6f9 DM |
253 | static struct m48t59_plat_data m48t59_data = { |
254 | .read_byte = mostek_read_byte, | |
255 | .write_byte = mostek_write_byte, | |
256 | }; | |
257 | ||
258 | /* resource is set at runtime */ | |
259 | static struct platform_device m48t59_rtc = { | |
260 | .name = "rtc-m48t59", | |
261 | .id = 0, | |
262 | .num_resources = 1, | |
263 | .dev = { | |
264 | .platform_data = &m48t59_data, | |
265 | }, | |
266 | }; | |
96ba989d | 267 | |
7c9503b8 | 268 | static int clock_probe(struct platform_device *op) |
1da177e4 | 269 | { |
61c7a080 | 270 | struct device_node *dp = op->dev.of_node; |
8271f042 | 271 | const char *model = of_get_property(dp, "model", NULL); |
1da177e4 | 272 | |
ee5caf0e DM |
273 | if (!model) |
274 | return -ENODEV; | |
1da177e4 | 275 | |
1c833bc3 KO |
276 | /* Only the primary RTC has an address property */ |
277 | if (!of_find_property(dp, "address", NULL)) | |
278 | return -ENODEV; | |
279 | ||
c4cbe6f9 | 280 | m48t59_rtc.resource = &op->resource[0]; |
ee5caf0e | 281 | if (!strcmp(model, "mk48t02")) { |
1da177e4 | 282 | /* Map the clock register io area read-only */ |
c4cbe6f9 DM |
283 | m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0, |
284 | 2048, "rtc-m48t59"); | |
285 | m48t59_data.type = M48T59RTC_TYPE_M48T02; | |
ee5caf0e | 286 | } else if (!strcmp(model, "mk48t08")) { |
c4cbe6f9 DM |
287 | m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0, |
288 | 8192, "rtc-m48t59"); | |
289 | m48t59_data.type = M48T59RTC_TYPE_M48T08; | |
ee5caf0e DM |
290 | } else |
291 | return -ENODEV; | |
1da177e4 | 292 | |
c4cbe6f9 DM |
293 | if (platform_device_register(&m48t59_rtc) < 0) |
294 | printk(KERN_ERR "Registering RTC device failed\n"); | |
96ba989d | 295 | |
ee5caf0e DM |
296 | return 0; |
297 | } | |
298 | ||
505d9147 | 299 | static struct of_device_id clock_match[] = { |
ee5caf0e DM |
300 | { |
301 | .name = "eeprom", | |
302 | }, | |
303 | {}, | |
304 | }; | |
305 | ||
4ebb24f7 | 306 | static struct platform_driver clock_driver = { |
ee5caf0e | 307 | .probe = clock_probe, |
4018294b GL |
308 | .driver = { |
309 | .name = "rtc", | |
4018294b | 310 | .of_match_table = clock_match, |
a2cd1558 | 311 | }, |
ee5caf0e DM |
312 | }; |
313 | ||
314 | ||
315 | /* Probe for the mostek real time clock chip. */ | |
96ba989d | 316 | static int __init clock_init(void) |
ee5caf0e | 317 | { |
4ebb24f7 | 318 | return platform_driver_register(&clock_driver); |
1da177e4 | 319 | } |
96ba989d BB |
320 | /* Must be after subsys_initcall() so that busses are probed. Must |
321 | * be before device_initcall() because things like the RTC driver | |
322 | * need to see the clock registers. | |
323 | */ | |
324 | fs_initcall(clock_init); | |
96ba989d | 325 | |
62f08283 | 326 | static void __init sparc32_late_time_init(void) |
1da177e4 | 327 | { |
62f08283 TK |
328 | if (sparc_config.features & FEAT_L10_CLOCKEVENT) |
329 | setup_timer_ce(); | |
330 | if (sparc_config.features & FEAT_L10_CLOCKSOURCE) | |
331 | setup_timer_cs(); | |
332 | #ifdef CONFIG_SMP | |
333 | register_percpu_ce(smp_processor_id()); | |
334 | #endif | |
1da177e4 LT |
335 | } |
336 | ||
62f08283 | 337 | static void __init sbus_time_init(void) |
1da177e4 | 338 | { |
62f08283 TK |
339 | sparc_config.get_cycles_offset = sbus_cycles_offset; |
340 | sparc_config.init_timers(); | |
1da177e4 LT |
341 | } |
342 | ||
62f08283 | 343 | void __init time_init(void) |
1da177e4 | 344 | { |
62f08283 TK |
345 | sparc_config.features = 0; |
346 | late_time_init = sparc32_late_time_init; | |
1da177e4 | 347 | |
06010fb5 | 348 | if (pcic_present()) |
0299b137 | 349 | pci_time_init(); |
06010fb5 SR |
350 | else |
351 | sbus_time_init(); | |
1da177e4 LT |
352 | } |
353 |