Commit | Line | Data |
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88278ca2 | 1 | /* |
1da177e4 LT |
2 | * trampoline.S: SMP cpu boot-up trampoline code. |
3 | * | |
4 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
8 | #include <linux/init.h> | |
9 | #include <asm/head.h> | |
10 | #include <asm/psr.h> | |
11 | #include <asm/page.h> | |
12 | #include <asm/asi.h> | |
13 | #include <asm/ptrace.h> | |
14 | #include <asm/vaddrs.h> | |
15 | #include <asm/contregs.h> | |
16 | #include <asm/thread_info.h> | |
17 | ||
18 | .globl sun4m_cpu_startup, __smp4m_processor_id | |
19 | .globl sun4d_cpu_startup, __smp4d_processor_id | |
20 | ||
409832f5 | 21 | __CPUINIT |
1da177e4 LT |
22 | .align 4 |
23 | ||
24 | /* When we start up a cpu for the first time it enters this routine. | |
25 | * This initializes the chip from whatever state the prom left it | |
26 | * in and sets PIL in %psr to 15, no irqs. | |
27 | */ | |
28 | ||
29 | sun4m_cpu_startup: | |
30 | cpu1_startup: | |
31 | sethi %hi(trapbase_cpu1), %g3 | |
32 | b 1f | |
33 | or %g3, %lo(trapbase_cpu1), %g3 | |
34 | ||
35 | cpu2_startup: | |
36 | sethi %hi(trapbase_cpu2), %g3 | |
37 | b 1f | |
38 | or %g3, %lo(trapbase_cpu2), %g3 | |
39 | ||
40 | cpu3_startup: | |
41 | sethi %hi(trapbase_cpu3), %g3 | |
42 | b 1f | |
43 | or %g3, %lo(trapbase_cpu3), %g3 | |
44 | ||
45 | 1: | |
46 | /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ | |
47 | set (PSR_PIL | PSR_S | PSR_PS), %g1 | |
48 | wr %g1, 0x0, %psr ! traps off though | |
49 | WRITE_PAUSE | |
50 | ||
51 | /* Our %wim is one behind CWP */ | |
52 | mov 2, %g1 | |
53 | wr %g1, 0x0, %wim | |
54 | WRITE_PAUSE | |
55 | ||
56 | /* This identifies "this cpu". */ | |
57 | wr %g3, 0x0, %tbr | |
58 | WRITE_PAUSE | |
59 | ||
60 | /* Give ourselves a stack and curptr. */ | |
61 | set current_set, %g5 | |
62 | srl %g3, 10, %g4 | |
63 | and %g4, 0xc, %g4 | |
64 | ld [%g5 + %g4], %g6 | |
65 | ||
66 | sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp | |
67 | or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp | |
68 | add %g6, %sp, %sp | |
69 | ||
70 | /* Turn on traps (PSR_ET). */ | |
71 | rd %psr, %g1 | |
72 | wr %g1, PSR_ET, %psr ! traps on | |
73 | WRITE_PAUSE | |
74 | ||
75 | /* Init our caches, etc. */ | |
76 | set poke_srmmu, %g5 | |
77 | ld [%g5], %g5 | |
78 | call %g5 | |
79 | nop | |
80 | ||
81 | /* Start this processor. */ | |
82 | call smp4m_callin | |
83 | nop | |
84 | ||
85 | b,a smp_do_cpu_idle | |
86 | ||
87 | .text | |
88 | .align 4 | |
89 | ||
90 | smp_do_cpu_idle: | |
91 | call cpu_idle | |
92 | mov 0, %o0 | |
93 | ||
94 | call cpu_panic | |
95 | nop | |
96 | ||
97 | __smp4m_processor_id: | |
98 | rd %tbr, %g2 | |
99 | srl %g2, 12, %g2 | |
100 | and %g2, 3, %g2 | |
101 | retl | |
102 | mov %g1, %o7 | |
103 | ||
104 | __smp4d_processor_id: | |
105 | lda [%g0] ASI_M_VIKING_TMP1, %g2 | |
106 | retl | |
107 | mov %g1, %o7 | |
108 | ||
109 | /* CPUID in bootbus can be found at PA 0xff0140000 */ | |
110 | #define SUN4D_BOOTBUS_CPUID 0xf0140000 | |
111 | ||
409832f5 | 112 | __CPUINIT |
1da177e4 LT |
113 | .align 4 |
114 | ||
115 | sun4d_cpu_startup: | |
116 | /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ | |
117 | set (PSR_PIL | PSR_S | PSR_PS), %g1 | |
118 | wr %g1, 0x0, %psr ! traps off though | |
119 | WRITE_PAUSE | |
120 | ||
121 | /* Our %wim is one behind CWP */ | |
122 | mov 2, %g1 | |
123 | wr %g1, 0x0, %wim | |
124 | WRITE_PAUSE | |
125 | ||
126 | /* Set tbr - we use just one trap table. */ | |
127 | set trapbase, %g1 | |
128 | wr %g1, 0x0, %tbr | |
129 | WRITE_PAUSE | |
130 | ||
131 | /* Get our CPU id out of bootbus */ | |
132 | set SUN4D_BOOTBUS_CPUID, %g3 | |
133 | lduba [%g3] ASI_M_CTL, %g3 | |
134 | and %g3, 0xf8, %g3 | |
135 | srl %g3, 3, %g1 | |
136 | sta %g1, [%g0] ASI_M_VIKING_TMP1 | |
137 | ||
138 | /* Give ourselves a stack and curptr. */ | |
139 | set current_set, %g5 | |
140 | srl %g3, 1, %g4 | |
141 | ld [%g5 + %g4], %g6 | |
142 | ||
143 | sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp | |
144 | or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp | |
145 | add %g6, %sp, %sp | |
146 | ||
147 | /* Turn on traps (PSR_ET). */ | |
148 | rd %psr, %g1 | |
149 | wr %g1, PSR_ET, %psr ! traps on | |
150 | WRITE_PAUSE | |
151 | ||
152 | /* Init our caches, etc. */ | |
153 | set poke_srmmu, %g5 | |
154 | ld [%g5], %g5 | |
155 | call %g5 | |
156 | nop | |
157 | ||
158 | /* Start this processor. */ | |
159 | call smp4d_callin | |
160 | nop | |
161 | ||
162 | b,a smp_do_cpu_idle |