[deliverable/linux.git] / arch / sparc / kernel / trampoline_32.S

/*
 * trampoline.S: SMP cpu boot-up trampoline code.
 *
 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <asm/head.h>
#include <asm/psr.h>
#include <asm/page.h>
#include <asm/asi.h>
#include <asm/ptrace.h>
#include <asm/vaddrs.h>
#include <asm/contregs.h>
#include <asm/thread_info.h>

	.globl sun4m_cpu_startup
	.globl sun4d_cpu_startup

	.align 4

/* When we start up a cpu for the first time it enters this routine.
 * This initializes the chip from whatever state the prom left it
 * in and sets PIL in %psr to 15, no irqs.
 */

sun4m_cpu_startup:
cpu1_startup:
	sethi	%hi(trapbase_cpu1), %g3
	b	1f
	 or	%g3, %lo(trapbase_cpu1), %g3

cpu2_startup:
	sethi	%hi(trapbase_cpu2), %g3
	b	1f
	 or	%g3, %lo(trapbase_cpu2), %g3

cpu3_startup:
	sethi	%hi(trapbase_cpu3), %g3
	b	1f
	 or	%g3, %lo(trapbase_cpu3), %g3

1:
	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
	set	(PSR_PIL | PSR_S | PSR_PS), %g1
	wr	%g1, 0x0, %psr		! traps off though
	WRITE_PAUSE

	/* Our %wim is one behind CWP */
	mov	2, %g1
	wr	%g1, 0x0, %wim
	WRITE_PAUSE

	/* This identifies "this cpu". */
	wr	%g3, 0x0, %tbr
	WRITE_PAUSE

	/* Give ourselves a stack and curptr. */
	set	current_set, %g5
	srl	%g3, 10, %g4
	and	%g4, 0xc, %g4
	ld	[%g5 + %g4], %g6

	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
	add	%g6, %sp, %sp

	/* Turn on traps (PSR_ET). */
	rd	%psr, %g1
	wr	%g1, PSR_ET, %psr	! traps on
	WRITE_PAUSE

	/* Init our caches, etc. */
	set	poke_srmmu, %g5
	ld	[%g5], %g5
	call	%g5
	 nop

	/* Start this processor. */
	call	smp_callin
	 nop

	b,a	smp_panic

	.text
	.align	4

smp_panic:
	call	cpu_panic
	 nop

/* CPUID in bootbus can be found at PA 0xff0140000 */
#define SUN4D_BOOTBUS_CPUID	0xf0140000

	.align	4

sun4d_cpu_startup:
	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
	set	(PSR_PIL | PSR_S | PSR_PS), %g1
	wr	%g1, 0x0, %psr		! traps off though
	WRITE_PAUSE

	/* Our %wim is one behind CWP */
	mov	2, %g1
	wr	%g1, 0x0, %wim
	WRITE_PAUSE

	/* Set tbr - we use just one trap table. */
	set	trapbase, %g1
	wr	%g1, 0x0, %tbr
	WRITE_PAUSE

	/* Get our CPU id out of bootbus */
	set	SUN4D_BOOTBUS_CPUID, %g3
	lduba	[%g3] ASI_M_CTL, %g3
	and	%g3, 0xf8, %g3
	srl	%g3, 3, %g1
	sta	%g1, [%g0] ASI_M_VIKING_TMP1

	/* Give ourselves a stack and curptr. */
	set	current_set, %g5
	srl	%g3, 1, %g4
	ld	[%g5 + %g4], %g6

	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
	add	%g6, %sp, %sp

	/* Turn on traps (PSR_ET). */
	rd	%psr, %g1
	wr	%g1, PSR_ET, %psr	! traps on
	WRITE_PAUSE

	/* Init our caches, etc. */
	set	poke_srmmu, %g5
	ld	[%g5], %g5
	call	%g5
	 nop

	/* Start this processor. */
	call	smp_callin
	 nop

	b,a	smp_panic

	.align	4
        .global leon_smp_cpu_startup, smp_penguin_ctable

leon_smp_cpu_startup:

        set smp_penguin_ctable,%g1
        ld [%g1+4],%g1
        srl %g1,4,%g1
        set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
	sta %g1, [%g5] ASI_LEON_MMUREGS

	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
	set	(PSR_PIL | PSR_S | PSR_PS), %g1
	wr	%g1, 0x0, %psr		! traps off though
	WRITE_PAUSE

	/* Our %wim is one behind CWP */
	mov	2, %g1
	wr	%g1, 0x0, %wim
	WRITE_PAUSE

	/* Set tbr - we use just one trap table. */
	set	trapbase, %g1
	wr	%g1, 0x0, %tbr
	WRITE_PAUSE

	/* Get our CPU id */
        rd     %asr17,%g3

	/* Give ourselves a stack and curptr. */
	set	current_set, %g5
	srl	%g3, 28, %g4
	sll	%g4, 2, %g4
	ld	[%g5 + %g4], %g6

	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
	add	%g6, %sp, %sp

	/* Turn on traps (PSR_ET). */
	rd	%psr, %g1
	wr	%g1, PSR_ET, %psr	! traps on
	WRITE_PAUSE

	/* Init our caches, etc. */
	set	poke_srmmu, %g5
	ld	[%g5], %g5
	call	%g5
	 nop

	/* Start this processor. */
	call	smp_callin
	 nop

	b,a	smp_panic
Commit	Line	Data
88278ca2	1	/*
1da177e4 LT	2	* trampoline.S: SMP cpu boot-up trampoline code.
	3	*
	4	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	6	*/
	7
1da177e4 LT	8	#include <asm/head.h>
	9	#include <asm/psr.h>
	10	#include <asm/page.h>
	11	#include <asm/asi.h>
	12	#include <asm/ptrace.h>
	13	#include <asm/vaddrs.h>
	14	#include <asm/contregs.h>
	15	#include <asm/thread_info.h>
	16
c68e5d39 DM	17	.globl sun4m_cpu_startup
c68e5d39 DM	18	.globl sun4d_cpu_startup
1da177e4	19
1da177e4 LT	20	.align 4
	21
	22	/* When we start up a cpu for the first time it enters this routine.
	23	* This initializes the chip from whatever state the prom left it
	24	* in and sets PIL in %psr to 15, no irqs.
	25	*/
	26
	27	sun4m_cpu_startup:
	28	cpu1_startup:
	29	sethi %hi(trapbase_cpu1), %g3
	30	b 1f
	31	or %g3, %lo(trapbase_cpu1), %g3
	32
	33	cpu2_startup:
	34	sethi %hi(trapbase_cpu2), %g3
	35	b 1f
	36	or %g3, %lo(trapbase_cpu2), %g3
	37
	38	cpu3_startup:
	39	sethi %hi(trapbase_cpu3), %g3
	40	b 1f
	41	or %g3, %lo(trapbase_cpu3), %g3
	42
	43	1:
	44	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
	45	set (PSR_PIL \| PSR_S \| PSR_PS), %g1
	46	wr %g1, 0x0, %psr ! traps off though
	47	WRITE_PAUSE
	48
	49	/* Our %wim is one behind CWP */
	50	mov 2, %g1
	51	wr %g1, 0x0, %wim
	52	WRITE_PAUSE
	53
	54	/* This identifies "this cpu". */
	55	wr %g3, 0x0, %tbr
	56	WRITE_PAUSE
	57
	58	/* Give ourselves a stack and curptr. */
	59	set current_set, %g5
	60	srl %g3, 10, %g4
	61	and %g4, 0xc, %g4
	62	ld [%g5 + %g4], %g6
	63
	64	sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
	65	or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
	66	add %g6, %sp, %sp
	67
	68	/* Turn on traps (PSR_ET). */
	69	rd %psr, %g1
	70	wr %g1, PSR_ET, %psr ! traps on
	71	WRITE_PAUSE
	72
	73	/* Init our caches, etc. */
	74	set poke_srmmu, %g5
	75	ld [%g5], %g5
	76	call %g5
	77	nop
	78
	79	/* Start this processor. */
f9fd3488	80	call smp_callin
1da177e4 LT	81	nop
1da177e4 LT	82
f9fd3488	83	b,a smp_panic
1da177e4 LT	84
	85	.text
	86	.align 4
	87
f9fd3488	88	smp_panic:
1da177e4 LT	89	call cpu_panic
	90	nop
	91
1da177e4 LT	92	/* CPUID in bootbus can be found at PA 0xff0140000 */
	93	#define SUN4D_BOOTBUS_CPUID 0xf0140000
	94
1da177e4 LT	95	.align 4
	96
	97	sun4d_cpu_startup:
	98	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
	99	set (PSR_PIL \| PSR_S \| PSR_PS), %g1
	100	wr %g1, 0x0, %psr ! traps off though
	101	WRITE_PAUSE
	102
	103	/* Our %wim is one behind CWP */
	104	mov 2, %g1
	105	wr %g1, 0x0, %wim
	106	WRITE_PAUSE
	107
	108	/* Set tbr - we use just one trap table. */
	109	set trapbase, %g1
	110	wr %g1, 0x0, %tbr
	111	WRITE_PAUSE
	112
	113	/* Get our CPU id out of bootbus */
	114	set SUN4D_BOOTBUS_CPUID, %g3
	115	lduba [%g3] ASI_M_CTL, %g3
	116	and %g3, 0xf8, %g3
	117	srl %g3, 3, %g1
	118	sta %g1, [%g0] ASI_M_VIKING_TMP1
	119
	120	/* Give ourselves a stack and curptr. */
	121	set current_set, %g5
	122	srl %g3, 1, %g4
	123	ld [%g5 + %g4], %g6
	124
	125	sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
	126	or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
	127	add %g6, %sp, %sp
	128
	129	/* Turn on traps (PSR_ET). */
	130	rd %psr, %g1
	131	wr %g1, PSR_ET, %psr ! traps on
	132	WRITE_PAUSE
	133
	134	/* Init our caches, etc. */
	135	set poke_srmmu, %g5
	136	ld [%g5], %g5
	137	call %g5
	138	nop
	139
	140	/* Start this processor. */
f9fd3488	141	call smp_callin
1da177e4 LT	142	nop
1da177e4 LT	143
f9fd3488	144	b,a smp_panic
8401707f	145
8401707f KE	146	.align 4
	147	.global leon_smp_cpu_startup, smp_penguin_ctable
	148
	149	leon_smp_cpu_startup:
	150
	151	set smp_penguin_ctable,%g1
	152	ld [%g1+4],%g1
	153	srl %g1,4,%g1
	154	set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
31079488	155	sta %g1, [%g5] ASI_LEON_MMUREGS
8401707f KE	156
	157	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
	158	set (PSR_PIL \| PSR_S \| PSR_PS), %g1
	159	wr %g1, 0x0, %psr ! traps off though
	160	WRITE_PAUSE
	161
	162	/* Our %wim is one behind CWP */
	163	mov 2, %g1
	164	wr %g1, 0x0, %wim
	165	WRITE_PAUSE
	166
	167	/* Set tbr - we use just one trap table. */
	168	set trapbase, %g1
	169	wr %g1, 0x0, %tbr
	170	WRITE_PAUSE
	171
	172	/* Get our CPU id */
	173	rd %asr17,%g3
	174
	175	/* Give ourselves a stack and curptr. */
	176	set current_set, %g5
	177	srl %g3, 28, %g4
	178	sll %g4, 2, %g4
	179	ld [%g5 + %g4], %g6
	180
	181	sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
	182	or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
	183	add %g6, %sp, %sp
	184
	185	/* Turn on traps (PSR_ET). */
	186	rd %psr, %g1
	187	wr %g1, PSR_ET, %psr ! traps on
	188	WRITE_PAUSE
	189
	190	/* Init our caches, etc. */
	191	set poke_srmmu, %g5
	192	ld [%g5], %g5
	193	call %g5
	194	nop
	195
	196	/* Start this processor. */
f9fd3488	197	call smp_callin
8401707f KE	198	nop
8401707f KE	199
f9fd3488	200	b,a smp_panic