[deliverable/linux.git] / arch / sparc / kernel / unaligned_64.c

/*
 * unaligned.c: Unaligned load/store trap handling with special
 *              cases for the kernel to do them more quickly.
 *
 * Copyright (C) 1996,2008 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */


#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <asm/asi.h>
#include <asm/ptrace.h>
#include <asm/pstate.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <linux/smp.h>
#include <linux/bitops.h>
#include <linux/perf_event.h>
#include <linux/ratelimit.h>
#include <asm/fpumacro.h>
#include <asm/cacheflush.h>

enum direction {
	load,    /* ld, ldd, ldh, ldsh */
	store,   /* st, std, sth, stsh */
	both,    /* Swap, ldstub, cas, ... */
	fpld,
	fpst,
	invalid,
};

static inline enum direction decode_direction(unsigned int insn)
{
	unsigned long tmp = (insn >> 21) & 1;

	if (!tmp)
		return load;
	else {
		switch ((insn>>19)&0xf) {
		case 15: /* swap* */
			return both;
		default:
			return store;
		}
	}
}

/* 16 = double-word, 8 = extra-word, 4 = word, 2 = half-word */
static inline int decode_access_size(struct pt_regs *regs, unsigned int insn)
{
	unsigned int tmp;

	tmp = ((insn >> 19) & 0xf);
	if (tmp == 11 || tmp == 14) /* ldx/stx */
		return 8;
	tmp &= 3;
	if (!tmp)
		return 4;
	else if (tmp == 3)
		return 16;	/* ldd/std - Although it is actually 8 */
	else if (tmp == 2)
		return 2;
	else {
		printk("Impossible unaligned trap. insn=%08x\n", insn);
		die_if_kernel("Byte sized unaligned access?!?!", regs);

		/* GCC should never warn that control reaches the end
		 * of this function without returning a value because
		 * die_if_kernel() is marked with attribute 'noreturn'.
		 * Alas, some versions do...
		 */

		return 0;
	}
}

static inline int decode_asi(unsigned int insn, struct pt_regs *regs)
{
	if (insn & 0x800000) {
		if (insn & 0x2000)
			return (unsigned char)(regs->tstate >> 24);	/* %asi */
		else
			return (unsigned char)(insn >> 5);		/* imm_asi */
	} else
		return ASI_P;
}

/* 0x400000 = signed, 0 = unsigned */
static inline int decode_signedness(unsigned int insn)
{
	return (insn & 0x400000);
}

static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
				       unsigned int rd, int from_kernel)
{
	if (rs2 >= 16 || rs1 >= 16 || rd >= 16) {
		if (from_kernel != 0)
			__asm__ __volatile__("flushw");
		else
			flushw_user();
	}
}

static inline long sign_extend_imm13(long imm)
{
	return imm << 51 >> 51;
}

static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
{
	unsigned long value, fp;
	
	if (reg < 16)
		return (!reg ? 0 : regs->u_regs[reg]);

	fp = regs->u_regs[UREG_FP];

	if (regs->tstate & TSTATE_PRIV) {
		struct reg_window *win;
		win = (struct reg_window *)(fp + STACK_BIAS);
		value = win->locals[reg - 16];
	} else if (!test_thread_64bit_stack(fp)) {
		struct reg_window32 __user *win32;
		win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
		get_user(value, &win32->locals[reg - 16]);
	} else {
		struct reg_window __user *win;
		win = (struct reg_window __user *)(fp + STACK_BIAS);
		get_user(value, &win->locals[reg - 16]);
	}
	return value;
}

static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs)
{
	unsigned long fp;

	if (reg < 16)
		return &regs->u_regs[reg];

	fp = regs->u_regs[UREG_FP];

	if (regs->tstate & TSTATE_PRIV) {
		struct reg_window *win;
		win = (struct reg_window *)(fp + STACK_BIAS);
		return &win->locals[reg - 16];
	} else if (!test_thread_64bit_stack(fp)) {
		struct reg_window32 *win32;
		win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
		return (unsigned long *)&win32->locals[reg - 16];
	} else {
		struct reg_window *win;
		win = (struct reg_window *)(fp + STACK_BIAS);
		return &win->locals[reg - 16];
	}
}

unsigned long compute_effective_address(struct pt_regs *regs,
					unsigned int insn, unsigned int rd)
{
	unsigned int rs1 = (insn >> 14) & 0x1f;
	unsigned int rs2 = insn & 0x1f;
	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;

	if (insn & 0x2000) {
		maybe_flush_windows(rs1, 0, rd, from_kernel);
		return (fetch_reg(rs1, regs) + sign_extend_imm13(insn));
	} else {
		maybe_flush_windows(rs1, rs2, rd, from_kernel);
		return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));
	}
}

/* This is just to make gcc think die_if_kernel does return... */
static void __used unaligned_panic(char *str, struct pt_regs *regs)
{
	die_if_kernel(str, regs);
}

extern int do_int_load(unsigned long *dest_reg, int size,
		       unsigned long *saddr, int is_signed, int asi);
	
extern int __do_int_store(unsigned long *dst_addr, int size,
			  unsigned long src_val, int asi);

static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
			       struct pt_regs *regs, int asi, int orig_asi)
{
	unsigned long zero = 0;
	unsigned long *src_val_p = &zero;
	unsigned long src_val;

	if (size == 16) {
		size = 8;
		zero = (((long)(reg_num ?
		        (unsigned)fetch_reg(reg_num, regs) : 0)) << 32) |
			(unsigned)fetch_reg(reg_num + 1, regs);
	} else if (reg_num) {
		src_val_p = fetch_reg_addr(reg_num, regs);
	}
	src_val = *src_val_p;
	if (unlikely(asi != orig_asi)) {
		switch (size) {
		case 2:
			src_val = swab16(src_val);
			break;
		case 4:
			src_val = swab32(src_val);
			break;
		case 8:
			src_val = swab64(src_val);
			break;
		case 16:
		default:
			BUG();
			break;
		}
	}
	return __do_int_store(dst_addr, size, src_val, asi);
}

static inline void advance(struct pt_regs *regs)
{
	regs->tpc   = regs->tnpc;
	regs->tnpc += 4;
	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
}

static inline int floating_point_load_or_store_p(unsigned int insn)
{
	return (insn >> 24) & 1;
}

static inline int ok_for_kernel(unsigned int insn)
{
	return !floating_point_load_or_store_p(insn);
}

static void kernel_mna_trap_fault(int fixup_tstate_asi)
{
	struct pt_regs *regs = current_thread_info()->kern_una_regs;
	unsigned int insn = current_thread_info()->kern_una_insn;
	const struct exception_table_entry *entry;

	entry = search_exception_tables(regs->tpc);
	if (!entry) {
		unsigned long address;

		address = compute_effective_address(regs, insn,
						    ((insn >> 25) & 0x1f));
        	if (address < PAGE_SIZE) {
                	printk(KERN_ALERT "Unable to handle kernel NULL "
			       "pointer dereference in mna handler");
        	} else
                	printk(KERN_ALERT "Unable to handle kernel paging "
			       "request in mna handler");
	        printk(KERN_ALERT " at virtual address %016lx\n",address);
		printk(KERN_ALERT "current->{active_,}mm->context = %016lx\n",
			(current->mm ? CTX_HWBITS(current->mm->context) :
			CTX_HWBITS(current->active_mm->context)));
		printk(KERN_ALERT "current->{active_,}mm->pgd = %016lx\n",
			(current->mm ? (unsigned long) current->mm->pgd :
			(unsigned long) current->active_mm->pgd));
	        die_if_kernel("Oops", regs);
		/* Not reached */
	}
	regs->tpc = entry->fixup;
	regs->tnpc = regs->tpc + 4;

	if (fixup_tstate_asi) {
		regs->tstate &= ~TSTATE_ASI;
		regs->tstate |= (ASI_AIUS << 24UL);
	}
}

static void log_unaligned(struct pt_regs *regs)
{
	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

	if (__ratelimit(&ratelimit)) {
		printk("Kernel unaligned access at TPC[%lx] %pS\n",
		       regs->tpc, (void *) regs->tpc);
	}
}

asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
{
	enum direction dir = decode_direction(insn);
	int size = decode_access_size(regs, insn);
	int orig_asi, asi;

	current_thread_info()->kern_una_regs = regs;
	current_thread_info()->kern_una_insn = insn;

	orig_asi = asi = decode_asi(insn, regs);

	/* If this is a {get,put}_user() on an unaligned userspace pointer,
	 * just signal a fault and do not log the event.
	 */
	if (asi == ASI_AIUS) {
		kernel_mna_trap_fault(0);
		return;
	}

	log_unaligned(regs);

	if (!ok_for_kernel(insn) || dir == both) {
		printk("Unsupported unaligned load/store trap for kernel "
		       "at <%016lx>.\n", regs->tpc);
		unaligned_panic("Kernel does fpu/atomic "
				"unaligned load/store.", regs);

		kernel_mna_trap_fault(0);
	} else {
		unsigned long addr, *reg_addr;
		int err;

		addr = compute_effective_address(regs, insn,
						 ((insn >> 25) & 0x1f));
		perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
		switch (asi) {
		case ASI_NL:
		case ASI_AIUPL:
		case ASI_AIUSL:
		case ASI_PL:
		case ASI_SL:
		case ASI_PNFL:
		case ASI_SNFL:
			asi &= ~0x08;
			break;
		}
		switch (dir) {
		case load:
			reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
			err = do_int_load(reg_addr, size,
					  (unsigned long *) addr,
					  decode_signedness(insn), asi);
			if (likely(!err) && unlikely(asi != orig_asi)) {
				unsigned long val_in = *reg_addr;
				switch (size) {
				case 2:
					val_in = swab16(val_in);
					break;
				case 4:
					val_in = swab32(val_in);
					break;
				case 8:
					val_in = swab64(val_in);
					break;
				case 16:
				default:
					BUG();
					break;
				}
				*reg_addr = val_in;
			}
			break;

		case store:
			err = do_int_store(((insn>>25)&0x1f), size,
					   (unsigned long *) addr, regs,
					   asi, orig_asi);
			break;

		default:
			panic("Impossible kernel unaligned trap.");
			/* Not reached... */
		}
		if (unlikely(err))
			kernel_mna_trap_fault(1);
		else
			advance(regs);
	}
}

int handle_popc(u32 insn, struct pt_regs *regs)
{
	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	int ret, rd = ((insn >> 25) & 0x1f);
	u64 value;
	                        
	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
	if (insn & 0x2000) {
		maybe_flush_windows(0, 0, rd, from_kernel);
		value = sign_extend_imm13(insn);
	} else {
		maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
		value = fetch_reg(insn & 0x1f, regs);
	}
	ret = hweight64(value);
	if (rd < 16) {
		if (rd)
			regs->u_regs[rd] = ret;
	} else {
		unsigned long fp = regs->u_regs[UREG_FP];

		if (!test_thread_64bit_stack(fp)) {
			struct reg_window32 __user *win32;
			win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
			put_user(ret, &win32->locals[rd - 16]);
		} else {
			struct reg_window __user *win;
			win = (struct reg_window __user *)(fp + STACK_BIAS);
			put_user(ret, &win->locals[rd - 16]);
		}
	}
	advance(regs);
	return 1;
}

extern void do_fpother(struct pt_regs *regs);
extern void do_privact(struct pt_regs *regs);
extern void spitfire_data_access_exception(struct pt_regs *regs,
					   unsigned long sfsr,
					   unsigned long sfar);
extern void sun4v_data_access_exception(struct pt_regs *regs,
					unsigned long addr,
					unsigned long type_ctx);

int handle_ldf_stq(u32 insn, struct pt_regs *regs)
{
	unsigned long addr = compute_effective_address(regs, insn, 0);
	int freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
	struct fpustate *f = FPUSTATE;
	int asi = decode_asi(insn, regs);
	int flag = (freg < 32) ? FPRS_DL : FPRS_DU;

	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);

	save_and_clear_fpu();
	current_thread_info()->xfsr[0] &= ~0x1c000;
	if (freg & 3) {
		current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
		do_fpother(regs);
		return 0;
	}
	if (insn & 0x200000) {
		/* STQ */
		u64 first = 0, second = 0;
		
		if (current_thread_info()->fpsaved[0] & flag) {
			first = *(u64 *)&f->regs[freg];
			second = *(u64 *)&f->regs[freg+2];
		}
		if (asi < 0x80) {
			do_privact(regs);
			return 1;
		}
		switch (asi) {
		case ASI_P:
		case ASI_S: break;
		case ASI_PL:
		case ASI_SL: 
			{
				/* Need to convert endians */
				u64 tmp = __swab64p(&first);
				
				first = __swab64p(&second);
				second = tmp;
				break;
			}
		default:
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
			return 1;
		}
		if (put_user (first >> 32, (u32 __user *)addr) ||
		    __put_user ((u32)first, (u32 __user *)(addr + 4)) ||
		    __put_user (second >> 32, (u32 __user *)(addr + 8)) ||
		    __put_user ((u32)second, (u32 __user *)(addr + 12))) {
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
		    	return 1;
		}
	} else {
		/* LDF, LDDF, LDQF */
		u32 data[4] __attribute__ ((aligned(8)));
		int size, i;
		int err;

		if (asi < 0x80) {
			do_privact(regs);
			return 1;
		} else if (asi > ASI_SNFL) {
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
			return 1;
		}
		switch (insn & 0x180000) {
		case 0x000000: size = 1; break;
		case 0x100000: size = 4; break;
		default: size = 2; break;
		}
		for (i = 0; i < size; i++)
			data[i] = 0;
		
		err = get_user (data[0], (u32 __user *) addr);
		if (!err) {
			for (i = 1; i < size; i++)
				err |= __get_user (data[i], (u32 __user *)(addr + 4*i));
		}
		if (err && !(asi & 0x2 /* NF */)) {
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
			return 1;
		}
		if (asi & 0x8) /* Little */ {
			u64 tmp;

			switch (size) {
			case 1: data[0] = le32_to_cpup(data + 0); break;
			default:*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 0));
				break;
			case 4: tmp = le64_to_cpup((u64 *)(data + 0));
				*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 2));
				*(u64 *)(data + 2) = tmp;
				break;
			}
		}
		if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
			current_thread_info()->fpsaved[0] = FPRS_FEF;
			current_thread_info()->gsr[0] = 0;
		}
		if (!(current_thread_info()->fpsaved[0] & flag)) {
			if (freg < 32)
				memset(f->regs, 0, 32*sizeof(u32));
			else
				memset(f->regs+32, 0, 32*sizeof(u32));
		}
		memcpy(f->regs + freg, data, size * 4);
		current_thread_info()->fpsaved[0] |= flag;
	}
	advance(regs);
	return 1;
}

void handle_ld_nf(u32 insn, struct pt_regs *regs)
{
	int rd = ((insn >> 25) & 0x1f);
	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	unsigned long *reg;
	                        
	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);

	maybe_flush_windows(0, 0, rd, from_kernel);
	reg = fetch_reg_addr(rd, regs);
	if (from_kernel || rd < 16) {
		reg[0] = 0;
		if ((insn & 0x780000) == 0x180000)
			reg[1] = 0;
	} else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
		put_user(0, (int __user *) reg);
		if ((insn & 0x780000) == 0x180000)
			put_user(0, ((int __user *) reg) + 1);
	} else {
		put_user(0, (unsigned long __user *) reg);
		if ((insn & 0x780000) == 0x180000)
			put_user(0, (unsigned long __user *) reg + 1);
	}
	advance(regs);
}

void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
{
	unsigned long pc = regs->tpc;
	unsigned long tstate = regs->tstate;
	u32 insn;
	u64 value;
	u8 freg;
	int flag;
	struct fpustate *f = FPUSTATE;

	if (tstate & TSTATE_PRIV)
		die_if_kernel("lddfmna from kernel", regs);
	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
	if (test_thread_flag(TIF_32BIT))
		pc = (u32)pc;
	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
		int asi = decode_asi(insn, regs);
		u32 first, second;
		int err;

		if ((asi > ASI_SNFL) ||
		    (asi < ASI_P))
			goto daex;
		first = second = 0;
		err = get_user(first, (u32 __user *)sfar);
		if (!err)
			err = get_user(second, (u32 __user *)(sfar + 4));
		if (err) {
			if (!(asi & 0x2))
				goto daex;
			first = second = 0;
		}
		save_and_clear_fpu();
		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
		value = (((u64)first) << 32) | second;
		if (asi & 0x8) /* Little */
			value = __swab64p(&value);
		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
		if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
			current_thread_info()->fpsaved[0] = FPRS_FEF;
			current_thread_info()->gsr[0] = 0;
		}
		if (!(current_thread_info()->fpsaved[0] & flag)) {
			if (freg < 32)
				memset(f->regs, 0, 32*sizeof(u32));
			else
				memset(f->regs+32, 0, 32*sizeof(u32));
		}
		*(u64 *)(f->regs + freg) = value;
		current_thread_info()->fpsaved[0] |= flag;
	} else {
daex:
		if (tlb_type == hypervisor)
			sun4v_data_access_exception(regs, sfar, sfsr);
		else
			spitfire_data_access_exception(regs, sfsr, sfar);
		return;
	}
	advance(regs);
}

void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
{
	unsigned long pc = regs->tpc;
	unsigned long tstate = regs->tstate;
	u32 insn;
	u64 value;
	u8 freg;
	int flag;
	struct fpustate *f = FPUSTATE;

	if (tstate & TSTATE_PRIV)
		die_if_kernel("stdfmna from kernel", regs);
	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
	if (test_thread_flag(TIF_32BIT))
		pc = (u32)pc;
	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
		int asi = decode_asi(insn, regs);
		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
		value = 0;
		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
		if ((asi > ASI_SNFL) ||
		    (asi < ASI_P))
			goto daex;
		save_and_clear_fpu();
		if (current_thread_info()->fpsaved[0] & flag)
			value = *(u64 *)&f->regs[freg];
		switch (asi) {
		case ASI_P:
		case ASI_S: break;
		case ASI_PL:
		case ASI_SL: 
			value = __swab64p(&value); break;
		default: goto daex;
		}
		if (put_user (value >> 32, (u32 __user *) sfar) ||
		    __put_user ((u32)value, (u32 __user *)(sfar + 4)))
			goto daex;
	} else {
daex:
		if (tlb_type == hypervisor)
			sun4v_data_access_exception(regs, sfar, sfsr);
		else
			spitfire_data_access_exception(regs, sfsr, sfar);
		return;
	}
	advance(regs);
}
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* unaligned.c: Unaligned load/store trap handling with special
	3	* cases for the kernel to do them more quickly.
	4	*
4fe3ebec	5	* Copyright (C) 1996,2008 David S. Miller (davem@davemloft.net)
1da177e4 LT	6	* Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	7	*/
	8
	9
cbc9fc5d	10	#include <linux/jiffies.h>
1da177e4 LT	11	#include <linux/kernel.h>
	12	#include <linux/sched.h>
	13	#include <linux/mm.h>
	14	#include <linux/module.h>
	15	#include <asm/asi.h>
	16	#include <asm/ptrace.h>
	17	#include <asm/pstate.h>
	18	#include <asm/processor.h>
1da177e4 LT	19	#include <asm/uaccess.h>
1da177e4 LT	20	#include <linux/smp.h>
1da177e4	21	#include <linux/bitops.h>
121dd5f2	22	#include <linux/perf_event.h>
c7ec2b58	23	#include <linux/ratelimit.h>
1da177e4	24	#include <asm/fpumacro.h>
d550bbd4	25	#include <asm/cacheflush.h>
1da177e4	26
1da177e4 LT	27	enum direction {
	28	load, /* ld, ldd, ldh, ldsh */
	29	store, /* st, std, sth, stsh */
	30	both, /* Swap, ldstub, cas, ... */
	31	fpld,
	32	fpst,
	33	invalid,
	34	};
	35
1da177e4 LT	36	static inline enum direction decode_direction(unsigned int insn)
	37	{
	38	unsigned long tmp = (insn >> 21) & 1;
	39
	40	if (!tmp)
	41	return load;
	42	else {
	43	switch ((insn>>19)&0xf) {
	44	case 15: /* swap* */
	45	return both;
	46	default:
	47	return store;
	48	}
	49	}
	50	}
	51
	52	/* 16 = double-word, 8 = extra-word, 4 = word, 2 = half-word */
baa06775	53	static inline int decode_access_size(struct pt_regs *regs, unsigned int insn)
1da177e4 LT	54	{
	55	unsigned int tmp;
	56
	57	tmp = ((insn >> 19) & 0xf);
	58	if (tmp == 11 \|\| tmp == 14) /* ldx/stx */
	59	return 8;
	60	tmp &= 3;
	61	if (!tmp)
	62	return 4;
	63	else if (tmp == 3)
	64	return 16; /* ldd/std - Although it is actually 8 */
	65	else if (tmp == 2)
	66	return 2;
	67	else {
	68	printk("Impossible unaligned trap. insn=%08x\n", insn);
baa06775	69	die_if_kernel("Byte sized unaligned access?!?!", regs);
1da177e4 LT	70
	71	/* GCC should never warn that control reaches the end
	72	* of this function without returning a value because
	73	* die_if_kernel() is marked with attribute 'noreturn'.
	74	* Alas, some versions do...
	75	*/
	76
	77	return 0;
	78	}
	79	}
	80
	81	static inline int decode_asi(unsigned int insn, struct pt_regs *regs)
	82	{
	83	if (insn & 0x800000) {
	84	if (insn & 0x2000)
	85	return (unsigned char)(regs->tstate >> 24); /* %asi */
	86	else
	87	return (unsigned char)(insn >> 5); /* imm_asi */
	88	} else
	89	return ASI_P;
	90	}
	91
	92	/* 0x400000 = signed, 0 = unsigned */
	93	static inline int decode_signedness(unsigned int insn)
	94	{
	95	return (insn & 0x400000);
	96	}
	97
	98	static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
	99	unsigned int rd, int from_kernel)
	100	{
	101	if (rs2 >= 16 \|\| rs1 >= 16 \|\| rd >= 16) {
	102	if (from_kernel != 0)
	103	__asm__ __volatile__("flushw");
	104	else
	105	flushw_user();
	106	}
	107	}
	108
	109	static inline long sign_extend_imm13(long imm)
	110	{
	111	return imm << 51 >> 51;
	112	}
	113
	114	static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
	115	{
517ffce4	116	unsigned long value, fp;
1da177e4 LT	117
	118	if (reg < 16)
	119	return (!reg ? 0 : regs->u_regs[reg]);
517ffce4 DM	120
	121	fp = regs->u_regs[UREG_FP];
	122
1da177e4 LT	123	if (regs->tstate & TSTATE_PRIV) {
1da177e4 LT	124	struct reg_window *win;
517ffce4	125	win = (struct reg_window *)(fp + STACK_BIAS);
1da177e4	126	value = win->locals[reg - 16];
517ffce4	127	} else if (!test_thread_64bit_stack(fp)) {
1da177e4	128	struct reg_window32 __user *win32;
517ffce4	129	win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
1da177e4 LT	130	get_user(value, &win32->locals[reg - 16]);
	131	} else {
	132	struct reg_window __user *win;
517ffce4	133	win = (struct reg_window __user *)(fp + STACK_BIAS);
1da177e4 LT	134	get_user(value, &win->locals[reg - 16]);
	135	}
	136	return value;
	137	}
	138
	139	static unsigned long fetch_reg_addr(unsigned int reg, struct pt_regs regs)
	140	{
517ffce4 DM	141	unsigned long fp;
517ffce4 DM	142
1da177e4 LT	143	if (reg < 16)
1da177e4 LT	144	return &regs->u_regs[reg];
517ffce4 DM	145
	146	fp = regs->u_regs[UREG_FP];
	147
1da177e4 LT	148	if (regs->tstate & TSTATE_PRIV) {
1da177e4 LT	149	struct reg_window *win;
517ffce4	150	win = (struct reg_window *)(fp + STACK_BIAS);
1da177e4	151	return &win->locals[reg - 16];
517ffce4	152	} else if (!test_thread_64bit_stack(fp)) {
1da177e4	153	struct reg_window32 *win32;
517ffce4	154	win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
1da177e4 LT	155	return (unsigned long *)&win32->locals[reg - 16];
	156	} else {
	157	struct reg_window *win;
517ffce4	158	win = (struct reg_window *)(fp + STACK_BIAS);
1da177e4 LT	159	return &win->locals[reg - 16];
	160	}
	161	}
	162
	163	unsigned long compute_effective_address(struct pt_regs *regs,
	164	unsigned int insn, unsigned int rd)
	165	{
	166	unsigned int rs1 = (insn >> 14) & 0x1f;
	167	unsigned int rs2 = insn & 0x1f;
	168	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	169
	170	if (insn & 0x2000) {
	171	maybe_flush_windows(rs1, 0, rd, from_kernel);
	172	return (fetch_reg(rs1, regs) + sign_extend_imm13(insn));
	173	} else {
	174	maybe_flush_windows(rs1, rs2, rd, from_kernel);
	175	return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));
	176	}
	177	}
	178
	179	/* This is just to make gcc think die_if_kernel does return... */
3ff6eecc	180	static void __used unaligned_panic(char str, struct pt_regs regs)
1da177e4 LT	181	{
	182	die_if_kernel(str, regs);
	183	}
	184
5fd29752 DM	185	extern int do_int_load(unsigned long *dest_reg, int size,
5fd29752 DM	186	unsigned long *saddr, int is_signed, int asi);
1da177e4	187
5fd29752 DM	188	extern int __do_int_store(unsigned long *dst_addr, int size,
5fd29752 DM	189	unsigned long src_val, int asi);
a3f99858	190
5fd29752 DM	191	static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
5fd29752 DM	192	struct pt_regs *regs, int asi, int orig_asi)
a3f99858 DM	193	{
a3f99858 DM	194	unsigned long zero = 0;
ff171d8f DM	195	unsigned long *src_val_p = &zero;
ff171d8f DM	196	unsigned long src_val;
a3f99858 DM	197
	198	if (size == 16) {
	199	size = 8;
	200	zero = (((long)(reg_num ?
	201	(unsigned)fetch_reg(reg_num, regs) : 0)) << 32) \|
	202	(unsigned)fetch_reg(reg_num + 1, regs);
	203	} else if (reg_num) {
ff171d8f DM	204	src_val_p = fetch_reg_addr(reg_num, regs);
	205	}
	206	src_val = *src_val_p;
	207	if (unlikely(asi != orig_asi)) {
	208	switch (size) {
	209	case 2:
	210	src_val = swab16(src_val);
	211	break;
	212	case 4:
	213	src_val = swab32(src_val);
	214	break;
	215	case 8:
	216	src_val = swab64(src_val);
	217	break;
	218	case 16:
	219	default:
	220	BUG();
	221	break;
6cb79b3f	222	}
a3f99858	223	}
5fd29752	224	return __do_int_store(dst_addr, size, src_val, asi);
a3f99858	225	}
1da177e4 LT	226
	227	static inline void advance(struct pt_regs *regs)
	228	{
	229	regs->tpc = regs->tnpc;
	230	regs->tnpc += 4;
	231	if (test_thread_flag(TIF_32BIT)) {
	232	regs->tpc &= 0xffffffff;
	233	regs->tnpc &= 0xffffffff;
	234	}
	235	}
	236
	237	static inline int floating_point_load_or_store_p(unsigned int insn)
	238	{
	239	return (insn >> 24) & 1;
	240	}
	241
	242	static inline int ok_for_kernel(unsigned int insn)
	243	{
	244	return !floating_point_load_or_store_p(insn);
	245	}
	246
c449c38b	247	static void kernel_mna_trap_fault(int fixup_tstate_asi)
1da177e4	248	{
a3f99858 DM	249	struct pt_regs *regs = current_thread_info()->kern_una_regs;
a3f99858 DM	250	unsigned int insn = current_thread_info()->kern_una_insn;
8cf14af0	251	const struct exception_table_entry *entry;
1da177e4	252
8cf14af0 DM	253	entry = search_exception_tables(regs->tpc);
8cf14af0 DM	254	if (!entry) {
a3f99858 DM	255	unsigned long address;
	256
	257	address = compute_effective_address(regs, insn,
	258	((insn >> 25) & 0x1f));
1da177e4	259	if (address < PAGE_SIZE) {
a3f99858 DM	260	printk(KERN_ALERT "Unable to handle kernel NULL "
a3f99858 DM	261	"pointer dereference in mna handler");
1da177e4	262	} else
a3f99858 DM	263	printk(KERN_ALERT "Unable to handle kernel paging "
a3f99858 DM	264	"request in mna handler");
1da177e4	265	printk(KERN_ALERT " at virtual address %016lx\n",address);
a3f99858	266	printk(KERN_ALERT "current->{active_,}mm->context = %016lx\n",
1da177e4 LT	267	(current->mm ? CTX_HWBITS(current->mm->context) :
1da177e4 LT	268	CTX_HWBITS(current->active_mm->context)));
a3f99858	269	printk(KERN_ALERT "current->{active_,}mm->pgd = %016lx\n",
1da177e4 LT	270	(current->mm ? (unsigned long) current->mm->pgd :
	271	(unsigned long) current->active_mm->pgd));
	272	die_if_kernel("Oops", regs);
	273	/* Not reached */
	274	}
8cf14af0	275	regs->tpc = entry->fixup;
1da177e4	276	regs->tnpc = regs->tpc + 4;
1da177e4	277
c449c38b DM	278	if (fixup_tstate_asi) {
	279	regs->tstate &= ~TSTATE_ASI;
	280	regs->tstate \|= (ASI_AIUS << 24UL);
	281	}
1da177e4 LT	282	}
1da177e4 LT	283
c449c38b	284	static void log_unaligned(struct pt_regs *regs)
1da177e4	285	{
c7ec2b58	286	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
a3f99858	287
c7ec2b58	288	if (__ratelimit(&ratelimit)) {
4fe3ebec DM	289	printk("Kernel unaligned access at TPC[%lx] %pS\n",
4fe3ebec DM	290	regs->tpc, (void *) regs->tpc);
27cc64c7	291	}
c449c38b DM	292	}
	293
	294	asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
	295	{
	296	enum direction dir = decode_direction(insn);
baa06775	297	int size = decode_access_size(regs, insn);
c449c38b DM	298	int orig_asi, asi;
	299
	300	current_thread_info()->kern_una_regs = regs;
	301	current_thread_info()->kern_una_insn = insn;
	302
	303	orig_asi = asi = decode_asi(insn, regs);
	304
	305	/* If this is a {get,put}_user() on an unaligned userspace pointer,
	306	* just signal a fault and do not log the event.
	307	*/
	308	if (asi == ASI_AIUS) {
	309	kernel_mna_trap_fault(0);
	310	return;
	311	}
	312
	313	log_unaligned(regs);
27cc64c7	314
1da177e4	315	if (!ok_for_kernel(insn) \|\| dir == both) {
a3f99858 DM	316	printk("Unsupported unaligned load/store trap for kernel "
	317	"at <%016lx>.\n", regs->tpc);
	318	unaligned_panic("Kernel does fpu/atomic "
	319	"unaligned load/store.", regs);
	320
c449c38b	321	kernel_mna_trap_fault(0);
1da177e4	322	} else {
705747ab	323	unsigned long addr, *reg_addr;
c449c38b	324	int err;
1da177e4	325
a3f99858 DM	326	addr = compute_effective_address(regs, insn,
a3f99858 DM	327	((insn >> 25) & 0x1f));
a8b0ca17	328	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
ff171d8f DM	329	switch (asi) {
	330	case ASI_NL:
	331	case ASI_AIUPL:
	332	case ASI_AIUSL:
	333	case ASI_PL:
	334	case ASI_SL:
	335	case ASI_PNFL:
	336	case ASI_SNFL:
	337	asi &= ~0x08;
	338	break;
6cb79b3f	339	}
1da177e4 LT	340	switch (dir) {
1da177e4 LT	341	case load:
705747ab	342	reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
5fd29752 DM	343	err = do_int_load(reg_addr, size,
	344	(unsigned long *) addr,
	345	decode_signedness(insn), asi);
	346	if (likely(!err) && unlikely(asi != orig_asi)) {
705747ab	347	unsigned long val_in = *reg_addr;
ff171d8f DM	348	switch (size) {
	349	case 2:
	350	val_in = swab16(val_in);
	351	break;
	352	case 4:
	353	val_in = swab32(val_in);
	354	break;
	355	case 8:
	356	val_in = swab64(val_in);
	357	break;
	358	case 16:
	359	default:
	360	BUG();
	361	break;
6cb79b3f	362	}
705747ab	363	*reg_addr = val_in;
ff171d8f	364	}
1da177e4 LT	365	break;
	366
	367	case store:
5fd29752 DM	368	err = do_int_store(((insn>>25)&0x1f), size,
	369	(unsigned long *) addr, regs,
	370	asi, orig_asi);
1da177e4	371	break;
a3f99858	372
1da177e4 LT	373	default:
	374	panic("Impossible kernel unaligned trap.");
	375	/* Not reached... */
	376	}
5fd29752	377	if (unlikely(err))
c449c38b	378	kernel_mna_trap_fault(1);
5fd29752 DM	379	else
5fd29752 DM	380	advance(regs);
1da177e4 LT	381	}
	382	}
	383
1da177e4 LT	384	int handle_popc(u32 insn, struct pt_regs *regs)
1da177e4 LT	385	{
1da177e4	386	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
d600cbed DM	387	int ret, rd = ((insn >> 25) & 0x1f);
d600cbed DM	388	u64 value;
1da177e4	389
a8b0ca17	390	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
1da177e4 LT	391	if (insn & 0x2000) {
	392	maybe_flush_windows(0, 0, rd, from_kernel);
	393	value = sign_extend_imm13(insn);
	394	} else {
	395	maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
	396	value = fetch_reg(insn & 0x1f, regs);
	397	}
d600cbed	398	ret = hweight64(value);
1da177e4 LT	399	if (rd < 16) {
	400	if (rd)
	401	regs->u_regs[rd] = ret;
	402	} else {
517ffce4 DM	403	unsigned long fp = regs->u_regs[UREG_FP];
	404
	405	if (!test_thread_64bit_stack(fp)) {
1da177e4	406	struct reg_window32 __user *win32;
517ffce4	407	win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
1da177e4 LT	408	put_user(ret, &win32->locals[rd - 16]);
	409	} else {
	410	struct reg_window __user *win;
517ffce4	411	win = (struct reg_window __user *)(fp + STACK_BIAS);
1da177e4 LT	412	put_user(ret, &win->locals[rd - 16]);
	413	}
	414	}
	415	advance(regs);
	416	return 1;
	417	}
	418
	419	extern void do_fpother(struct pt_regs *regs);
	420	extern void do_privact(struct pt_regs *regs);
6c52a96e DM	421	extern void spitfire_data_access_exception(struct pt_regs *regs,
	422	unsigned long sfsr,
	423	unsigned long sfar);
ed6b0b45 DM	424	extern void sun4v_data_access_exception(struct pt_regs *regs,
	425	unsigned long addr,
	426	unsigned long type_ctx);
1da177e4 LT	427
	428	int handle_ldf_stq(u32 insn, struct pt_regs *regs)
	429	{
	430	unsigned long addr = compute_effective_address(regs, insn, 0);
	431	int freg = ((insn >> 25) & 0x1e) \| ((insn >> 20) & 0x20);
	432	struct fpustate *f = FPUSTATE;
	433	int asi = decode_asi(insn, regs);
	434	int flag = (freg < 32) ? FPRS_DL : FPRS_DU;
	435
a8b0ca17	436	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
121dd5f2	437
1da177e4 LT	438	save_and_clear_fpu();
	439	current_thread_info()->xfsr[0] &= ~0x1c000;
	440	if (freg & 3) {
	441	current_thread_info()->xfsr[0] \|= (6 << 14) /* invalid_fp_register */;
	442	do_fpother(regs);
	443	return 0;
	444	}
	445	if (insn & 0x200000) {
	446	/* STQ */
	447	u64 first = 0, second = 0;
	448
	449	if (current_thread_info()->fpsaved[0] & flag) {
	450	first = (u64 )&f->regs[freg];
	451	second = (u64 )&f->regs[freg+2];
	452	}
	453	if (asi < 0x80) {
	454	do_privact(regs);
	455	return 1;
	456	}
	457	switch (asi) {
	458	case ASI_P:
	459	case ASI_S: break;
	460	case ASI_PL:
	461	case ASI_SL:
	462	{
	463	/* Need to convert endians */
	464	u64 tmp = __swab64p(&first);
	465
	466	first = __swab64p(&second);
	467	second = tmp;
	468	break;
	469	}
	470	default:
ed6b0b45 DM	471	if (tlb_type == hypervisor)
	472	sun4v_data_access_exception(regs, addr, 0);
	473	else
	474	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	475	return 1;
	476	}
	477	if (put_user (first >> 32, (u32 __user *)addr) \|\|
	478	__put_user ((u32)first, (u32 __user *)(addr + 4)) \|\|
	479	__put_user (second >> 32, (u32 __user *)(addr + 8)) \|\|
	480	__put_user ((u32)second, (u32 __user *)(addr + 12))) {
ed6b0b45 DM	481	if (tlb_type == hypervisor)
	482	sun4v_data_access_exception(regs, addr, 0);
	483	else
	484	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	485	return 1;
	486	}
	487	} else {
	488	/* LDF, LDDF, LDQF */
	489	u32 data[4] __attribute__ ((aligned(8)));
	490	int size, i;
	491	int err;
	492
	493	if (asi < 0x80) {
	494	do_privact(regs);
	495	return 1;
	496	} else if (asi > ASI_SNFL) {
ed6b0b45 DM	497	if (tlb_type == hypervisor)
	498	sun4v_data_access_exception(regs, addr, 0);
	499	else
	500	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	501	return 1;
	502	}
	503	switch (insn & 0x180000) {
	504	case 0x000000: size = 1; break;
	505	case 0x100000: size = 4; break;
	506	default: size = 2; break;
	507	}
	508	for (i = 0; i < size; i++)
	509	data[i] = 0;
	510
	511	err = get_user (data[0], (u32 __user *) addr);
	512	if (!err) {
	513	for (i = 1; i < size; i++)
	514	err \|= __get_user (data[i], (u32 __user )(addr + 4i));
	515	}
	516	if (err && !(asi & 0x2 /* NF */)) {
ed6b0b45 DM	517	if (tlb_type == hypervisor)
	518	sun4v_data_access_exception(regs, addr, 0);
	519	else
	520	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	521	return 1;
	522	}
	523	if (asi & 0x8) /* Little */ {
	524	u64 tmp;
	525
	526	switch (size) {
	527	case 1: data[0] = le32_to_cpup(data + 0); break;
	528	default:(u64 )(data + 0) = le64_to_cpup((u64 *)(data + 0));
	529	break;
	530	case 4: tmp = le64_to_cpup((u64 *)(data + 0));
	531	(u64 )(data + 0) = le64_to_cpup((u64 *)(data + 2));
	532	(u64 )(data + 2) = tmp;
	533	break;
	534	}
	535	}
	536	if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
	537	current_thread_info()->fpsaved[0] = FPRS_FEF;
	538	current_thread_info()->gsr[0] = 0;
	539	}
	540	if (!(current_thread_info()->fpsaved[0] & flag)) {
	541	if (freg < 32)
	542	memset(f->regs, 0, 32*sizeof(u32));
	543	else
	544	memset(f->regs+32, 0, 32*sizeof(u32));
	545	}
	546	memcpy(f->regs + freg, data, size * 4);
	547	current_thread_info()->fpsaved[0] \|= flag;
	548	}
	549	advance(regs);
	550	return 1;
	551	}
	552
	553	void handle_ld_nf(u32 insn, struct pt_regs *regs)
	554	{
	555	int rd = ((insn >> 25) & 0x1f);
	556	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	557	unsigned long *reg;
	558
a8b0ca17	559	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
121dd5f2	560
1da177e4 LT	561	maybe_flush_windows(0, 0, rd, from_kernel);
	562	reg = fetch_reg_addr(rd, regs);
	563	if (from_kernel \|\| rd < 16) {
	564	reg[0] = 0;
	565	if ((insn & 0x780000) == 0x180000)
	566	reg[1] = 0;
517ffce4	567	} else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
1da177e4 LT	568	put_user(0, (int __user *) reg);
	569	if ((insn & 0x780000) == 0x180000)
	570	put_user(0, ((int __user *) reg) + 1);
	571	} else {
	572	put_user(0, (unsigned long __user *) reg);
	573	if ((insn & 0x780000) == 0x180000)
	574	put_user(0, (unsigned long __user *) reg + 1);
	575	}
	576	advance(regs);
	577	}
	578
	579	void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
	580	{
	581	unsigned long pc = regs->tpc;
	582	unsigned long tstate = regs->tstate;
	583	u32 insn;
1da177e4	584	u64 value;
ed6b0b45	585	u8 freg;
1da177e4 LT	586	int flag;
	587	struct fpustate *f = FPUSTATE;
	588
	589	if (tstate & TSTATE_PRIV)
	590	die_if_kernel("lddfmna from kernel", regs);
a8b0ca17	591	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
1da177e4 LT	592	if (test_thread_flag(TIF_32BIT))
	593	pc = (u32)pc;
	594	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
ed6b0b45	595	int asi = decode_asi(insn, regs);
b41418f4	596	u32 first, second;
18b8e08e DM	597	int err;
18b8e08e DM	598
1da177e4 LT	599	if ((asi > ASI_SNFL) \|\|
	600	(asi < ASI_P))
	601	goto daex;
b41418f4	602	first = second = 0;
18b8e08e DM	603	err = get_user(first, (u32 __user *)sfar);
	604	if (!err)
	605	err = get_user(second, (u32 __user *)(sfar + 4));
	606	if (err) {
b41418f4	607	if (!(asi & 0x2))
1da177e4	608	goto daex;
b41418f4	609	first = second = 0;
1da177e4 LT	610	}
	611	save_and_clear_fpu();
	612	freg = ((insn >> 25) & 0x1e) \| ((insn >> 20) & 0x20);
	613	value = (((u64)first) << 32) \| second;
	614	if (asi & 0x8) /* Little */
	615	value = __swab64p(&value);
	616	flag = (freg < 32) ? FPRS_DL : FPRS_DU;
	617	if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
	618	current_thread_info()->fpsaved[0] = FPRS_FEF;
	619	current_thread_info()->gsr[0] = 0;
	620	}
	621	if (!(current_thread_info()->fpsaved[0] & flag)) {
	622	if (freg < 32)
	623	memset(f->regs, 0, 32*sizeof(u32));
	624	else
	625	memset(f->regs+32, 0, 32*sizeof(u32));
	626	}
	627	(u64 )(f->regs + freg) = value;
	628	current_thread_info()->fpsaved[0] \|= flag;
	629	} else {
ed6b0b45 DM	630	daex:
	631	if (tlb_type == hypervisor)
	632	sun4v_data_access_exception(regs, sfar, sfsr);
	633	else
	634	spitfire_data_access_exception(regs, sfsr, sfar);
1da177e4 LT	635	return;
	636	}
	637	advance(regs);
1da177e4 LT	638	}
	639
	640	void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
	641	{
	642	unsigned long pc = regs->tpc;
	643	unsigned long tstate = regs->tstate;
	644	u32 insn;
	645	u64 value;
ed6b0b45	646	u8 freg;
1da177e4 LT	647	int flag;
	648	struct fpustate *f = FPUSTATE;
	649
	650	if (tstate & TSTATE_PRIV)
	651	die_if_kernel("stdfmna from kernel", regs);
a8b0ca17	652	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
1da177e4 LT	653	if (test_thread_flag(TIF_32BIT))
	654	pc = (u32)pc;
	655	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
ed6b0b45	656	int asi = decode_asi(insn, regs);
1da177e4	657	freg = ((insn >> 25) & 0x1e) \| ((insn >> 20) & 0x20);
1da177e4 LT	658	value = 0;
	659	flag = (freg < 32) ? FPRS_DL : FPRS_DU;
	660	if ((asi > ASI_SNFL) \|\|
	661	(asi < ASI_P))
	662	goto daex;
	663	save_and_clear_fpu();
	664	if (current_thread_info()->fpsaved[0] & flag)
	665	value = (u64 )&f->regs[freg];
	666	switch (asi) {
	667	case ASI_P:
	668	case ASI_S: break;
	669	case ASI_PL:
	670	case ASI_SL:
	671	value = __swab64p(&value); break;
	672	default: goto daex;
	673	}
	674	if (put_user (value >> 32, (u32 __user *) sfar) \|\|
	675	__put_user ((u32)value, (u32 __user *)(sfar + 4)))
	676	goto daex;
	677	} else {
ed6b0b45 DM	678	daex:
	679	if (tlb_type == hypervisor)
	680	sun4v_data_access_exception(regs, sfar, sfsr);
	681	else
	682	spitfire_data_access_exception(regs, sfsr, sfar);
1da177e4 LT	683	return;
	684	}
	685	advance(regs);
1da177e4	686	}