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mm: thp: Use more portable PMD clearing sequenece in zap_huge_pmd().
[deliverable/linux.git] / arch / sparc / mm / init_64.c
CommitLineData
b00dc837 1/*
1da177e4
LT		 2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
1da177e4
LT		 16#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
c9cf5528 19#include <linux/poison.h>
1da177e4
LT		 20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
13edad7a 24#include <linux/sort.h>
5cbc3073 25#include <linux/percpu.h>
95f72d1e 26#include <linux/memblock.h>
919ee677 27#include <linux/mmzone.h>
5a0e3ad6 28#include <linux/gfp.h>
1da177e4
LT		 29
30#include <asm/head.h>
1da177e4
LT		 31#include <asm/page.h>
32#include <asm/pgalloc.h>
33#include <asm/pgtable.h>
34#include <asm/oplib.h>
35#include <asm/iommu.h>
36#include <asm/io.h>
37#include <asm/uaccess.h>
38#include <asm/mmu_context.h>
39#include <asm/tlbflush.h>
40#include <asm/dma.h>
41#include <asm/starfire.h>
42#include <asm/tlb.h>
43#include <asm/spitfire.h>
44#include <asm/sections.h>
517af332 45#include <asm/tsb.h>
481295f9 46#include <asm/hypervisor.h>
372b07bb 47#include <asm/prom.h>
5cbc3073 48#include <asm/mdesc.h>
3d5ae6b6 49#include <asm/cpudata.h>
4f70f7a9 50#include <asm/irq.h>
1da177e4 51
27137e52 52#include "init_64.h"
9cc3a1ac 53
4f93d21d 54unsigned long kern_linear_pte_xor[4] __read_mostly;
9cc3a1ac 55
4f93d21d
DM		 56/* A bitmap, two bits for every 256MB of physical memory. These two
57 * bits determine what page size we use for kernel linear
58 * translations. They form an index into kern_linear_pte_xor[]. The
59 * value in the indexed slot is XOR'd with the TLB miss virtual
60 * address to form the resulting TTE. The mapping is:
61 *
62 * 0 ==> 4MB
63 * 1 ==> 256MB
64 * 2 ==> 2GB
65 * 3 ==> 16GB
66 *
67 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
68 * support 2GB pages, and hopefully future cpus will support the 16GB
69 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
70 * if these larger page sizes are not supported by the cpu.
71 *
72 * It would be nice to determine this from the machine description
73 * 'cpu' properties, but we need to have this table setup before the
74 * MDESC is initialized.
9cc3a1ac
DM		 75 */
76unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
77
d1acb421 78#ifndef CONFIG_DEBUG_PAGEALLOC
4f93d21d
DM		 79/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
80 * Space is allocated for this right after the trap table in
81 * arch/sparc64/kernel/head.S
2d9e2763
DM		 82 */
83extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 84#endif
d7744a09 85
ce33fdc5
DM		 86static unsigned long cpu_pgsz_mask;
87
13edad7a
DM		 88#define MAX_BANKS 32
89
9a2ed5cc
DM		 90static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata;
91static int pavail_ents __devinitdata;
13edad7a
DM		 92
93static int cmp_p64(const void *a, const void *b)
94{
95 const struct linux_prom64_registers *x = a, *y = b;
96
97 if (x->phys_addr > y->phys_addr)
98 return 1;
99 if (x->phys_addr < y->phys_addr)
100 return -1;
101 return 0;
102}
103
104static void __init read_obp_memory(const char *property,
105 struct linux_prom64_registers *regs,
106 int *num_ents)
107{
8d125562 108 phandle node = prom_finddevice("/memory");
13edad7a
DM		 109 int prop_size = prom_getproplen(node, property);
110 int ents, ret, i;
111
112 ents = prop_size / sizeof(struct linux_prom64_registers);
113 if (ents > MAX_BANKS) {
114 prom_printf("The machine has more %s property entries than "
115 "this kernel can support (%d).\n",
116 property, MAX_BANKS);
117 prom_halt();
118 }
119
120 ret = prom_getproperty(node, property, (char *) regs, prop_size);
121 if (ret == -1) {
5da444aa
AM		 122 prom_printf("Couldn't get %s property from /memory.\n",
123 property);
13edad7a
DM		 124 prom_halt();
125 }
126
13edad7a
DM		 127 /* Sanitize what we got from the firmware, by page aligning
128 * everything.
129 */
130 for (i = 0; i < ents; i++) {
131 unsigned long base, size;
132
133 base = regs[i].phys_addr;
134 size = regs[i].reg_size;
10147570 135
13edad7a
DM		 136 size &= PAGE_MASK;
137 if (base & ~PAGE_MASK) {
138 unsigned long new_base = PAGE_ALIGN(base);
139
140 size -= new_base - base;
141 if ((long) size < 0L)
142 size = 0UL;
143 base = new_base;
144 }
0015d3d6
DM		 145 if (size == 0UL) {
146 /* If it is empty, simply get rid of it.
147 * This simplifies the logic of the other
148 * functions that process these arrays.
149 */
150 memmove(&regs[i], &regs[i + 1],
151 (ents - i - 1) * sizeof(regs[0]));
486ad10a 152 i--;
0015d3d6
DM		 153 ents--;
154 continue;
486ad10a 155 }
0015d3d6
DM		 156 regs[i].phys_addr = base;
157 regs[i].reg_size = size;
486ad10a
DM		 158 }
159
160 *num_ents = ents;
161
c9c10830 162 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 163 cmp_p64, NULL);
164}
1da177e4 165
d8ed1d43
DM		 166unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
167 sizeof(unsigned long)];
917c3660 168EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
1da177e4 169
d1112018 170/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 171unsigned long kern_base __read_mostly;
172unsigned long kern_size __read_mostly;
1da177e4 173
1da177e4
LT		 174/* Initial ramdisk setup */
175extern unsigned long sparc_ramdisk_image64;
176extern unsigned int sparc_ramdisk_image;
177extern unsigned int sparc_ramdisk_size;
178
1ac4f5eb 179struct page *mem_map_zero __read_mostly;
35802c0b 180EXPORT_SYMBOL(mem_map_zero);
1da177e4 181
0835ae0f
DM		 182unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
183
184unsigned long sparc64_kern_pri_context __read_mostly;
185unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186unsigned long sparc64_kern_sec_context __read_mostly;
187
64658743 188int num_kernel_image_mappings;
1da177e4 189
1da177e4
LT		 190#ifdef CONFIG_DEBUG_DCFLUSH
191atomic_t dcpage_flushes = ATOMIC_INIT(0);
192#ifdef CONFIG_SMP
193atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
194#endif
195#endif
196
7a591cfe 197inline void flush_dcache_page_impl(struct page *page)
1da177e4 198{
7a591cfe 199 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 200#ifdef CONFIG_DEBUG_DCFLUSH
201 atomic_inc(&dcpage_flushes);
202#endif
203
204#ifdef DCACHE_ALIASING_POSSIBLE
205 __flush_dcache_page(page_address(page),
206 ((tlb_type == spitfire) &&
207 page_mapping(page) != NULL));
208#else
209 if (page_mapping(page) != NULL &&
210 tlb_type == spitfire)
211 __flush_icache_page(__pa(page_address(page)));
212#endif
213}
214
215#define PG_dcache_dirty PG_arch_1
22adb358
DM		 216#define PG_dcache_cpu_shift 32UL
217#define PG_dcache_cpu_mask \
218 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 219
220#define dcache_dirty_cpu(page) \
48b0e548 221 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 222
d979f179 223static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 224{
225 unsigned long mask = this_cpu;
48b0e548
DM		 226 unsigned long non_cpu_bits;
227
228 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
230
1da177e4
LT		 231 __asm__ __volatile__("1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "and %%g7, %1, %%g1\n\t"
234 "or %%g1, %0, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
236 "cmp %%g7, %%g1\n\t"
237 "bne,pn %%xcc, 1b\n\t"
b445e26c 238 " nop"
1da177e4
LT		 239 : /* no outputs */
240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
241 : "g1", "g7");
242}
243
d979f179 244static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 245{
246 unsigned long mask = (1UL << PG_dcache_dirty);
247
248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249 "1:\n\t"
250 "ldx [%2], %%g7\n\t"
48b0e548 251 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 252 "and %%g1, %3, %%g1\n\t"
253 "cmp %%g1, %0\n\t"
254 "bne,pn %%icc, 2f\n\t"
255 " andn %%g7, %1, %%g1\n\t"
256 "casx [%2], %%g7, %%g1\n\t"
257 "cmp %%g7, %%g1\n\t"
258 "bne,pn %%xcc, 1b\n\t"
b445e26c 259 " nop\n"
1da177e4
LT		 260 "2:"
261 : /* no outputs */
262 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 263 "i" (PG_dcache_cpu_mask),
264 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 265 : "g1", "g7");
266}
267
517af332
DM		 268static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269{
270 unsigned long tsb_addr = (unsigned long) ent;
271
3b3ab2eb 272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 273 tsb_addr = __pa(tsb_addr);
274
275 __tsb_insert(tsb_addr, tag, pte);
276}
277
c4bce90e 278unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
c4bce90e 279
ff9aefbf 280static void flush_dcache(unsigned long pfn)
1da177e4 281{
ff9aefbf 282 struct page *page;
7a591cfe 283
ff9aefbf 284 page = pfn_to_page(pfn);
1a78cedb 285 if (page) {
7a591cfe 286 unsigned long pg_flags;
7a591cfe 287
ff9aefbf
SR		 288 pg_flags = page->flags;
289 if (pg_flags & (1UL << PG_dcache_dirty)) {
7a591cfe
DM		 290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291 PG_dcache_cpu_mask);
292 int this_cpu = get_cpu();
293
294 /* This is just to optimize away some function calls
295 * in the SMP case.
296 */
297 if (cpu == this_cpu)
298 flush_dcache_page_impl(page);
299 else
300 smp_flush_dcache_page_impl(page, cpu);
301
302 clear_dcache_dirty_cpu(page, cpu);
303
304 put_cpu();
305 }
1da177e4 306 }
ff9aefbf
SR		 307}
308
4b3073e1 309void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
ff9aefbf
SR		 310{
311 struct mm_struct *mm;
312 struct tsb *tsb;
313 unsigned long tag, flags;
314 unsigned long tsb_index, tsb_hash_shift;
4b3073e1 315 pte_t pte = *ptep;
ff9aefbf
SR		 316
317 if (tlb_type != hypervisor) {
318 unsigned long pfn = pte_pfn(pte);
319
320 if (pfn_valid(pfn))
321 flush_dcache(pfn);
322 }
bd40791e
DM		 323
324 mm = vma->vm_mm;
7a1ac526 325
dcc1e8dd
DM		 326 tsb_index = MM_TSB_BASE;
327 tsb_hash_shift = PAGE_SHIFT;
328
7a1ac526
DM		 329 spin_lock_irqsave(&mm->context.lock, flags);
330
dcc1e8dd
DM		 331#ifdef CONFIG_HUGETLB_PAGE
332 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
333 if ((tlb_type == hypervisor &&
334 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
335 (tlb_type != hypervisor &&
336 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
337 tsb_index = MM_TSB_HUGE;
338 tsb_hash_shift = HPAGE_SHIFT;
339 }
340 }
341#endif
342
343 tsb = mm->context.tsb_block[tsb_index].tsb;
344 tsb += ((address >> tsb_hash_shift) &
345 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 346 tag = (address >> 22UL);
347 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 348
349 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 350}
351
352void flush_dcache_page(struct page *page)
353{
a9546f59
DM		 354 struct address_space *mapping;
355 int this_cpu;
1da177e4 356
7a591cfe
DM		 357 if (tlb_type == hypervisor)
358 return;
359
a9546f59
DM		 360 /* Do not bother with the expensive D-cache flush if it
361 * is merely the zero page. The 'bigcore' testcase in GDB
362 * causes this case to run millions of times.
363 */
364 if (page == ZERO_PAGE(0))
365 return;
366
367 this_cpu = get_cpu();
368
369 mapping = page_mapping(page);
1da177e4 370 if (mapping && !mapping_mapped(mapping)) {
a9546f59 371 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 372 if (dirty) {
a9546f59
DM		 373 int dirty_cpu = dcache_dirty_cpu(page);
374
1da177e4
LT		 375 if (dirty_cpu == this_cpu)
376 goto out;
377 smp_flush_dcache_page_impl(page, dirty_cpu);
378 }
379 set_dcache_dirty(page, this_cpu);
380 } else {
381 /* We could delay the flush for the !page_mapping
382 * case too. But that case is for exec env/arg
383 * pages and those are %99 certainly going to get
384 * faulted into the tlb (and thus flushed) anyways.
385 */
386 flush_dcache_page_impl(page);
387 }
388
389out:
390 put_cpu();
391}
917c3660 392EXPORT_SYMBOL(flush_dcache_page);
1da177e4 393
05e14cb3 394void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 395{
a43fe0e7 396 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 397 if (tlb_type == spitfire) {
398 unsigned long kaddr;
399
a94aa253
DM		 400 /* This code only runs on Spitfire cpus so this is
401 * why we can assume _PAGE_PADDR_4U.
402 */
403 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
404 unsigned long paddr, mask = _PAGE_PADDR_4U;
405
406 if (kaddr >= PAGE_OFFSET)
407 paddr = kaddr & mask;
408 else {
409 pgd_t *pgdp = pgd_offset_k(kaddr);
410 pud_t *pudp = pud_offset(pgdp, kaddr);
411 pmd_t *pmdp = pmd_offset(pudp, kaddr);
412 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
413
414 paddr = pte_val(*ptep) & mask;
415 }
416 __flush_icache_page(paddr);
417 }
1da177e4
LT		 418 }
419}
917c3660 420EXPORT_SYMBOL(flush_icache_range);
1da177e4 421
1da177e4
LT		 422void mmu_info(struct seq_file *m)
423{
ce33fdc5
DM		 424 static const char *pgsz_strings[] = {
425 "8K", "64K", "512K", "4MB", "32MB",
426 "256MB", "2GB", "16GB",
427 };
428 int i, printed;
429
1da177e4
LT		 430 if (tlb_type == cheetah)
431 seq_printf(m, "MMU Type\t: Cheetah\n");
432 else if (tlb_type == cheetah_plus)
433 seq_printf(m, "MMU Type\t: Cheetah+\n");
434 else if (tlb_type == spitfire)
435 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 436 else if (tlb_type == hypervisor)
437 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 438 else
439 seq_printf(m, "MMU Type\t: ???\n");
440
ce33fdc5
DM		 441 seq_printf(m, "MMU PGSZs\t: ");
442 printed = 0;
443 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
444 if (cpu_pgsz_mask & (1UL << i)) {
445 seq_printf(m, "%s%s",
446 printed ? "," : "", pgsz_strings[i]);
447 printed++;
448 }
449 }
450 seq_putc(m, '\n');
451
1da177e4
LT		 452#ifdef CONFIG_DEBUG_DCFLUSH
453 seq_printf(m, "DCPageFlushes\t: %d\n",
454 atomic_read(&dcpage_flushes));
455#ifdef CONFIG_SMP
456 seq_printf(m, "DCPageFlushesXC\t: %d\n",
457 atomic_read(&dcpage_flushes_xcall));
458#endif /* CONFIG_SMP */
459#endif /* CONFIG_DEBUG_DCFLUSH */
460}
461
a94aa253
DM		 462struct linux_prom_translation prom_trans[512] __read_mostly;
463unsigned int prom_trans_ents __read_mostly;
464
1da177e4
LT		 465unsigned long kern_locked_tte_data;
466
c9c10830
DM		 467/* The obp translations are saved based on 8k pagesize, since obp can
468 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 469 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 470 */
5085b4a5
DM		 471static inline int in_obp_range(unsigned long vaddr)
472{
473 return (vaddr >= LOW_OBP_ADDRESS &&
474 vaddr < HI_OBP_ADDRESS);
475}
476
c9c10830 477static int cmp_ptrans(const void *a, const void *b)
405599bd 478{
c9c10830 479 const struct linux_prom_translation *x = a, *y = b;
405599bd 480
c9c10830
DM		 481 if (x->virt > y->virt)
482 return 1;
483 if (x->virt < y->virt)
484 return -1;
485 return 0;
405599bd
DM		 486}
487
c9c10830 488/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 489static void __init read_obp_translations(void)
405599bd 490{
c9c10830 491 int n, node, ents, first, last, i;
1da177e4
LT		 492
493 node = prom_finddevice("/virtual-memory");
494 n = prom_getproplen(node, "translations");
405599bd 495 if (unlikely(n == 0 || n == -1)) {
b206fc4c 496 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 497 prom_halt();
498 }
405599bd 499 if (unlikely(n > sizeof(prom_trans))) {
5da444aa 500 prom_printf("prom_mappings: Size %d is too big.\n", n);
1da177e4
LT		 501 prom_halt();
502 }
405599bd 503
b206fc4c 504 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 505 (char *)&prom_trans[0],
506 sizeof(prom_trans))) == -1) {
b206fc4c 507 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 508 prom_halt();
509 }
9ad98c5b 510
b206fc4c 511 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 512
c9c10830
DM		 513 ents = n;
514
515 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
516 cmp_ptrans, NULL);
517
518 /* Now kick out all the non-OBP entries. */
519 for (i = 0; i < ents; i++) {
520 if (in_obp_range(prom_trans[i].virt))
521 break;
522 }
523 first = i;
524 for (; i < ents; i++) {
525 if (!in_obp_range(prom_trans[i].virt))
526 break;
527 }
528 last = i;
529
530 for (i = 0; i < (last - first); i++) {
531 struct linux_prom_translation *src = &prom_trans[i + first];
532 struct linux_prom_translation *dest = &prom_trans[i];
533
534 *dest = *src;
535 }
536 for (; i < ents; i++) {
537 struct linux_prom_translation *dest = &prom_trans[i];
538 dest->virt = dest->size = dest->data = 0x0UL;
539 }
540
541 prom_trans_ents = last - first;
542
543 if (tlb_type == spitfire) {
544 /* Clear diag TTE bits. */
545 for (i = 0; i < prom_trans_ents; i++)
546 prom_trans[i].data &= ~0x0003fe0000000000UL;
547 }
f4142cba
DM		 548
549 /* Force execute bit on. */
550 for (i = 0; i < prom_trans_ents; i++)
551 prom_trans[i].data |= (tlb_type == hypervisor ?
552 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
405599bd 553}
1da177e4 554
d82ace7d
DM		 555static void __init hypervisor_tlb_lock(unsigned long vaddr,
556 unsigned long pte,
557 unsigned long mmu)
558{
7db35f31
DM		 559 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
560
561 if (ret != 0) {
5da444aa 562 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
7db35f31 563 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 564 prom_halt();
565 }
d82ace7d
DM		 566}
567
c4bce90e
DM		 568static unsigned long kern_large_tte(unsigned long paddr);
569
898cf0ec 570static void __init remap_kernel(void)
405599bd
DM		 571{
572 unsigned long phys_page, tte_vaddr, tte_data;
64658743 573 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 574
1da177e4 575 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 576 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 577 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 578
579 kern_locked_tte_data = tte_data;
580
d82ace7d
DM		 581 /* Now lock us into the TLBs via Hypervisor or OBP. */
582 if (tlb_type == hypervisor) {
64658743 583 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 584 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
585 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 586 tte_vaddr += 0x400000;
587 tte_data += 0x400000;
d82ace7d
DM		 588 }
589 } else {
64658743
DM		 590 for (i = 0; i < num_kernel_image_mappings; i++) {
591 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
592 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
593 tte_vaddr += 0x400000;
594 tte_data += 0x400000;
d82ace7d 595 }
64658743 596 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 597 }
0835ae0f
DM		 598 if (tlb_type == cheetah_plus) {
599 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
600 CTX_CHEETAH_PLUS_NUC);
601 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
602 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
603 }
405599bd 604}
1da177e4 605
405599bd 606
c9c10830 607static void __init inherit_prom_mappings(void)
9ad98c5b 608{
405599bd 609 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 610 printk("Remapping the kernel... ");
405599bd 611 remap_kernel();
3c62a2d3 612 printk("done.\n");
1da177e4
LT		 613}
614
1da177e4
LT		 615void prom_world(int enter)
616{
1da177e4
LT		 617 if (!enter)
618 set_fs((mm_segment_t) { get_thread_current_ds() });
619
3487d1d4 620 __asm__ __volatile__("flushw");
1da177e4
LT		 621}
622
1da177e4
LT		 623void __flush_dcache_range(unsigned long start, unsigned long end)
624{
625 unsigned long va;
626
627 if (tlb_type == spitfire) {
628 int n = 0;
629
630 for (va = start; va < end; va += 32) {
631 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
632 if (++n >= 512)
633 break;
634 }
a43fe0e7 635 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 636 start = __pa(start);
637 end = __pa(end);
638 for (va = start; va < end; va += 32)
639 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
640 "membar #Sync"
641 : /* no outputs */
642 : "r" (va),
643 "i" (ASI_DCACHE_INVALIDATE));
644 }
645}
917c3660 646EXPORT_SYMBOL(__flush_dcache_range);
1da177e4 647
85f1e1f6
DM		 648/* get_new_mmu_context() uses "cache + 1". */
649DEFINE_SPINLOCK(ctx_alloc_lock);
650unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
651#define MAX_CTX_NR (1UL << CTX_NR_BITS)
652#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
653DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
654
1da177e4
LT		 655/* Caller does TLB context flushing on local CPU if necessary.
656 * The caller also ensures that CTX_VALID(mm->context) is false.
657 *
658 * We must be careful about boundary cases so that we never
659 * let the user have CTX 0 (nucleus) or we ever use a CTX
660 * version of zero (and thus NO_CONTEXT would not be caught
661 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 662 *
663 * Always invoked with interrupts disabled.
1da177e4
LT		 664 */
665void get_new_mmu_context(struct mm_struct *mm)
666{
667 unsigned long ctx, new_ctx;
668 unsigned long orig_pgsz_bits;
a77754b4 669 unsigned long flags;
a0663a79 670 int new_version;
1da177e4 671
a77754b4 672 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 673 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
674 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
675 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 676 new_version = 0;
1da177e4
LT		 677 if (new_ctx >= (1 << CTX_NR_BITS)) {
678 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
679 if (new_ctx >= ctx) {
680 int i;
681 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
682 CTX_FIRST_VERSION;
683 if (new_ctx == 1)
684 new_ctx = CTX_FIRST_VERSION;
685
686 /* Don't call memset, for 16 entries that's just
687 * plain silly...
688 */
689 mmu_context_bmap[0] = 3;
690 mmu_context_bmap[1] = 0;
691 mmu_context_bmap[2] = 0;
692 mmu_context_bmap[3] = 0;
693 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
694 mmu_context_bmap[i + 0] = 0;
695 mmu_context_bmap[i + 1] = 0;
696 mmu_context_bmap[i + 2] = 0;
697 mmu_context_bmap[i + 3] = 0;
698 }
a0663a79 699 new_version = 1;
1da177e4
LT		 700 goto out;
701 }
702 }
703 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
704 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
705out:
706 tlb_context_cache = new_ctx;
707 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 708 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 709
710 if (unlikely(new_version))
711 smp_new_mmu_context_version();
1da177e4
LT		 712}
713
919ee677
DM		 714static int numa_enabled = 1;
715static int numa_debug;
716
717static int __init early_numa(char *p)
1da177e4 718{
919ee677
DM		 719 if (!p)
720 return 0;
721
722 if (strstr(p, "off"))
723 numa_enabled = 0;
d1112018 724
919ee677
DM		 725 if (strstr(p, "debug"))
726 numa_debug = 1;
d1112018 727
919ee677 728 return 0;
d1112018 729}
919ee677
DM		 730early_param("numa", early_numa);
731
732#define numadbg(f, a...) \
733do { if (numa_debug) \
734 printk(KERN_INFO f, ## a); \
735} while (0)
d1112018 736
4e82c9a6
DM		 737static void __init find_ramdisk(unsigned long phys_base)
738{
739#ifdef CONFIG_BLK_DEV_INITRD
740 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
741 unsigned long ramdisk_image;
742
743 /* Older versions of the bootloader only supported a
744 * 32-bit physical address for the ramdisk image
745 * location, stored at sparc_ramdisk_image. Newer
746 * SILO versions set sparc_ramdisk_image to zero and
747 * provide a full 64-bit physical address at
748 * sparc_ramdisk_image64.
749 */
750 ramdisk_image = sparc_ramdisk_image;
751 if (!ramdisk_image)
752 ramdisk_image = sparc_ramdisk_image64;
753
754 /* Another bootloader quirk. The bootloader normalizes
755 * the physical address to KERNBASE, so we have to
756 * factor that back out and add in the lowest valid
757 * physical page address to get the true physical address.
758 */
759 ramdisk_image -= KERNBASE;
760 ramdisk_image += phys_base;
761
919ee677
DM		 762 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
763 ramdisk_image, sparc_ramdisk_size);
764
4e82c9a6
DM		 765 initrd_start = ramdisk_image;
766 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23 767
95f72d1e 768 memblock_reserve(initrd_start, sparc_ramdisk_size);
d45100f7
DM		 769
770 initrd_start += PAGE_OFFSET;
771 initrd_end += PAGE_OFFSET;
4e82c9a6
DM		 772 }
773#endif
774}
775
919ee677
DM		 776struct node_mem_mask {
777 unsigned long mask;
778 unsigned long val;
919ee677
DM		 779};
780static struct node_mem_mask node_masks[MAX_NUMNODES];
781static int num_node_masks;
782
783int numa_cpu_lookup_table[NR_CPUS];
784cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
785
786#ifdef CONFIG_NEED_MULTIPLE_NODES
919ee677
DM		 787
788struct mdesc_mblock {
789 u64 base;
790 u64 size;
791 u64 offset; /* RA-to-PA */
792};
793static struct mdesc_mblock *mblocks;
794static int num_mblocks;
795
796static unsigned long ra_to_pa(unsigned long addr)
797{
798 int i;
799
800 for (i = 0; i < num_mblocks; i++) {
801 struct mdesc_mblock *m = &mblocks[i];
802
803 if (addr >= m->base &&
804 addr < (m->base + m->size)) {
805 addr += m->offset;
806 break;
807 }
808 }
809 return addr;
810}
811
812static int find_node(unsigned long addr)
813{
814 int i;
815
816 addr = ra_to_pa(addr);
817 for (i = 0; i < num_node_masks; i++) {
818 struct node_mem_mask *p = &node_masks[i];
819
820 if ((addr & p->mask) == p->val)
821 return i;
822 }
823 return -1;
824}
825
f9b18db3 826static u64 memblock_nid_range(u64 start, u64 end, int *nid)
919ee677
DM		 827{
828 *nid = find_node(start);
829 start += PAGE_SIZE;
830 while (start < end) {
831 int n = find_node(start);
832
833 if (n != *nid)
834 break;
835 start += PAGE_SIZE;
836 }
837
c918dcce
DM		 838 if (start > end)
839 start = end;
840
919ee677
DM		 841 return start;
842}
919ee677
DM		 843#endif
844
845/* This must be invoked after performing all of the necessary
2a4814df 846 * memblock_set_node() calls for 'nid'. We need to be able to get
919ee677 847 * correct data from get_pfn_range_for_nid().
f1cfdb55 848 */
919ee677
DM		 849static void __init allocate_node_data(int nid)
850{
919ee677 851 struct pglist_data *p;
aa6f0790 852 unsigned long start_pfn, end_pfn;
919ee677 853#ifdef CONFIG_NEED_MULTIPLE_NODES
aa6f0790
PG		 854 unsigned long paddr;
855
9d1e2492 856 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
919ee677
DM		 857 if (!paddr) {
858 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
859 prom_halt();
860 }
861 NODE_DATA(nid) = __va(paddr);
862 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
863
625d693e 864 NODE_DATA(nid)->node_id = nid;
919ee677
DM		 865#endif
866
867 p = NODE_DATA(nid);
868
869 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
870 p->node_start_pfn = start_pfn;
871 p->node_spanned_pages = end_pfn - start_pfn;
919ee677
DM		 872}
873
874static void init_node_masks_nonnuma(void)
d1112018 875{
1da177e4
LT		 876 int i;
877
919ee677 878 numadbg("Initializing tables for non-numa.\n");
6fc5bae7 879
919ee677
DM		 880 node_masks[0].mask = node_masks[0].val = 0;
881 num_node_masks = 1;
d1112018 882
919ee677
DM		 883 for (i = 0; i < NR_CPUS; i++)
884 numa_cpu_lookup_table[i] = 0;
1da177e4 885
fb1fece5 886 cpumask_setall(&numa_cpumask_lookup_table[0]);
919ee677
DM		 887}
888
889#ifdef CONFIG_NEED_MULTIPLE_NODES
890struct pglist_data *node_data[MAX_NUMNODES];
891
892EXPORT_SYMBOL(numa_cpu_lookup_table);
893EXPORT_SYMBOL(numa_cpumask_lookup_table);
894EXPORT_SYMBOL(node_data);
895
896struct mdesc_mlgroup {
897 u64 node;
898 u64 latency;
899 u64 match;
900 u64 mask;
901};
902static struct mdesc_mlgroup *mlgroups;
903static int num_mlgroups;
904
905static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
906 u32 cfg_handle)
907{
908 u64 arc;
909
910 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
911 u64 target = mdesc_arc_target(md, arc);
912 const u64 *val;
913
914 val = mdesc_get_property(md, target,
915 "cfg-handle", NULL);
916 if (val && *val == cfg_handle)
917 return 0;
918 }
919 return -ENODEV;
920}
921
922static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
923 u32 cfg_handle)
924{
925 u64 arc, candidate, best_latency = ~(u64)0;
926
927 candidate = MDESC_NODE_NULL;
928 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
929 u64 target = mdesc_arc_target(md, arc);
930 const char *name = mdesc_node_name(md, target);
931 const u64 *val;
932
933 if (strcmp(name, "pio-latency-group"))
934 continue;
935
936 val = mdesc_get_property(md, target, "latency", NULL);
937 if (!val)
938 continue;
939
940 if (*val < best_latency) {
941 candidate = target;
942 best_latency = *val;
943 }
944 }
945
946 if (candidate == MDESC_NODE_NULL)
947 return -ENODEV;
948
949 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
950}
951
952int of_node_to_nid(struct device_node *dp)
953{
954 const struct linux_prom64_registers *regs;
955 struct mdesc_handle *md;
956 u32 cfg_handle;
957 int count, nid;
958 u64 grp;
959
072bd413
DM		 960 /* This is the right thing to do on currently supported
961 * SUN4U NUMA platforms as well, as the PCI controller does
962 * not sit behind any particular memory controller.
963 */
919ee677
DM		 964 if (!mlgroups)
965 return -1;
966
967 regs = of_get_property(dp, "reg", NULL);
968 if (!regs)
969 return -1;
970
971 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
972
973 md = mdesc_grab();
974
975 count = 0;
976 nid = -1;
977 mdesc_for_each_node_by_name(md, grp, "group") {
978 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
979 nid = count;
980 break;
981 }
982 count++;
983 }
984
985 mdesc_release(md);
986
987 return nid;
988}
989
01c45381 990static void __init add_node_ranges(void)
919ee677 991{
08b84798 992 struct memblock_region *reg;
919ee677 993
08b84798
BH		 994 for_each_memblock(memory, reg) {
995 unsigned long size = reg->size;
919ee677
DM		 996 unsigned long start, end;
997
08b84798 998 start = reg->base;
919ee677
DM		 999 end = start + size;
1000 while (start < end) {
1001 unsigned long this_end;
1002 int nid;
1003
35a1f0bd 1004 this_end = memblock_nid_range(start, end, &nid);
919ee677 1005
2a4814df 1006 numadbg("Setting memblock NUMA node nid[%d] "
919ee677
DM		 1007 "start[%lx] end[%lx]\n",
1008 nid, start, this_end);
1009
2a4814df 1010 memblock_set_node(start, this_end - start, nid);
919ee677
DM		 1011 start = this_end;
1012 }
1013 }
1014}
1015
1016static int __init grab_mlgroups(struct mdesc_handle *md)
1017{
1018 unsigned long paddr;
1019 int count = 0;
1020 u64 node;
1021
1022 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1023 count++;
1024 if (!count)
1025 return -ENOENT;
1026
95f72d1e 1027 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
919ee677
DM		 1028 SMP_CACHE_BYTES);
1029 if (!paddr)
1030 return -ENOMEM;
1031
1032 mlgroups = __va(paddr);
1033 num_mlgroups = count;
1034
1035 count = 0;
1036 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1037 struct mdesc_mlgroup *m = &mlgroups[count++];
1038 const u64 *val;
1039
1040 m->node = node;
1041
1042 val = mdesc_get_property(md, node, "latency", NULL);
1043 m->latency = *val;
1044 val = mdesc_get_property(md, node, "address-match", NULL);
1045 m->match = *val;
1046 val = mdesc_get_property(md, node, "address-mask", NULL);
1047 m->mask = *val;
1048
90181136
SR		 1049 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1050 "match[%llx] mask[%llx]\n",
919ee677
DM		 1051 count - 1, m->node, m->latency, m->match, m->mask);
1052 }
1053
1054 return 0;
1055}
1056
1057static int __init grab_mblocks(struct mdesc_handle *md)
1058{
1059 unsigned long paddr;
1060 int count = 0;
1061 u64 node;
1062
1063 mdesc_for_each_node_by_name(md, node, "mblock")
1064 count++;
1065 if (!count)
1066 return -ENOENT;
1067
95f72d1e 1068 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
919ee677
DM		 1069 SMP_CACHE_BYTES);
1070 if (!paddr)
1071 return -ENOMEM;
1072
1073 mblocks = __va(paddr);
1074 num_mblocks = count;
1075
1076 count = 0;
1077 mdesc_for_each_node_by_name(md, node, "mblock") {
1078 struct mdesc_mblock *m = &mblocks[count++];
1079 const u64 *val;
1080
1081 val = mdesc_get_property(md, node, "base", NULL);
1082 m->base = *val;
1083 val = mdesc_get_property(md, node, "size", NULL);
1084 m->size = *val;
1085 val = mdesc_get_property(md, node,
1086 "address-congruence-offset", NULL);
1087 m->offset = *val;
1088
90181136 1089 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
919ee677
DM		 1090 count - 1, m->base, m->size, m->offset);
1091 }
1092
1093 return 0;
1094}
1095
1096static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1097 u64 grp, cpumask_t *mask)
1098{
1099 u64 arc;
1100
fb1fece5 1101 cpumask_clear(mask);
919ee677
DM		 1102
1103 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1104 u64 target = mdesc_arc_target(md, arc);
1105 const char *name = mdesc_node_name(md, target);
1106 const u64 *id;
1107
1108 if (strcmp(name, "cpu"))
1109 continue;
1110 id = mdesc_get_property(md, target, "id", NULL);
e305cb8f 1111 if (*id < nr_cpu_ids)
fb1fece5 1112 cpumask_set_cpu(*id, mask);
919ee677
DM		 1113 }
1114}
1115
1116static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1117{
1118 int i;
1119
1120 for (i = 0; i < num_mlgroups; i++) {
1121 struct mdesc_mlgroup *m = &mlgroups[i];
1122 if (m->node == node)
1123 return m;
1124 }
1125 return NULL;
1126}
1127
1128static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1129 int index)
1130{
1131 struct mdesc_mlgroup *candidate = NULL;
1132 u64 arc, best_latency = ~(u64)0;
1133 struct node_mem_mask *n;
1134
1135 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1136 u64 target = mdesc_arc_target(md, arc);
1137 struct mdesc_mlgroup *m = find_mlgroup(target);
1138 if (!m)
1139 continue;
1140 if (m->latency < best_latency) {
1141 candidate = m;
1142 best_latency = m->latency;
1143 }
1144 }
1145 if (!candidate)
1146 return -ENOENT;
1147
1148 if (num_node_masks != index) {
1149 printk(KERN_ERR "Inconsistent NUMA state, "
1150 "index[%d] != num_node_masks[%d]\n",
1151 index, num_node_masks);
1152 return -EINVAL;
1153 }
1154
1155 n = &node_masks[num_node_masks++];
1156
1157 n->mask = candidate->mask;
1158 n->val = candidate->match;
1da177e4 1159
90181136 1160 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
919ee677 1161 index, n->mask, n->val, candidate->latency);
1da177e4 1162
919ee677
DM		 1163 return 0;
1164}
1165
1166static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1167 int index)
1168{
1169 cpumask_t mask;
1170 int cpu;
1171
1172 numa_parse_mdesc_group_cpus(md, grp, &mask);
1173
fb1fece5 1174 for_each_cpu(cpu, &mask)
919ee677 1175 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1176 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
919ee677
DM		 1177
1178 if (numa_debug) {
1179 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
fb1fece5 1180 for_each_cpu(cpu, &mask)
919ee677
DM		 1181 printk("%d ", cpu);
1182 printk("]\n");
1183 }
1184
1185 return numa_attach_mlgroup(md, grp, index);
1186}
1187
1188static int __init numa_parse_mdesc(void)
1189{
1190 struct mdesc_handle *md = mdesc_grab();
1191 int i, err, count;
1192 u64 node;
1193
1194 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1195 if (node == MDESC_NODE_NULL) {
1196 mdesc_release(md);
1197 return -ENOENT;
1198 }
1199
1200 err = grab_mblocks(md);
1201 if (err < 0)
1202 goto out;
1203
1204 err = grab_mlgroups(md);
1205 if (err < 0)
1206 goto out;
1207
1208 count = 0;
1209 mdesc_for_each_node_by_name(md, node, "group") {
1210 err = numa_parse_mdesc_group(md, node, count);
1211 if (err < 0)
1212 break;
1213 count++;
1214 }
1215
1216 add_node_ranges();
1217
1218 for (i = 0; i < num_node_masks; i++) {
1219 allocate_node_data(i);
1220 node_set_online(i);
1221 }
1222
1223 err = 0;
1224out:
1225 mdesc_release(md);
1226 return err;
1227}
1228
072bd413
DM		 1229static int __init numa_parse_jbus(void)
1230{
1231 unsigned long cpu, index;
1232
1233 /* NUMA node id is encoded in bits 36 and higher, and there is
1234 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1235 */
1236 index = 0;
1237 for_each_present_cpu(cpu) {
1238 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1239 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
072bd413
DM		 1240 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1241 node_masks[index].val = cpu << 36UL;
1242
1243 index++;
1244 }
1245 num_node_masks = index;
1246
1247 add_node_ranges();
1248
1249 for (index = 0; index < num_node_masks; index++) {
1250 allocate_node_data(index);
1251 node_set_online(index);
1252 }
1253
1254 return 0;
1255}
1256
919ee677
DM		 1257static int __init numa_parse_sun4u(void)
1258{
072bd413
DM		 1259 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1260 unsigned long ver;
1261
1262 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1263 if ((ver >> 32UL) == __JALAPENO_ID ||
1264 (ver >> 32UL) == __SERRANO_ID)
1265 return numa_parse_jbus();
1266 }
919ee677
DM		 1267 return -1;
1268}
1269
1270static int __init bootmem_init_numa(void)
1271{
1272 int err = -1;
1273
1274 numadbg("bootmem_init_numa()\n");
1275
1276 if (numa_enabled) {
1277 if (tlb_type == hypervisor)
1278 err = numa_parse_mdesc();
1279 else
1280 err = numa_parse_sun4u();
1281 }
1282 return err;
1283}
1284
1285#else
1da177e4 1286
919ee677
DM		 1287static int bootmem_init_numa(void)
1288{
1289 return -1;
1290}
1291
1292#endif
1293
1294static void __init bootmem_init_nonnuma(void)
1295{
95f72d1e
YL		 1296 unsigned long top_of_ram = memblock_end_of_DRAM();
1297 unsigned long total_ram = memblock_phys_mem_size();
919ee677
DM		 1298
1299 numadbg("bootmem_init_nonnuma()\n");
1300
1301 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1302 top_of_ram, total_ram);
1303 printk(KERN_INFO "Memory hole size: %ldMB\n",
1304 (top_of_ram - total_ram) >> 20);
1305
1306 init_node_masks_nonnuma();
2a4814df 1307 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
919ee677 1308 allocate_node_data(0);
919ee677
DM		 1309 node_set_online(0);
1310}
1311
919ee677
DM		 1312static unsigned long __init bootmem_init(unsigned long phys_base)
1313{
1314 unsigned long end_pfn;
919ee677 1315
95f72d1e 1316 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
919ee677
DM		 1317 max_pfn = max_low_pfn = end_pfn;
1318 min_low_pfn = (phys_base >> PAGE_SHIFT);
1319
1320 if (bootmem_init_numa() < 0)
1321 bootmem_init_nonnuma();
1322
625d693e
DM		 1323 /* Dump memblock with node info. */
1324 memblock_dump_all();
919ee677 1325
625d693e 1326 /* XXX cpu notifier XXX */
d1112018 1327
625d693e 1328 sparse_memory_present_with_active_regions(MAX_NUMNODES);
d1112018
DM		 1329 sparse_init();
1330
1da177e4
LT		 1331 return end_pfn;
1332}
1333
9cc3a1ac
DM		 1334static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1335static int pall_ents __initdata;
1336
56425306 1337#ifdef CONFIG_DEBUG_PAGEALLOC
896aef43
SR		 1338static unsigned long __ref kernel_map_range(unsigned long pstart,
1339 unsigned long pend, pgprot_t prot)
56425306
DM		 1340{
1341 unsigned long vstart = PAGE_OFFSET + pstart;
1342 unsigned long vend = PAGE_OFFSET + pend;
1343 unsigned long alloc_bytes = 0UL;
1344
1345 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1346 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1347 vstart, vend);
1348 prom_halt();
1349 }
1350
1351 while (vstart < vend) {
1352 unsigned long this_end, paddr = __pa(vstart);
1353 pgd_t *pgd = pgd_offset_k(vstart);
1354 pud_t *pud;
1355 pmd_t *pmd;
1356 pte_t *pte;
1357
1358 pud = pud_offset(pgd, vstart);
1359 if (pud_none(*pud)) {
1360 pmd_t *new;
1361
1362 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1363 alloc_bytes += PAGE_SIZE;
1364 pud_populate(&init_mm, pud, new);
1365 }
1366
1367 pmd = pmd_offset(pud, vstart);
1368 if (!pmd_present(*pmd)) {
1369 pte_t *new;
1370
1371 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1372 alloc_bytes += PAGE_SIZE;
1373 pmd_populate_kernel(&init_mm, pmd, new);
1374 }
1375
1376 pte = pte_offset_kernel(pmd, vstart);
1377 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1378 if (this_end > vend)
1379 this_end = vend;
1380
1381 while (vstart < this_end) {
1382 pte_val(*pte) = (paddr | pgprot_val(prot));
1383
1384 vstart += PAGE_SIZE;
1385 paddr += PAGE_SIZE;
1386 pte++;
1387 }
1388 }
1389
1390 return alloc_bytes;
1391}
1392
56425306 1393extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1394#endif /* CONFIG_DEBUG_PAGEALLOC */
1395
4f93d21d 1396static void __init kpte_set_val(unsigned long index, unsigned long val)
9cc3a1ac 1397{
4f93d21d 1398 unsigned long *ptr = kpte_linear_bitmap;
9cc3a1ac 1399
4f93d21d
DM		 1400 val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1401 ptr += (index / (BITS_PER_LONG / 2));
9cc3a1ac 1402
4f93d21d
DM		 1403 *ptr |= val;
1404}
f7c00338 1405
4f93d21d
DM		 1406static const unsigned long kpte_shift_min = 28; /* 256MB */
1407static const unsigned long kpte_shift_max = 34; /* 16GB */
1408static const unsigned long kpte_shift_incr = 3;
9cc3a1ac 1409
4f93d21d
DM		 1410static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1411 unsigned long shift)
1412{
1413 unsigned long size = (1UL << shift);
1414 unsigned long mask = (size - 1UL);
1415 unsigned long remains = end - start;
1416 unsigned long val;
9cc3a1ac 1417
4f93d21d
DM		 1418 if (remains < size || (start & mask))
1419 return start;
9cc3a1ac 1420
4f93d21d
DM		 1421 /* VAL maps:
1422 *
1423 * shift 28 --> kern_linear_pte_xor index 1
1424 * shift 31 --> kern_linear_pte_xor index 2
1425 * shift 34 --> kern_linear_pte_xor index 3
1426 */
1427 val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1428
1429 remains &= ~mask;
1430 if (shift != kpte_shift_max)
1431 remains = size;
1432
1433 while (remains) {
1434 unsigned long index = start >> kpte_shift_min;
1435
1436 kpte_set_val(index, val);
1437
1438 start += 1UL << kpte_shift_min;
1439 remains -= 1UL << kpte_shift_min;
1440 }
1441
1442 return start;
1443}
1444
1445static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1446{
1447 unsigned long smallest_size, smallest_mask;
1448 unsigned long s;
1449
1450 smallest_size = (1UL << kpte_shift_min);
1451 smallest_mask = (smallest_size - 1UL);
1452
1453 while (start < end) {
1454 unsigned long orig_start = start;
1455
1456 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1457 start = kpte_mark_using_shift(start, end, s);
1458
1459 if (start != orig_start)
1460 break;
9cc3a1ac 1461 }
4f93d21d
DM		 1462
1463 if (start == orig_start)
1464 start = (start + smallest_size) & ~smallest_mask;
9cc3a1ac
DM		 1465 }
1466}
56425306 1467
8f361453 1468static void __init init_kpte_bitmap(void)
56425306 1469{
9cc3a1ac 1470 unsigned long i;
13edad7a
DM		 1471
1472 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1473 unsigned long phys_start, phys_end;
1474
13edad7a
DM		 1475 phys_start = pall[i].phys_addr;
1476 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1477
1478 mark_kpte_bitmap(phys_start, phys_end);
8f361453
DM		 1479 }
1480}
9cc3a1ac 1481
8f361453
DM		 1482static void __init kernel_physical_mapping_init(void)
1483{
9cc3a1ac 1484#ifdef CONFIG_DEBUG_PAGEALLOC
8f361453
DM		 1485 unsigned long i, mem_alloced = 0UL;
1486
1487 for (i = 0; i < pall_ents; i++) {
1488 unsigned long phys_start, phys_end;
1489
1490 phys_start = pall[i].phys_addr;
1491 phys_end = phys_start + pall[i].reg_size;
1492
56425306
DM		 1493 mem_alloced += kernel_map_range(phys_start, phys_end,
1494 PAGE_KERNEL);
56425306
DM		 1495 }
1496
1497 printk("Allocated %ld bytes for kernel page tables.\n",
1498 mem_alloced);
1499
1500 kvmap_linear_patch[0] = 0x01000000; /* nop */
1501 flushi(&kvmap_linear_patch[0]);
1502
1503 __flush_tlb_all();
9cc3a1ac 1504#endif
56425306
DM		 1505}
1506
9cc3a1ac 1507#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1508void kernel_map_pages(struct page *page, int numpages, int enable)
1509{
1510 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1511 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1512
1513 kernel_map_range(phys_start, phys_end,
1514 (enable ? PAGE_KERNEL : __pgprot(0)));
1515
74bf4312
DM		 1516 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1517 PAGE_OFFSET + phys_end);
1518
56425306
DM		 1519 /* we should perform an IPI and flush all tlbs,
1520 * but that can deadlock->flush only current cpu.
1521 */
1522 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1523 PAGE_OFFSET + phys_end);
1524}
1525#endif
1526
10147570
DM		 1527unsigned long __init find_ecache_flush_span(unsigned long size)
1528{
0836a0eb
DM		 1529 int i;
1530
13edad7a
DM		 1531 for (i = 0; i < pavail_ents; i++) {
1532 if (pavail[i].reg_size >= size)
1533 return pavail[i].phys_addr;
0836a0eb
DM		 1534 }
1535
13edad7a 1536 return ~0UL;
0836a0eb
DM		 1537}
1538
517af332
DM		 1539static void __init tsb_phys_patch(void)
1540{
d257d5da 1541 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1542 struct tsb_phys_patch_entry *p;
1543
d257d5da
DM		 1544 pquad = &__tsb_ldquad_phys_patch;
1545 while (pquad < &__tsb_ldquad_phys_patch_end) {
1546 unsigned long addr = pquad->addr;
1547
1548 if (tlb_type == hypervisor)
1549 *(unsigned int *) addr = pquad->sun4v_insn;
1550 else
1551 *(unsigned int *) addr = pquad->sun4u_insn;
1552 wmb();
1553 __asm__ __volatile__("flush %0"
1554 : /* no outputs */
1555 : "r" (addr));
1556
1557 pquad++;
1558 }
1559
517af332
DM		 1560 p = &__tsb_phys_patch;
1561 while (p < &__tsb_phys_patch_end) {
1562 unsigned long addr = p->addr;
1563
1564 *(unsigned int *) addr = p->insn;
1565 wmb();
1566 __asm__ __volatile__("flush %0"
1567 : /* no outputs */
1568 : "r" (addr));
1569
1570 p++;
1571 }
1572}
1573
490384e7 1574/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1575#ifndef CONFIG_DEBUG_PAGEALLOC
1576#define NUM_KTSB_DESCR 2
1577#else
1578#define NUM_KTSB_DESCR 1
1579#endif
1580static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1581extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1582
9076d0e7
DM		 1583static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1584{
1585 pa >>= KTSB_PHYS_SHIFT;
1586
1587 while (start < end) {
1588 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1589
1590 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1591 __asm__ __volatile__("flush %0" : : "r" (ia));
1592
1593 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1594 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1595
1596 start++;
1597 }
1598}
1599
1600static void ktsb_phys_patch(void)
1601{
1602 extern unsigned int __swapper_tsb_phys_patch;
1603 extern unsigned int __swapper_tsb_phys_patch_end;
9076d0e7
DM		 1604 unsigned long ktsb_pa;
1605
1606 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1607 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1608 &__swapper_tsb_phys_patch_end, ktsb_pa);
1609#ifndef CONFIG_DEBUG_PAGEALLOC
0785a8e8
DM		 1610 {
1611 extern unsigned int __swapper_4m_tsb_phys_patch;
1612 extern unsigned int __swapper_4m_tsb_phys_patch_end;
9076d0e7
DM		 1613 ktsb_pa = (kern_base +
1614 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1615 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1616 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
0785a8e8 1617 }
9076d0e7
DM		 1618#endif
1619}
1620
490384e7
DM		 1621static void __init sun4v_ktsb_init(void)
1622{
1623 unsigned long ktsb_pa;
1624
d7744a09 1625 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1626 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1627
1628 switch (PAGE_SIZE) {
1629 case 8 * 1024:
1630 default:
1631 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1632 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1633 break;
1634
1635 case 64 * 1024:
1636 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1637 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1638 break;
1639
1640 case 512 * 1024:
1641 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1642 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1643 break;
1644
1645 case 4 * 1024 * 1024:
1646 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1647 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1648 break;
6cb79b3f 1649 }
490384e7 1650
3f19a84e 1651 ktsb_descr[0].assoc = 1;
490384e7
DM		 1652 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1653 ktsb_descr[0].ctx_idx = 0;
1654 ktsb_descr[0].tsb_base = ktsb_pa;
1655 ktsb_descr[0].resv = 0;
1656
d1acb421 1657#ifndef CONFIG_DEBUG_PAGEALLOC
4f93d21d 1658 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
d7744a09
DM		 1659 ktsb_pa = (kern_base +
1660 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1661
1662 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
c69ad0a3
DM		 1663 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1664 HV_PGSZ_MASK_256MB |
1665 HV_PGSZ_MASK_2GB |
1666 HV_PGSZ_MASK_16GB) &
1667 cpu_pgsz_mask);
d7744a09
DM		 1668 ktsb_descr[1].assoc = 1;
1669 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1670 ktsb_descr[1].ctx_idx = 0;
1671 ktsb_descr[1].tsb_base = ktsb_pa;
1672 ktsb_descr[1].resv = 0;
d1acb421 1673#endif
490384e7
DM		 1674}
1675
1676void __cpuinit sun4v_ktsb_register(void)
1677{
7db35f31 1678 unsigned long pa, ret;
490384e7
DM		 1679
1680 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1681
7db35f31
DM		 1682 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1683 if (ret != 0) {
1684 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1685 "errors with %lx\n", pa, ret);
1686 prom_halt();
1687 }
490384e7
DM		 1688}
1689
c69ad0a3
DM		 1690static void __init sun4u_linear_pte_xor_finalize(void)
1691{
1692#ifndef CONFIG_DEBUG_PAGEALLOC
1693 /* This is where we would add Panther support for
1694 * 32MB and 256MB pages.
1695 */
1696#endif
1697}
1698
1699static void __init sun4v_linear_pte_xor_finalize(void)
1700{
1701#ifndef CONFIG_DEBUG_PAGEALLOC
1702 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1703 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1704 0xfffff80000000000UL;
1705 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1706 _PAGE_P_4V | _PAGE_W_4V);
1707 } else {
1708 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1709 }
1710
1711 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1712 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1713 0xfffff80000000000UL;
1714 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1715 _PAGE_P_4V | _PAGE_W_4V);
1716 } else {
1717 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1718 }
1719
1720 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1721 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1722 0xfffff80000000000UL;
1723 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1724 _PAGE_P_4V | _PAGE_W_4V);
1725 } else {
1726 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1727 }
1728#endif
1729}
1730
1da177e4
LT		 1731/* paging_init() sets up the page tables */
1732
1da177e4 1733static unsigned long last_valid_pfn;
56425306 1734pgd_t swapper_pg_dir[2048];
1da177e4 1735
c4bce90e
DM		 1736static void sun4u_pgprot_init(void);
1737static void sun4v_pgprot_init(void);
1738
1da177e4
LT		 1739void __init paging_init(void)
1740{
919ee677 1741 unsigned long end_pfn, shift, phys_base;
0836a0eb 1742 unsigned long real_end, i;
aa6f0790 1743 int node;
0836a0eb 1744
22adb358
DM		 1745 /* These build time checkes make sure that the dcache_dirty_cpu()
1746 * page->flags usage will work.
1747 *
1748 * When a page gets marked as dcache-dirty, we store the
1749 * cpu number starting at bit 32 in the page->flags. Also,
1750 * functions like clear_dcache_dirty_cpu use the cpu mask
1751 * in 13-bit signed-immediate instruction fields.
1752 */
9223b419
CL		 1753
1754 /*
1755 * Page flags must not reach into upper 32 bits that are used
1756 * for the cpu number
1757 */
1758 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1759
1760 /*
1761 * The bit fields placed in the high range must not reach below
1762 * the 32 bit boundary. Otherwise we cannot place the cpu field
1763 * at the 32 bit boundary.
1764 */
22adb358 1765 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
9223b419
CL		 1766 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1767
22adb358
DM		 1768 BUILD_BUG_ON(NR_CPUS > 4096);
1769
481295f9
DM		 1770 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1771 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1772
d7744a09 1773 /* Invalidate both kernel TSBs. */
8b234274 1774 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1775#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1776 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1777#endif
8b234274 1778
c4bce90e
DM		 1779 if (tlb_type == hypervisor)
1780 sun4v_pgprot_init();
1781 else
1782 sun4u_pgprot_init();
1783
d257d5da 1784 if (tlb_type == cheetah_plus ||
9076d0e7 1785 tlb_type == hypervisor) {
517af332 1786 tsb_phys_patch();
9076d0e7
DM		 1787 ktsb_phys_patch();
1788 }
517af332 1789
c69ad0a3 1790 if (tlb_type == hypervisor)
d257d5da
DM		 1791 sun4v_patch_tlb_handlers();
1792
a94a172d
DM		 1793 /* Find available physical memory...
1794 *
1795 * Read it twice in order to work around a bug in openfirmware.
1796 * The call to grab this table itself can cause openfirmware to
1797 * allocate memory, which in turn can take away some space from
1798 * the list of available memory. Reading it twice makes sure
1799 * we really do get the final value.
1800 */
1801 read_obp_translations();
1802 read_obp_memory("reg", &pall[0], &pall_ents);
1803 read_obp_memory("available", &pavail[0], &pavail_ents);
13edad7a 1804 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1805
1806 phys_base = 0xffffffffffffffffUL;
3b2a7e23 1807 for (i = 0; i < pavail_ents; i++) {
13edad7a 1808 phys_base = min(phys_base, pavail[i].phys_addr);
95f72d1e 1809 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
3b2a7e23
DM		 1810 }
1811
95f72d1e 1812 memblock_reserve(kern_base, kern_size);
0836a0eb 1813
4e82c9a6
DM		 1814 find_ramdisk(phys_base);
1815
95f72d1e 1816 memblock_enforce_memory_limit(cmdline_memory_size);
25b0c659 1817
1aadc056 1818 memblock_allow_resize();
95f72d1e 1819 memblock_dump_all();
3b2a7e23 1820
1da177e4
LT		 1821 set_bit(0, mmu_context_bmap);
1822
2bdb3cb2
DM		 1823 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1824
1da177e4 1825 real_end = (unsigned long)_end;
64658743
DM		 1826 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1827 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1828 num_kernel_image_mappings);
2bdb3cb2
DM		 1829
1830 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1831 * work.
1832 */
1833 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1834
56425306 1835 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1836
1837 /* Now can init the kernel/bad page tables. */
1838 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1839 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1840
c9c10830 1841 inherit_prom_mappings();
5085b4a5 1842
8f361453
DM		 1843 init_kpte_bitmap();
1844
a8b900d8
DM		 1845 /* Ok, we can use our TLB miss and window trap handlers safely. */
1846 setup_tba();
1da177e4 1847
c9c10830 1848 __flush_tlb_all();
9ad98c5b 1849
ad072004 1850 prom_build_devicetree();
b696fdc2 1851 of_populate_present_mask();
b99c6ebe
DM		 1852#ifndef CONFIG_SMP
1853 of_fill_in_cpu_data();
1854#endif
ad072004 1855
890db403 1856 if (tlb_type == hypervisor) {
4a283339 1857 sun4v_mdesc_init();
6ac5c610 1858 mdesc_populate_present_mask(cpu_all_mask);
b99c6ebe
DM		 1859#ifndef CONFIG_SMP
1860 mdesc_fill_in_cpu_data(cpu_all_mask);
1861#endif
ce33fdc5 1862 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
c69ad0a3
DM		 1863
1864 sun4v_linear_pte_xor_finalize();
1865
1866 sun4v_ktsb_init();
1867 sun4v_ktsb_register();
ce33fdc5
DM		 1868 } else {
1869 unsigned long impl, ver;
1870
1871 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1872 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1873
1874 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1875 impl = ((ver >> 32) & 0xffff);
1876 if (impl == PANTHER_IMPL)
1877 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1878 HV_PGSZ_MASK_256MB);
c69ad0a3
DM		 1879
1880 sun4u_linear_pte_xor_finalize();
890db403 1881 }
4a283339 1882
c69ad0a3
DM		 1883 /* Flush the TLBs and the 4M TSB so that the updated linear
1884 * pte XOR settings are realized for all mappings.
1885 */
1886 __flush_tlb_all();
1887#ifndef CONFIG_DEBUG_PAGEALLOC
1888 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1889#endif
1890 __flush_tlb_all();
1891
5ed56f1a
DM		 1892 /* Setup bootmem... */
1893 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1894
4f70f7a9
DM		 1895 /* Once the OF device tree and MDESC have been setup, we know
1896 * the list of possible cpus. Therefore we can allocate the
1897 * IRQ stacks.
1898 */
1899 for_each_possible_cpu(i) {
aa6f0790 1900 node = cpu_to_node(i);
5ed56f1a
DM		 1901
1902 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1903 THREAD_SIZE,
1904 THREAD_SIZE, 0);
1905 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1906 THREAD_SIZE,
1907 THREAD_SIZE, 0);
4f70f7a9
DM		 1908 }
1909
56425306 1910 kernel_physical_mapping_init();
56425306 1911
1da177e4 1912 {
919ee677 1913 unsigned long max_zone_pfns[MAX_NR_ZONES];
1da177e4 1914
919ee677 1915 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1da177e4 1916
919ee677 1917 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1da177e4 1918
919ee677 1919 free_area_init_nodes(max_zone_pfns);
1da177e4
LT		 1920 }
1921
3c62a2d3 1922 printk("Booting Linux...\n");
1da177e4
LT		 1923}
1924
9a2ed5cc 1925int __devinit page_in_phys_avail(unsigned long paddr)
919ee677
DM		 1926{
1927 int i;
1928
1929 paddr &= PAGE_MASK;
1930
1931 for (i = 0; i < pavail_ents; i++) {
1932 unsigned long start, end;
1933
1934 start = pavail[i].phys_addr;
1935 end = start + pavail[i].reg_size;
1936
1937 if (paddr >= start && paddr < end)
1938 return 1;
1939 }
1940 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1941 return 1;
1942#ifdef CONFIG_BLK_DEV_INITRD
1943 if (paddr >= __pa(initrd_start) &&
1944 paddr < __pa(PAGE_ALIGN(initrd_end)))
1945 return 1;
1946#endif
1947
1948 return 0;
1949}
1950
1951static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1952static int pavail_rescan_ents __initdata;
1953
1954/* Certain OBP calls, such as fetching "available" properties, can
1955 * claim physical memory. So, along with initializing the valid
1956 * address bitmap, what we do here is refetch the physical available
1957 * memory list again, and make sure it provides at least as much
1958 * memory as 'pavail' does.
1959 */
d8ed1d43 1960static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1da177e4 1961{
1da177e4
LT		 1962 int i;
1963
13edad7a 1964 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1965
13edad7a 1966 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1967 unsigned long old_start, old_end;
1968
13edad7a 1969 old_start = pavail[i].phys_addr;
919ee677 1970 old_end = old_start + pavail[i].reg_size;
1da177e4
LT		 1971 while (old_start < old_end) {
1972 int n;
1973
c2a5a46b 1974 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1975 unsigned long new_start, new_end;
1976
13edad7a
DM		 1977 new_start = pavail_rescan[n].phys_addr;
1978 new_end = new_start +
1979 pavail_rescan[n].reg_size;
1da177e4
LT		 1980
1981 if (new_start <= old_start &&
1982 new_end >= (old_start + PAGE_SIZE)) {
d8ed1d43 1983 set_bit(old_start >> 22, bitmap);
1da177e4
LT		 1984 goto do_next_page;
1985 }
1986 }
919ee677
DM		 1987
1988 prom_printf("mem_init: Lost memory in pavail\n");
1989 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1990 pavail[i].phys_addr,
1991 pavail[i].reg_size);
1992 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1993 pavail_rescan[i].phys_addr,
1994 pavail_rescan[i].reg_size);
1995 prom_printf("mem_init: Cannot continue, aborting.\n");
1996 prom_halt();
1da177e4
LT		 1997
1998 do_next_page:
1999 old_start += PAGE_SIZE;
2000 }
2001 }
2002}
2003
d8ed1d43
DM		 2004static void __init patch_tlb_miss_handler_bitmap(void)
2005{
2006 extern unsigned int valid_addr_bitmap_insn[];
2007 extern unsigned int valid_addr_bitmap_patch[];
2008
2009 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2010 mb();
2011 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2012 flushi(&valid_addr_bitmap_insn[0]);
2013}
2014
1da177e4
LT		 2015void __init mem_init(void)
2016{
2017 unsigned long codepages, datapages, initpages;
2018 unsigned long addr, last;
1da177e4
LT		 2019
2020 addr = PAGE_OFFSET + kern_base;
2021 last = PAGE_ALIGN(kern_size) + addr;
2022 while (addr < last) {
2023 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2024 addr += PAGE_SIZE;
2025 }
2026
d8ed1d43
DM		 2027 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2028 patch_tlb_miss_handler_bitmap();
1da177e4 2029
1da177e4
LT		 2030 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2031
919ee677 2032#ifdef CONFIG_NEED_MULTIPLE_NODES
d8ed1d43
DM		 2033 {
2034 int i;
2035 for_each_online_node(i) {
2036 if (NODE_DATA(i)->node_spanned_pages != 0) {
2037 totalram_pages +=
2038 free_all_bootmem_node(NODE_DATA(i));
2039 }
919ee677 2040 }
625d693e 2041 totalram_pages += free_low_memory_core_early(MAX_NUMNODES);
919ee677
DM		 2042 }
2043#else
2044 totalram_pages = free_all_bootmem();
2045#endif
2046
f1cfdb55
DM		 2047 /* We subtract one to account for the mem_map_zero page
2048 * allocated below.
2049 */
919ee677
DM		 2050 totalram_pages -= 1;
2051 num_physpages = totalram_pages;
1da177e4
LT		 2052
2053 /*
2054 * Set up the zero page, mark it reserved, so that page count
2055 * is not manipulated when freeing the page from user ptes.
2056 */
2057 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2058 if (mem_map_zero == NULL) {
2059 prom_printf("paging_init: Cannot alloc zero page.\n");
2060 prom_halt();
2061 }
2062 SetPageReserved(mem_map_zero);
2063
2064 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
2065 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
2066 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
2067 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
2068 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
2069 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
2070
96177299 2071 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 2072 nr_free_pages() << (PAGE_SHIFT-10),
2073 codepages << (PAGE_SHIFT-10),
2074 datapages << (PAGE_SHIFT-10),
2075 initpages << (PAGE_SHIFT-10),
2076 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2077
2078 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2079 cheetah_ecache_flush_init();
2080}
2081
898cf0ec 2082void free_initmem(void)
1da177e4
LT		 2083{
2084 unsigned long addr, initend;
f2b60794
DM		 2085 int do_free = 1;
2086
2087 /* If the physical memory maps were trimmed by kernel command
2088 * line options, don't even try freeing this initmem stuff up.
2089 * The kernel image could have been in the trimmed out region
2090 * and if so the freeing below will free invalid page structs.
2091 */
2092 if (cmdline_memory_size)
2093 do_free = 0;
1da177e4
LT		 2094
2095 /*
2096 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2097 */
2098 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2099 initend = (unsigned long)(__init_end) & PAGE_MASK;
2100 for (; addr < initend; addr += PAGE_SIZE) {
2101 unsigned long page;
2102 struct page *p;
2103
2104 page = (addr +
2105 ((unsigned long) __va(kern_base)) -
2106 ((unsigned long) KERNBASE));
c9cf5528 2107 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4 2108
f2b60794
DM		 2109 if (do_free) {
2110 p = virt_to_page(page);
2111
2112 ClearPageReserved(p);
2113 init_page_count(p);
2114 __free_page(p);
2115 num_physpages++;
2116 totalram_pages++;
2117 }
1da177e4
LT		 2118 }
2119}
2120
2121#ifdef CONFIG_BLK_DEV_INITRD
2122void free_initrd_mem(unsigned long start, unsigned long end)
2123{
2124 if (start < end)
2125 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2126 for (; start < end; start += PAGE_SIZE) {
2127 struct page *p = virt_to_page(start);
2128
2129 ClearPageReserved(p);
7835e98b 2130 init_page_count(p);
1da177e4
LT		 2131 __free_page(p);
2132 num_physpages++;
2133 totalram_pages++;
2134 }
2135}
2136#endif
c4bce90e 2137
c4bce90e
DM		 2138#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2139#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2140#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2141#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2142#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2143#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2144
2145pgprot_t PAGE_KERNEL __read_mostly;
2146EXPORT_SYMBOL(PAGE_KERNEL);
2147
2148pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2149pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 2150
2151pgprot_t PAGE_SHARED __read_mostly;
2152EXPORT_SYMBOL(PAGE_SHARED);
2153
c4bce90e
DM		 2154unsigned long pg_iobits __read_mostly;
2155
2156unsigned long _PAGE_IE __read_mostly;
987c74fc 2157EXPORT_SYMBOL(_PAGE_IE);
b2bef442 2158
c4bce90e 2159unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 2160EXPORT_SYMBOL(_PAGE_E);
2161
c4bce90e 2162unsigned long _PAGE_CACHE __read_mostly;
b2bef442 2163EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 2164
46644c24 2165#ifdef CONFIG_SPARSEMEM_VMEMMAP
46644c24
DM		 2166unsigned long vmemmap_table[VMEMMAP_SIZE];
2167
2856cc2e
DM		 2168static long __meminitdata addr_start, addr_end;
2169static int __meminitdata node_start;
2170
46644c24
DM		 2171int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2172{
2173 unsigned long vstart = (unsigned long) start;
2174 unsigned long vend = (unsigned long) (start + nr);
2175 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2176 unsigned long phys_end = (vend - VMEMMAP_BASE);
2177 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2178 unsigned long end = VMEMMAP_ALIGN(phys_end);
2179 unsigned long pte_base;
2180
2181 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2182 _PAGE_CP_4U | _PAGE_CV_4U |
2183 _PAGE_P_4U | _PAGE_W_4U);
2184 if (tlb_type == hypervisor)
2185 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2186 _PAGE_CP_4V | _PAGE_CV_4V |
2187 _PAGE_P_4V | _PAGE_W_4V);
2188
2189 for (; addr < end; addr += VMEMMAP_CHUNK) {
2190 unsigned long *vmem_pp =
2191 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2192 void *block;
2193
2194 if (!(*vmem_pp & _PAGE_VALID)) {
2195 block = vmemmap_alloc_block(1UL << 22, node);
2196 if (!block)
2197 return -ENOMEM;
2198
2199 *vmem_pp = pte_base | __pa(block);
2200
2856cc2e
DM		 2201 /* check to see if we have contiguous blocks */
2202 if (addr_end != addr || node_start != node) {
2203 if (addr_start)
2204 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2205 addr_start, addr_end-1, node_start);
2206 addr_start = addr;
2207 node_start = node;
2208 }
2209 addr_end = addr + VMEMMAP_CHUNK;
46644c24
DM		 2210 }
2211 }
2212 return 0;
2213}
2856cc2e
DM		 2214
2215void __meminit vmemmap_populate_print_last(void)
2216{
2217 if (addr_start) {
2218 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2219 addr_start, addr_end-1, node_start);
2220 addr_start = 0;
2221 addr_end = 0;
2222 node_start = 0;
2223 }
2224}
46644c24
DM		 2225#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2226
c4bce90e
DM		 2227static void prot_init_common(unsigned long page_none,
2228 unsigned long page_shared,
2229 unsigned long page_copy,
2230 unsigned long page_readonly,
2231 unsigned long page_exec_bit)
2232{
2233 PAGE_COPY = __pgprot(page_copy);
0f15952a 2234 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 2235
2236 protection_map[0x0] = __pgprot(page_none);
2237 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2238 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2239 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2240 protection_map[0x4] = __pgprot(page_readonly);
2241 protection_map[0x5] = __pgprot(page_readonly);
2242 protection_map[0x6] = __pgprot(page_copy);
2243 protection_map[0x7] = __pgprot(page_copy);
2244 protection_map[0x8] = __pgprot(page_none);
2245 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2246 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2247 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2248 protection_map[0xc] = __pgprot(page_readonly);
2249 protection_map[0xd] = __pgprot(page_readonly);
2250 protection_map[0xe] = __pgprot(page_shared);
2251 protection_map[0xf] = __pgprot(page_shared);
2252}
2253
2254static void __init sun4u_pgprot_init(void)
2255{
2256 unsigned long page_none, page_shared, page_copy, page_readonly;
2257 unsigned long page_exec_bit;
4f93d21d 2258 int i;
c4bce90e
DM		 2259
2260 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2261 _PAGE_CACHE_4U | _PAGE_P_4U |
2262 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2263 _PAGE_EXEC_4U);
2264 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2265 _PAGE_CACHE_4U | _PAGE_P_4U |
2266 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2267 _PAGE_EXEC_4U | _PAGE_L_4U);
c4bce90e
DM		 2268
2269 _PAGE_IE = _PAGE_IE_4U;
2270 _PAGE_E = _PAGE_E_4U;
2271 _PAGE_CACHE = _PAGE_CACHE_4U;
2272
2273 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2274 __ACCESS_BITS_4U | _PAGE_E_4U);
2275
d1acb421 2276#ifdef CONFIG_DEBUG_PAGEALLOC
15b9350a 2277 kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
d1acb421 2278#else
9cc3a1ac 2279 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
af1ee569 2280 0xfffff80000000000UL;
d1acb421 2281#endif
9cc3a1ac
DM		 2282 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2283 _PAGE_P_4U | _PAGE_W_4U);
2284
4f93d21d
DM		 2285 for (i = 1; i < 4; i++)
2286 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
c4bce90e 2287
c4bce90e
DM		 2288 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2289 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2290 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2291
2292
2293 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2294 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2295 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2296 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2297 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2298 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2299 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2300
2301 page_exec_bit = _PAGE_EXEC_4U;
2302
2303 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2304 page_exec_bit);
2305}
2306
2307static void __init sun4v_pgprot_init(void)
2308{
2309 unsigned long page_none, page_shared, page_copy, page_readonly;
2310 unsigned long page_exec_bit;
4f93d21d 2311 int i;
c4bce90e
DM		 2312
2313 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2314 _PAGE_CACHE_4V | _PAGE_P_4V |
2315 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2316 _PAGE_EXEC_4V);
2317 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
c4bce90e
DM		 2318
2319 _PAGE_IE = _PAGE_IE_4V;
2320 _PAGE_E = _PAGE_E_4V;
2321 _PAGE_CACHE = _PAGE_CACHE_4V;
2322
d1acb421 2323#ifdef CONFIG_DEBUG_PAGEALLOC
15b9350a 2324 kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
d1acb421 2325#else
9cc3a1ac 2326 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
af1ee569 2327 0xfffff80000000000UL;
d1acb421 2328#endif
9cc3a1ac
DM		 2329 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2330 _PAGE_P_4V | _PAGE_W_4V);
2331
c69ad0a3
DM		 2332 for (i = 1; i < 4; i++)
2333 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
4f93d21d 2334
c4bce90e
DM		 2335 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2336 __ACCESS_BITS_4V | _PAGE_E_4V);
2337
c4bce90e
DM		 2338 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2339 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2340 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2341 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2342
2343 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2344 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2345 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2346 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2347 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2348 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2349 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2350
2351 page_exec_bit = _PAGE_EXEC_4V;
2352
2353 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2354 page_exec_bit);
2355}
2356
2357unsigned long pte_sz_bits(unsigned long sz)
2358{
2359 if (tlb_type == hypervisor) {
2360 switch (sz) {
2361 case 8 * 1024:
2362 default:
2363 return _PAGE_SZ8K_4V;
2364 case 64 * 1024:
2365 return _PAGE_SZ64K_4V;
2366 case 512 * 1024:
2367 return _PAGE_SZ512K_4V;
2368 case 4 * 1024 * 1024:
2369 return _PAGE_SZ4MB_4V;
6cb79b3f 2370 }
c4bce90e
DM		 2371 } else {
2372 switch (sz) {
2373 case 8 * 1024:
2374 default:
2375 return _PAGE_SZ8K_4U;
2376 case 64 * 1024:
2377 return _PAGE_SZ64K_4U;
2378 case 512 * 1024:
2379 return _PAGE_SZ512K_4U;
2380 case 4 * 1024 * 1024:
2381 return _PAGE_SZ4MB_4U;
6cb79b3f 2382 }
c4bce90e
DM		 2383 }
2384}
2385
2386pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2387{
2388 pte_t pte;
cf627156
DM		 2389
2390 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 2391 pte_val(pte) |= (((unsigned long)space) << 32);
2392 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 2393
cf627156 2394 return pte;
c4bce90e
DM		 2395}
2396
2397static unsigned long kern_large_tte(unsigned long paddr)
2398{
2399 unsigned long val;
2400
2401 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2402 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2403 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2404 if (tlb_type == hypervisor)
2405 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2406 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2407 _PAGE_EXEC_4V | _PAGE_W_4V);
2408
2409 return val | paddr;
2410}
2411
c4bce90e
DM		 2412/* If not locked, zap it. */
2413void __flush_tlb_all(void)
2414{
2415 unsigned long pstate;
2416 int i;
2417
2418 __asm__ __volatile__("flushw\n\t"
2419 "rdpr %%pstate, %0\n\t"
2420 "wrpr %0, %1, %%pstate"
2421 : "=r" (pstate)
2422 : "i" (PSTATE_IE));
8f361453
DM		 2423 if (tlb_type == hypervisor) {
2424 sun4v_mmu_demap_all();
2425 } else if (tlb_type == spitfire) {
c4bce90e
DM		 2426 for (i = 0; i < 64; i++) {
2427 /* Spitfire Errata #32 workaround */
2428 /* NOTE: Always runs on spitfire, so no
2429 * cheetah+ page size encodings.
2430 */
2431 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2432 "flush %%g6"
2433 : /* No outputs */
2434 : "r" (0),
2435 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2436
2437 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2438 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2439 "membar #Sync"
2440 : /* no outputs */
2441 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2442 spitfire_put_dtlb_data(i, 0x0UL);
2443 }
2444
2445 /* Spitfire Errata #32 workaround */
2446 /* NOTE: Always runs on spitfire, so no
2447 * cheetah+ page size encodings.
2448 */
2449 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2450 "flush %%g6"
2451 : /* No outputs */
2452 : "r" (0),
2453 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2454
2455 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2456 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2457 "membar #Sync"
2458 : /* no outputs */
2459 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2460 spitfire_put_itlb_data(i, 0x0UL);
2461 }
2462 }
2463 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2464 cheetah_flush_dtlb_all();
2465 cheetah_flush_itlb_all();
2466 }
2467 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2468 : : "r" (pstate));
2469}
c460bec7
DM		 2470
2471static pte_t *get_from_cache(struct mm_struct *mm)
2472{
2473 struct page *page;
2474 pte_t *ret;
2475
2476 spin_lock(&mm->page_table_lock);
2477 page = mm->context.pgtable_page;
2478 ret = NULL;
2479 if (page) {
2480 void *p = page_address(page);
2481
2482 mm->context.pgtable_page = NULL;
2483
2484 ret = (pte_t *) (p + (PAGE_SIZE / 2));
2485 }
2486 spin_unlock(&mm->page_table_lock);
2487
2488 return ret;
2489}
2490
2491static struct page *__alloc_for_cache(struct mm_struct *mm)
2492{
2493 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2494 __GFP_REPEAT | __GFP_ZERO);
2495
2496 if (page) {
2497 spin_lock(&mm->page_table_lock);
2498 if (!mm->context.pgtable_page) {
2499 atomic_set(&page->_count, 2);
2500 mm->context.pgtable_page = page;
2501 }
2502 spin_unlock(&mm->page_table_lock);
2503 }
2504 return page;
2505}
2506
2507pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2508 unsigned long address)
2509{
2510 struct page *page;
2511 pte_t *pte;
2512
2513 pte = get_from_cache(mm);
2514 if (pte)
2515 return pte;
2516
2517 page = __alloc_for_cache(mm);
2518 if (page)
2519 pte = (pte_t *) page_address(page);
2520
2521 return pte;
2522}
2523
2524pgtable_t pte_alloc_one(struct mm_struct *mm,
2525 unsigned long address)
2526{
2527 struct page *page;
2528 pte_t *pte;
2529
2530 pte = get_from_cache(mm);
2531 if (pte)
2532 return pte;
2533
2534 page = __alloc_for_cache(mm);
2535 if (page) {
2536 pgtable_page_ctor(page);
2537 pte = (pte_t *) page_address(page);
2538 }
2539
2540 return pte;
2541}
2542
2543void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2544{
2545 struct page *page = virt_to_page(pte);
2546 if (put_page_testzero(page))
2547 free_hot_cold_page(page, 0);
2548}
2549
2550static void __pte_free(pgtable_t pte)
2551{
2552 struct page *page = virt_to_page(pte);
2553 if (put_page_testzero(page)) {
2554 pgtable_page_dtor(page);
2555 free_hot_cold_page(page, 0);
2556 }
2557}
2558
2559void pte_free(struct mm_struct *mm, pgtable_t pte)
2560{
2561 __pte_free(pte);
2562}
2563
2564void pgtable_free(void *table, bool is_page)
2565{
2566 if (is_page)
2567 __pte_free(table);
2568 else
2569 kmem_cache_free(pgtable_cache, table);
2570}
Linux kernel - Deliverables
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