sparc64 mm: Fix base TSB sizing when hugetlb pages are used
[deliverable/linux.git] / arch / sparc / mm / tsb.c
CommitLineData
74bf4312
DM
1/* arch/sparc64/mm/tsb.c
2 *
a3cf5e6b 3 * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
74bf4312
DM
4 */
5
6#include <linux/kernel.h>
a3cf5e6b 7#include <linux/preempt.h>
5a0e3ad6 8#include <linux/slab.h>
74bf4312 9#include <asm/page.h>
98c5584c 10#include <asm/pgtable.h>
f36391d2 11#include <asm/mmu_context.h>
8c7260c0 12#include <asm/setup.h>
bd40791e 13#include <asm/tsb.h>
f36391d2 14#include <asm/tlb.h>
9b4006dc 15#include <asm/oplib.h>
74bf4312 16
74bf4312
DM
17extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
18
dcc1e8dd 19static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long hash_shift, unsigned long nentries)
74bf4312 20{
dcc1e8dd 21 vaddr >>= hash_shift;
98c5584c 22 return vaddr & (nentries - 1);
74bf4312
DM
23}
24
8b234274 25static inline int tag_compare(unsigned long tag, unsigned long vaddr)
74bf4312 26{
8b234274 27 return (tag == (vaddr >> 22));
74bf4312
DM
28}
29
30/* TSB flushes need only occur on the processor initiating the address
31 * space modification, not on each cpu the address space has run on.
32 * Only the TLB flush needs that treatment.
33 */
34
35void flush_tsb_kernel_range(unsigned long start, unsigned long end)
36{
37 unsigned long v;
38
39 for (v = start; v < end; v += PAGE_SIZE) {
dcc1e8dd
DM
40 unsigned long hash = tsb_hash(v, PAGE_SHIFT,
41 KERNEL_TSB_NENTRIES);
98c5584c 42 struct tsb *ent = &swapper_tsb[hash];
74bf4312 43
293666b7 44 if (tag_compare(ent->tag, v))
8b234274 45 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
74bf4312
DM
46 }
47}
48
f36391d2
DM
49static void __flush_tsb_one_entry(unsigned long tsb, unsigned long v,
50 unsigned long hash_shift,
51 unsigned long nentries)
74bf4312 52{
f36391d2 53 unsigned long tag, ent, hash;
7a1ac526 54
f36391d2
DM
55 v &= ~0x1UL;
56 hash = tsb_hash(v, hash_shift, nentries);
57 ent = tsb + (hash * sizeof(struct tsb));
58 tag = (v >> 22UL);
74bf4312 59
f36391d2
DM
60 tsb_flush(ent, tag);
61}
74bf4312 62
f36391d2
DM
63static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift,
64 unsigned long tsb, unsigned long nentries)
65{
66 unsigned long i;
517af332 67
f36391d2
DM
68 for (i = 0; i < tb->tlb_nr; i++)
69 __flush_tsb_one_entry(tsb, tb->vaddrs[i], hash_shift, nentries);
dcc1e8dd
DM
70}
71
90f08e39 72void flush_tsb_user(struct tlb_batch *tb)
dcc1e8dd 73{
90f08e39 74 struct mm_struct *mm = tb->mm;
dcc1e8dd
DM
75 unsigned long nentries, base, flags;
76
77 spin_lock_irqsave(&mm->context.lock, flags);
7a1ac526 78
24e49ee3
NG
79 if (!tb->huge) {
80 base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb;
81 nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries;
82 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
83 base = __pa(base);
84 __flush_tsb_one(tb, PAGE_SHIFT, base, nentries);
85 }
9e695d2e 86#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
24e49ee3 87 if (tb->huge && mm->context.tsb_block[MM_TSB_HUGE].tsb) {
dcc1e8dd
DM
88 base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb;
89 nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries;
90 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
91 base = __pa(base);
37b3a8ff 92 __flush_tsb_one(tb, REAL_HPAGE_SHIFT, base, nentries);
dcc1e8dd
DM
93 }
94#endif
7a1ac526 95 spin_unlock_irqrestore(&mm->context.lock, flags);
74bf4312 96}
09f94287 97
24e49ee3 98void flush_tsb_user_page(struct mm_struct *mm, unsigned long vaddr, bool huge)
f36391d2
DM
99{
100 unsigned long nentries, base, flags;
101
102 spin_lock_irqsave(&mm->context.lock, flags);
103
24e49ee3
NG
104 if (!huge) {
105 base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb;
106 nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries;
107 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
108 base = __pa(base);
109 __flush_tsb_one_entry(base, vaddr, PAGE_SHIFT, nentries);
110 }
f36391d2 111#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
24e49ee3 112 if (huge && mm->context.tsb_block[MM_TSB_HUGE].tsb) {
f36391d2
DM
113 base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb;
114 nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries;
115 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
116 base = __pa(base);
37b3a8ff 117 __flush_tsb_one_entry(base, vaddr, REAL_HPAGE_SHIFT, nentries);
f36391d2
DM
118 }
119#endif
120 spin_unlock_irqrestore(&mm->context.lock, flags);
121}
122
dcc1e8dd
DM
123#define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_8K
124#define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_8K
dcc1e8dd 125
9e695d2e 126#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
dcc1e8dd
DM
127#define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_4MB
128#define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_4MB
dcc1e8dd
DM
129#endif
130
131static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsigned long tsb_bytes)
98c5584c
DM
132{
133 unsigned long tsb_reg, base, tsb_paddr;
134 unsigned long page_sz, tte;
135
dcc1e8dd
DM
136 mm->context.tsb_block[tsb_idx].tsb_nentries =
137 tsb_bytes / sizeof(struct tsb);
98c5584c 138
b18eb2d7
DM
139 switch (tsb_idx) {
140 case MM_TSB_BASE:
141 base = TSBMAP_8K_BASE;
142 break;
143#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
144 case MM_TSB_HUGE:
145 base = TSBMAP_4M_BASE;
146 break;
147#endif
148 default:
149 BUG();
150 }
151
c4bce90e 152 tte = pgprot_val(PAGE_KERNEL_LOCKED);
dcc1e8dd 153 tsb_paddr = __pa(mm->context.tsb_block[tsb_idx].tsb);
517af332 154 BUG_ON(tsb_paddr & (tsb_bytes - 1UL));
98c5584c
DM
155
156 /* Use the smallest page size that can map the whole TSB
157 * in one TLB entry.
158 */
159 switch (tsb_bytes) {
160 case 8192 << 0:
161 tsb_reg = 0x0UL;
162#ifdef DCACHE_ALIASING_POSSIBLE
163 base += (tsb_paddr & 8192);
164#endif
98c5584c
DM
165 page_sz = 8192;
166 break;
167
168 case 8192 << 1:
169 tsb_reg = 0x1UL;
98c5584c
DM
170 page_sz = 64 * 1024;
171 break;
172
173 case 8192 << 2:
174 tsb_reg = 0x2UL;
98c5584c
DM
175 page_sz = 64 * 1024;
176 break;
177
178 case 8192 << 3:
179 tsb_reg = 0x3UL;
98c5584c
DM
180 page_sz = 64 * 1024;
181 break;
182
183 case 8192 << 4:
184 tsb_reg = 0x4UL;
98c5584c
DM
185 page_sz = 512 * 1024;
186 break;
187
188 case 8192 << 5:
189 tsb_reg = 0x5UL;
98c5584c
DM
190 page_sz = 512 * 1024;
191 break;
192
193 case 8192 << 6:
194 tsb_reg = 0x6UL;
98c5584c
DM
195 page_sz = 512 * 1024;
196 break;
197
198 case 8192 << 7:
199 tsb_reg = 0x7UL;
98c5584c
DM
200 page_sz = 4 * 1024 * 1024;
201 break;
bd40791e
DM
202
203 default:
7e5766fa
DM
204 printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n",
205 current->comm, current->pid, tsb_bytes);
206 do_exit(SIGSEGV);
6cb79b3f 207 }
c4bce90e 208 tte |= pte_sz_bits(page_sz);
98c5584c 209
618e9ed9 210 if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
517af332
DM
211 /* Physical mapping, no locked TLB entry for TSB. */
212 tsb_reg |= tsb_paddr;
213
dcc1e8dd
DM
214 mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg;
215 mm->context.tsb_block[tsb_idx].tsb_map_vaddr = 0;
216 mm->context.tsb_block[tsb_idx].tsb_map_pte = 0;
517af332
DM
217 } else {
218 tsb_reg |= base;
219 tsb_reg |= (tsb_paddr & (page_sz - 1UL));
220 tte |= (tsb_paddr & ~(page_sz - 1UL));
221
dcc1e8dd
DM
222 mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg;
223 mm->context.tsb_block[tsb_idx].tsb_map_vaddr = base;
224 mm->context.tsb_block[tsb_idx].tsb_map_pte = tte;
517af332 225 }
98c5584c 226
618e9ed9
DM
227 /* Setup the Hypervisor TSB descriptor. */
228 if (tlb_type == hypervisor) {
dcc1e8dd 229 struct hv_tsb_descr *hp = &mm->context.tsb_descr[tsb_idx];
618e9ed9 230
dcc1e8dd
DM
231 switch (tsb_idx) {
232 case MM_TSB_BASE:
233 hp->pgsz_idx = HV_PGSZ_IDX_BASE;
618e9ed9 234 break;
9e695d2e 235#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
dcc1e8dd
DM
236 case MM_TSB_HUGE:
237 hp->pgsz_idx = HV_PGSZ_IDX_HUGE;
618e9ed9 238 break;
dcc1e8dd
DM
239#endif
240 default:
241 BUG();
6cb79b3f 242 }
618e9ed9
DM
243 hp->assoc = 1;
244 hp->num_ttes = tsb_bytes / 16;
245 hp->ctx_idx = 0;
dcc1e8dd
DM
246 switch (tsb_idx) {
247 case MM_TSB_BASE:
248 hp->pgsz_mask = HV_PGSZ_MASK_BASE;
618e9ed9 249 break;
9e695d2e 250#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
dcc1e8dd
DM
251 case MM_TSB_HUGE:
252 hp->pgsz_mask = HV_PGSZ_MASK_HUGE;
618e9ed9 253 break;
dcc1e8dd
DM
254#endif
255 default:
256 BUG();
6cb79b3f 257 }
618e9ed9
DM
258 hp->tsb_base = tsb_paddr;
259 hp->resv = 0;
260 }
98c5584c
DM
261}
262
4dedbf8d
DM
263struct kmem_cache *pgtable_cache __read_mostly;
264
e18b890b 265static struct kmem_cache *tsb_caches[8] __read_mostly;
9b4006dc
DM
266
267static const char *tsb_cache_names[8] = {
268 "tsb_8KB",
269 "tsb_16KB",
270 "tsb_32KB",
271 "tsb_64KB",
272 "tsb_128KB",
273 "tsb_256KB",
274 "tsb_512KB",
275 "tsb_1MB",
276};
277
3a2cba99 278void __init pgtable_cache_init(void)
9b4006dc
DM
279{
280 unsigned long i;
281
4dedbf8d
DM
282 pgtable_cache = kmem_cache_create("pgtable_cache",
283 PAGE_SIZE, PAGE_SIZE,
284 0,
285 _clear_page);
286 if (!pgtable_cache) {
287 prom_printf("pgtable_cache_init(): Could not create!\n");
288 prom_halt();
289 }
290
151b628f 291 for (i = 0; i < ARRAY_SIZE(tsb_cache_names); i++) {
9b4006dc
DM
292 unsigned long size = 8192 << i;
293 const char *name = tsb_cache_names[i];
294
295 tsb_caches[i] = kmem_cache_create(name,
296 size, size,
20c2df83 297 0, NULL);
9b4006dc
DM
298 if (!tsb_caches[i]) {
299 prom_printf("Could not create %s cache\n", name);
300 prom_halt();
301 }
302 }
303}
304
0871420f
DM
305int sysctl_tsb_ratio = -2;
306
307static unsigned long tsb_size_to_rss_limit(unsigned long new_size)
308{
309 unsigned long num_ents = (new_size / sizeof(struct tsb));
310
311 if (sysctl_tsb_ratio < 0)
312 return num_ents - (num_ents >> -sysctl_tsb_ratio);
313 else
314 return num_ents + (num_ents >> sysctl_tsb_ratio);
315}
316
dcc1e8dd
DM
317/* When the RSS of an address space exceeds tsb_rss_limit for a TSB,
318 * do_sparc64_fault() invokes this routine to try and grow it.
7a1ac526 319 *
bd40791e 320 * When we reach the maximum TSB size supported, we stick ~0UL into
dcc1e8dd 321 * tsb_rss_limit for that TSB so the grow checks in do_sparc64_fault()
bd40791e
DM
322 * will not trigger any longer.
323 *
324 * The TSB can be anywhere from 8K to 1MB in size, in increasing powers
325 * of two. The TSB must be aligned to it's size, so f.e. a 512K TSB
b52439c2
DM
326 * must be 512K aligned. It also must be physically contiguous, so we
327 * cannot use vmalloc().
bd40791e
DM
328 *
329 * The idea here is to grow the TSB when the RSS of the process approaches
330 * the number of entries that the current TSB can hold at once. Currently,
331 * we trigger when the RSS hits 3/4 of the TSB capacity.
332 */
dcc1e8dd 333void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long rss)
bd40791e
DM
334{
335 unsigned long max_tsb_size = 1 * 1024 * 1024;
9b4006dc 336 unsigned long new_size, old_size, flags;
7a1ac526 337 struct tsb *old_tsb, *new_tsb;
9b4006dc
DM
338 unsigned long new_cache_index, old_cache_index;
339 unsigned long new_rss_limit;
b52439c2 340 gfp_t gfp_flags;
bd40791e
DM
341
342 if (max_tsb_size > (PAGE_SIZE << MAX_ORDER))
343 max_tsb_size = (PAGE_SIZE << MAX_ORDER);
344
9b4006dc
DM
345 new_cache_index = 0;
346 for (new_size = 8192; new_size < max_tsb_size; new_size <<= 1UL) {
0871420f
DM
347 new_rss_limit = tsb_size_to_rss_limit(new_size);
348 if (new_rss_limit > rss)
bd40791e 349 break;
9b4006dc 350 new_cache_index++;
bd40791e
DM
351 }
352
9b4006dc 353 if (new_size == max_tsb_size)
b52439c2 354 new_rss_limit = ~0UL;
b52439c2 355
9b4006dc 356retry_tsb_alloc:
b52439c2 357 gfp_flags = GFP_KERNEL;
9b4006dc 358 if (new_size > (PAGE_SIZE * 2))
a55ee1ff 359 gfp_flags |= __GFP_NOWARN | __GFP_NORETRY;
b52439c2 360
1f261ef5
DM
361 new_tsb = kmem_cache_alloc_node(tsb_caches[new_cache_index],
362 gfp_flags, numa_node_id());
9b4006dc 363 if (unlikely(!new_tsb)) {
b52439c2
DM
364 /* Not being able to fork due to a high-order TSB
365 * allocation failure is very bad behavior. Just back
366 * down to a 0-order allocation and force no TSB
367 * growing for this address space.
368 */
dcc1e8dd
DM
369 if (mm->context.tsb_block[tsb_index].tsb == NULL &&
370 new_cache_index > 0) {
9b4006dc
DM
371 new_cache_index = 0;
372 new_size = 8192;
b52439c2 373 new_rss_limit = ~0UL;
9b4006dc 374 goto retry_tsb_alloc;
b52439c2
DM
375 }
376
377 /* If we failed on a TSB grow, we are under serious
378 * memory pressure so don't try to grow any more.
379 */
dcc1e8dd
DM
380 if (mm->context.tsb_block[tsb_index].tsb != NULL)
381 mm->context.tsb_block[tsb_index].tsb_rss_limit = ~0UL;
bd40791e 382 return;
b52439c2 383 }
bd40791e 384
8b234274 385 /* Mark all tags as invalid. */
bb8646d8 386 tsb_init(new_tsb, new_size);
7a1ac526
DM
387
388 /* Ok, we are about to commit the changes. If we are
389 * growing an existing TSB the locking is very tricky,
390 * so WATCH OUT!
391 *
392 * We have to hold mm->context.lock while committing to the
393 * new TSB, this synchronizes us with processors in
394 * flush_tsb_user() and switch_mm() for this address space.
395 *
396 * But even with that lock held, processors run asynchronously
397 * accessing the old TSB via TLB miss handling. This is OK
398 * because those actions are just propagating state from the
399 * Linux page tables into the TSB, page table mappings are not
400 * being changed. If a real fault occurs, the processor will
401 * synchronize with us when it hits flush_tsb_user(), this is
402 * also true for the case where vmscan is modifying the page
403 * tables. The only thing we need to be careful with is to
404 * skip any locked TSB entries during copy_tsb().
405 *
406 * When we finish committing to the new TSB, we have to drop
407 * the lock and ask all other cpus running this address space
408 * to run tsb_context_switch() to see the new TSB table.
409 */
410 spin_lock_irqsave(&mm->context.lock, flags);
411
dcc1e8dd
DM
412 old_tsb = mm->context.tsb_block[tsb_index].tsb;
413 old_cache_index =
414 (mm->context.tsb_block[tsb_index].tsb_reg_val & 0x7UL);
415 old_size = (mm->context.tsb_block[tsb_index].tsb_nentries *
416 sizeof(struct tsb));
7a1ac526 417
9b4006dc 418
7a1ac526
DM
419 /* Handle multiple threads trying to grow the TSB at the same time.
420 * One will get in here first, and bump the size and the RSS limit.
421 * The others will get in here next and hit this check.
422 */
dcc1e8dd
DM
423 if (unlikely(old_tsb &&
424 (rss < mm->context.tsb_block[tsb_index].tsb_rss_limit))) {
7a1ac526
DM
425 spin_unlock_irqrestore(&mm->context.lock, flags);
426
9b4006dc 427 kmem_cache_free(tsb_caches[new_cache_index], new_tsb);
7a1ac526
DM
428 return;
429 }
8b234274 430
dcc1e8dd 431 mm->context.tsb_block[tsb_index].tsb_rss_limit = new_rss_limit;
bd40791e 432
7a1ac526
DM
433 if (old_tsb) {
434 extern void copy_tsb(unsigned long old_tsb_base,
435 unsigned long old_tsb_size,
436 unsigned long new_tsb_base,
437 unsigned long new_tsb_size);
438 unsigned long old_tsb_base = (unsigned long) old_tsb;
439 unsigned long new_tsb_base = (unsigned long) new_tsb;
440
441 if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
442 old_tsb_base = __pa(old_tsb_base);
443 new_tsb_base = __pa(new_tsb_base);
444 }
9b4006dc 445 copy_tsb(old_tsb_base, old_size, new_tsb_base, new_size);
7a1ac526 446 }
bd40791e 447
dcc1e8dd
DM
448 mm->context.tsb_block[tsb_index].tsb = new_tsb;
449 setup_tsb_params(mm, tsb_index, new_size);
bd40791e 450
7a1ac526
DM
451 spin_unlock_irqrestore(&mm->context.lock, flags);
452
bd40791e
DM
453 /* If old_tsb is NULL, we're being invoked for the first time
454 * from init_new_context().
455 */
456 if (old_tsb) {
7a1ac526 457 /* Reload it on the local cpu. */
bd40791e
DM
458 tsb_context_switch(mm);
459
7a1ac526 460 /* Now force other processors to do the same. */
a3cf5e6b 461 preempt_disable();
7a1ac526 462 smp_tsb_sync(mm);
a3cf5e6b 463 preempt_enable();
7a1ac526
DM
464
465 /* Now it is safe to free the old tsb. */
9b4006dc 466 kmem_cache_free(tsb_caches[old_cache_index], old_tsb);
bd40791e
DM
467 }
468}
469
09f94287
DM
470int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
471{
9e695d2e 472#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
af1b1a9b 473 unsigned long total_huge_pte_count;
dcc1e8dd
DM
474#endif
475 unsigned int i;
476
a77754b4 477 spin_lock_init(&mm->context.lock);
09f94287
DM
478
479 mm->context.sparc64_ctx_val = 0UL;
09f94287 480
9e695d2e 481#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
af1b1a9b 482 /* We reset them to zero because the fork() page copying
dcc1e8dd
DM
483 * will re-increment the counters as the parent PTEs are
484 * copied into the child address space.
485 */
af1b1a9b
MK
486 total_huge_pte_count = mm->context.hugetlb_pte_count +
487 mm->context.thp_pte_count;
488 mm->context.hugetlb_pte_count = 0;
489 mm->context.thp_pte_count = 0;
dcc1e8dd
DM
490#endif
491
bd40791e
DM
492 /* copy_mm() copies over the parent's mm_struct before calling
493 * us, so we need to zero out the TSB pointer or else tsb_grow()
494 * will be confused and think there is an older TSB to free up.
495 */
dcc1e8dd
DM
496 for (i = 0; i < MM_NUM_TSBS; i++)
497 mm->context.tsb_block[i].tsb = NULL;
7a1ac526
DM
498
499 /* If this is fork, inherit the parent's TSB size. We would
500 * grow it to that size on the first page fault anyways.
501 */
dcc1e8dd 502 tsb_grow(mm, MM_TSB_BASE, get_mm_rss(mm));
bd40791e 503
9e695d2e 504#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
af1b1a9b
MK
505 if (unlikely(total_huge_pte_count))
506 tsb_grow(mm, MM_TSB_HUGE, total_huge_pte_count);
dcc1e8dd
DM
507#endif
508
509 if (unlikely(!mm->context.tsb_block[MM_TSB_BASE].tsb))
bd40791e 510 return -ENOMEM;
09f94287
DM
511
512 return 0;
513}
514
dcc1e8dd 515static void tsb_destroy_one(struct tsb_config *tp)
09f94287 516{
dcc1e8dd 517 unsigned long cache_index;
bd40791e 518
dcc1e8dd
DM
519 if (!tp->tsb)
520 return;
521 cache_index = tp->tsb_reg_val & 0x7UL;
522 kmem_cache_free(tsb_caches[cache_index], tp->tsb);
523 tp->tsb = NULL;
524 tp->tsb_reg_val = 0UL;
525}
98c5584c 526
dcc1e8dd
DM
527void destroy_context(struct mm_struct *mm)
528{
529 unsigned long flags, i;
530
531 for (i = 0; i < MM_NUM_TSBS; i++)
532 tsb_destroy_one(&mm->context.tsb_block[i]);
09f94287 533
77b838fa 534 spin_lock_irqsave(&ctx_alloc_lock, flags);
09f94287
DM
535
536 if (CTX_VALID(mm->context)) {
537 unsigned long nr = CTX_NRBITS(mm->context);
538 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
539 }
540
77b838fa 541 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
09f94287 542}
This page took 0.760235 seconds and 5 git commands to generate.