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[SPARC64]: Rewrite bootup sequence.
[deliverable/linux.git] / arch / sparc64 / kernel / head.S
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1da177e4
LT		 1/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
2 * head.S: Initial boot code for the Sparc64 port of Linux.
3 *
4 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 */
9
10#include <linux/config.h>
11#include <linux/version.h>
12#include <linux/errno.h>
13#include <asm/thread_info.h>
14#include <asm/asi.h>
15#include <asm/pstate.h>
16#include <asm/ptrace.h>
17#include <asm/spitfire.h>
18#include <asm/page.h>
19#include <asm/pgtable.h>
20#include <asm/errno.h>
21#include <asm/signal.h>
22#include <asm/processor.h>
23#include <asm/lsu.h>
24#include <asm/dcr.h>
25#include <asm/dcu.h>
26#include <asm/head.h>
27#include <asm/ttable.h>
28#include <asm/mmu.h>
29
30/* This section from from _start to sparc64_boot_end should fit into
31 * 0x0000.0000.0040.4000 to 0x0000.0000.0040.8000 and will be sharing space
32 * with bootup_user_stack, which is from 0x0000.0000.0040.4000 to
33 * 0x0000.0000.0040.6000 and empty_bad_page, which is from
34 * 0x0000.0000.0040.6000 to 0x0000.0000.0040.8000.
35 */
36
37 .text
38 .globl start, _start, stext, _stext
39_start:
40start:
41_stext:
42stext:
43bootup_user_stack:
44! 0x0000000000404000
45 b sparc64_boot
46 flushw /* Flush register file. */
47
48/* This stuff has to be in sync with SILO and other potential boot loaders
49 * Fields should be kept upward compatible and whenever any change is made,
50 * HdrS version should be incremented.
51 */
52 .global root_flags, ram_flags, root_dev
53 .global sparc_ramdisk_image, sparc_ramdisk_size
54 .global sparc_ramdisk_image64
55
56 .ascii "HdrS"
57 .word LINUX_VERSION_CODE
58
59 /* History:
60 *
61 * 0x0300 : Supports being located at other than 0x4000
62 * 0x0202 : Supports kernel params string
63 * 0x0201 : Supports reboot_command
64 */
65 .half 0x0301 /* HdrS version */
66
67root_flags:
68 .half 1
69root_dev:
70 .half 0
71ram_flags:
72 .half 0
73sparc_ramdisk_image:
74 .word 0
75sparc_ramdisk_size:
76 .word 0
77 .xword reboot_command
78 .xword bootstr_info
79sparc_ramdisk_image64:
80 .xword 0
81 .word _end
82
bff06d55
DM		 83 /* PROM cif handler code address is in %o4. */
84sparc64_boot:
851: rd %pc, %g7
86 set 1b, %g1
87 cmp %g1, %g7
88 be,pn %xcc, sparc64_boot_after_remap
89 mov %o4, %l7
90
91 /* We need to remap the kernel. Use position independant
92 * code to remap us to KERNBASE.
1da177e4 93 *
bff06d55
DM		 94 * SILO can invoke us with 32-bit address masking enabled,
95 * so make sure that's clear.
1da177e4 96 */
bff06d55
DM		 97 rdpr %pstate, %g1
98 andn %g1, PSTATE_AM, %g1
99 wrpr %g1, 0x0, %pstate
100 ba,a,pt %xcc, 1f
101
102 .globl prom_finddev_name, prom_chosen_path
103 .globl prom_getprop_name, prom_mmu_name
104 .globl prom_callmethod_name, prom_translate_name
105 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
106 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
107 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
108prom_finddev_name:
109 .asciz "finddevice"
110prom_chosen_path:
111 .asciz "/chosen"
112prom_getprop_name:
113 .asciz "getprop"
114prom_mmu_name:
115 .asciz "mmu"
116prom_callmethod_name:
117 .asciz "call-method"
118prom_translate_name:
119 .asciz "translate"
120prom_map_name:
121 .asciz "map"
122prom_unmap_name:
123 .asciz "unmap"
124 .align 4
125prom_mmu_ihandle_cache:
126 .word 0
127prom_boot_mapped_pc:
128 .word 0
129prom_boot_mapping_mode:
130 .word 0
131 .align 8
132prom_boot_mapping_phys_high:
133 .xword 0
134prom_boot_mapping_phys_low:
135 .xword 0
1361:
137 rd %pc, %l0
138 mov (1b - prom_finddev_name), %l1
139 mov (1b - prom_chosen_path), %l2
140 mov (1b - prom_boot_mapped_pc), %l3
141 sub %l0, %l1, %l1
142 sub %l0, %l2, %l2
143 sub %l0, %l3, %l3
144 stw %l0, [%l3]
145 sub %sp, (192 + 128), %sp
146
147 /* chosen_node = prom_finddevice("/chosen") */
148 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
149 mov 1, %l3
150 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
151 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
152 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
153 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
154 call %l7
155 add %sp, (2047 + 128), %o0 ! argument array
156
157 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
158
159 mov (1b - prom_getprop_name), %l1
160 mov (1b - prom_mmu_name), %l2
161 mov (1b - prom_mmu_ihandle_cache), %l5
162 sub %l0, %l1, %l1
163 sub %l0, %l2, %l2
164 sub %l0, %l5, %l5
165
166 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
167 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
168 mov 4, %l3
169 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
170 mov 1, %l3
171 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
172 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
173 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
174 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
175 mov 4, %l3
176 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
177 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
178 call %l7
179 add %sp, (2047 + 128), %o0 ! argument array
180
181 mov (1b - prom_callmethod_name), %l1
182 mov (1b - prom_translate_name), %l2
183 sub %l0, %l1, %l1
184 sub %l0, %l2, %l2
185 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
186
187 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
188 mov 3, %l3
189 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
190 mov 5, %l3
191 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
192 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
193 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
194 srlx %l0, 22, %l3
195 sllx %l3, 22, %l3
196 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
197 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
198 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
199 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
200 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
201 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
202 call %l7
203 add %sp, (2047 + 128), %o0 ! argument array
204
205 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
206 mov (1b - prom_boot_mapping_mode), %l4
207 sub %l0, %l4, %l4
208 stw %l1, [%l4]
209 mov (1b - prom_boot_mapping_phys_high), %l4
210 sub %l0, %l4, %l4
211 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
212 stx %l2, [%l4 + 0x0]
213 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
214 stx %l3, [%l4 + 0x8]
215
216 /* Leave service as-is, "call-method" */
217 mov 7, %l3
218 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
219 mov 1, %l3
220 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 7
221 mov (1b - prom_map_name), %l3
222 sub %l0, %l3, %l3
223 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
224 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
225 mov -1, %l3
226 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
227 sethi %hi(8 * 1024 * 1024), %l3
228 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
229 sethi %hi(KERNBASE), %l3
230 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
231 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
232 mov (1b - prom_boot_mapping_phys_low), %l3
233 sub %l0, %l3, %l3
234 ldx [%l3], %l3
235 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
236 call %l7
237 add %sp, (2047 + 128), %o0 ! argument array
238
239 add %sp, (192 + 128), %sp
240
241sparc64_boot_after_remap:
1da177e4
LT		 242 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
243 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
244 ba,pt %xcc, spitfire_boot
245 nop
246
247cheetah_plus_boot:
248 /* Preserve OBP chosen DCU and DCR register settings. */
249 ba,pt %xcc, cheetah_generic_boot
250 nop
251
252cheetah_boot:
253 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
254 wr %g1, %asr18
255
256 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
257 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
258 sllx %g7, 32, %g7
259 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
260 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
261 membar #Sync
262
263cheetah_generic_boot:
264 mov TSB_EXTENSION_P, %g3
265 stxa %g0, [%g3] ASI_DMMU
266 stxa %g0, [%g3] ASI_IMMU
267 membar #Sync
268
269 mov TSB_EXTENSION_S, %g3
270 stxa %g0, [%g3] ASI_DMMU
271 membar #Sync
272
273 mov TSB_EXTENSION_N, %g3
274 stxa %g0, [%g3] ASI_DMMU
275 stxa %g0, [%g3] ASI_IMMU
276 membar #Sync
277
bff06d55 278 ba,a,pt %xcc, jump_to_sun4u_init
1da177e4
LT		 279
280spitfire_boot:
281 /* Typically PROM has already enabled both MMU's and both on-chip
282 * caches, but we do it here anyway just to be paranoid.
283 */
284 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
285 stxa %g1, [%g0] ASI_LSU_CONTROL
286 membar #Sync
287
bff06d55 288jump_to_sun4u_init:
1da177e4
LT		 289 /*
290 * Make sure we are in privileged mode, have address masking,
291 * using the ordinary globals and have enabled floating
292 * point.
293 *
294 * Again, typically PROM has left %pil at 13 or similar, and
295 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
296 */
297 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
298 wr %g0, 0, %fprs
299
1da177e4
LT		 300 set sun4u_init, %g2
301 jmpl %g2 + %g0, %g0
302 nop
303
304sun4u_init:
305 /* Set ctx 0 */
306 mov PRIMARY_CONTEXT, %g7
307 stxa %g0, [%g7] ASI_DMMU
308 membar #Sync
309
310 mov SECONDARY_CONTEXT, %g7
311 stxa %g0, [%g7] ASI_DMMU
312 membar #Sync
313
1da177e4
LT		 314 BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
315
316 ba,pt %xcc, spitfire_tlb_fixup
317 nop
318
319cheetah_tlb_fixup:
1da177e4
LT		 320 mov 2, %g2 /* Set TLB type to cheetah+. */
321 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
322
323 mov 1, %g2 /* Set TLB type to cheetah. */
324
3251: sethi %hi(tlb_type), %g1
326 stw %g2, [%g1 + %lo(tlb_type)]
327
328 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
329 ba,pt %xcc, 2f
330 nop
331
3321: /* Patch context register writes to support nucleus page
333 * size correctly.
334 */
335 call cheetah_plus_patch_etrap
336 nop
337 call cheetah_plus_patch_rtrap
338 nop
339 call cheetah_plus_patch_fpdis
340 nop
341 call cheetah_plus_patch_winfixup
342 nop
1da177e4
LT		 343
3442: /* Patch copy/page operations to cheetah optimized versions. */
345 call cheetah_patch_copyops
346 nop
dbd2fdf5
DM		 347 call cheetah_patch_copy_page
348 nop
1da177e4
LT		 349 call cheetah_patch_cachetlbops
350 nop
351
352 ba,pt %xcc, tlb_fixup_done
353 nop
354
355spitfire_tlb_fixup:
1da177e4
LT		 356 /* Set TLB type to spitfire. */
357 mov 0, %g2
358 sethi %hi(tlb_type), %g1
359 stw %g2, [%g1 + %lo(tlb_type)]
360
361tlb_fixup_done:
362 sethi %hi(init_thread_union), %g6
363 or %g6, %lo(init_thread_union), %g6
364 ldx [%g6 + TI_TASK], %g4
365 mov %sp, %l6
366 mov %o4, %l7
367
1da177e4
LT		 368 wr %g0, ASI_P, %asi
369 mov 1, %g1
370 sllx %g1, THREAD_SHIFT, %g1
371 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
372 add %g6, %g1, %sp
373 mov 0, %fp
374
375 /* Set per-cpu pointer initially to zero, this makes
376 * the boot-cpu use the in-kernel-image per-cpu areas
377 * before setup_per_cpu_area() is invoked.
378 */
379 clr %g5
380
381 wrpr %g0, 0, %wstate
382 wrpr %g0, 0x0, %tl
383
384 /* Clear the bss */
385 sethi %hi(__bss_start), %o0
386 or %o0, %lo(__bss_start), %o0
387 sethi %hi(_end), %o1
388 or %o1, %lo(_end), %o1
389 call __bzero
390 sub %o1, %o0, %o1
391
392 mov %l6, %o1 ! OpenPROM stack
393 call prom_init
394 mov %l7, %o0 ! OpenPROM cif handler
395
396 /* Off we go.... */
397 call start_kernel
398 nop
399 /* Not reached... */
400
401/* IMPORTANT NOTE: Whenever making changes here, check
402 * trampoline.S as well. -jj */
403 .globl setup_tba
404setup_tba: /* i0 = is_starfire */
405 save %sp, -160, %sp
406
407 rdpr %tba, %g7
408 sethi %hi(prom_tba), %o1
409 or %o1, %lo(prom_tba), %o1
410 stx %g7, [%o1]
411
412 /* Setup "Linux" globals 8-) */
413 rdpr %pstate, %o1
414 mov %g6, %o2
415 wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate
416 sethi %hi(sparc64_ttable_tl0), %g1
417 wrpr %g1, %tba
418 mov %o2, %g6
419
420 /* Set up MMU globals */
421 wrpr %o1, (PSTATE_MG|PSTATE_IE), %pstate
422
423 /* Set fixed globals used by dTLB miss handler. */
424#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
425#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
426
427 mov TSB_REG, %g1
428 stxa %g0, [%g1] ASI_DMMU
429 membar #Sync
430 stxa %g0, [%g1] ASI_IMMU
431 membar #Sync
432 mov TLB_SFSR, %g1
433 sethi %uhi(KERN_HIGHBITS), %g2
434 or %g2, %ulo(KERN_HIGHBITS), %g2
435 sllx %g2, 32, %g2
436 or %g2, KERN_LOWBITS, %g2
437
438 BRANCH_IF_ANY_CHEETAH(g3,g7,cheetah_vpte_base)
439 ba,pt %xcc, spitfire_vpte_base
440 nop
441
442cheetah_vpte_base:
443 sethi %uhi(VPTE_BASE_CHEETAH), %g3
444 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
445 ba,pt %xcc, 2f
446 sllx %g3, 32, %g3
447
448spitfire_vpte_base:
449 sethi %uhi(VPTE_BASE_SPITFIRE), %g3
450 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
451 sllx %g3, 32, %g3
452
4532:
454 clr %g7
455#undef KERN_HIGHBITS
456#undef KERN_LOWBITS
457
458 /* Kill PROM timer */
459 sethi %hi(0x80000000), %o2
460 sllx %o2, 32, %o2
461 wr %o2, 0, %tick_cmpr
462
463 BRANCH_IF_ANY_CHEETAH(o2,o3,1f)
464
465 ba,pt %xcc, 2f
466 nop
467
468 /* Disable STICK_INT interrupts. */
4691:
470 sethi %hi(0x80000000), %o2
471 sllx %o2, 32, %o2
472 wr %o2, %asr25
473
474 /* Ok, we're done setting up all the state our trap mechanims needs,
475 * now get back into normal globals and let the PROM know what is up.
476 */
4772:
478 wrpr %g0, %g0, %wstate
479 wrpr %o1, PSTATE_IE, %pstate
480
481 call init_irqwork_curcpu
482 nop
483
484 call prom_set_trap_table
485 sethi %hi(sparc64_ttable_tl0), %o0
486
487 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
488 ba,pt %xcc, 2f
489 nop
490
4911: /* Start using proper page size encodings in ctx register. */
492 sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3
493 mov PRIMARY_CONTEXT, %g1
494 sllx %g3, 32, %g3
495 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
496 or %g3, %g2, %g3
497 stxa %g3, [%g1] ASI_DMMU
498 membar #Sync
499
5002:
501 rdpr %pstate, %o1
502 or %o1, PSTATE_IE, %o1
503 wrpr %o1, 0, %pstate
504
505 ret
506 restore
507
508/*
509 * The following skips make sure the trap table in ttable.S is aligned
510 * on a 32K boundary as required by the v9 specs for TBA register.
511 */
512sparc64_boot_end:
513 .skip 0x2000 + _start - sparc64_boot_end
514bootup_user_stack_end:
515 .skip 0x2000
516
517#ifdef CONFIG_SBUS
518/* This is just a hack to fool make depend config.h discovering
519 strategy: As the .S files below need config.h, but
520 make depend does not find it for them, we include config.h
521 in head.S */
522#endif
523
524! 0x0000000000408000
525
526#include "ttable.S"
527#include "systbls.S"
528
529 .align 1024
530 .globl swapper_pg_dir
531swapper_pg_dir:
532 .word 0
533
2a7e2990 534#include "ktlb.S"
1da177e4
LT		 535#include "etrap.S"
536#include "rtrap.S"
537#include "winfixup.S"
538#include "entry.S"
539
540 /* This is just anal retentiveness on my part... */
541 .align 16384
542
543 .data
544 .align 8
545 .globl prom_tba, tlb_type
546prom_tba: .xword 0
547tlb_type: .word 0 /* Must NOT end up in BSS */
548 .section ".fixup",#alloc,#execinstr
549 .globl __ret_efault
550__ret_efault:
551 ret
552 restore %g0, -EFAULT, %o0
553
Linux kernel - Deliverables
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