Commit | Line | Data |
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4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
4a907dec | 3 | * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
10 | #include <linux/ptrace.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/signal.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/random.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/proc_fs.h> | |
21 | #include <linux/seq_file.h> | |
b5a37e96 | 22 | #include <linux/bootmem.h> |
e18e2a00 | 23 | #include <linux/irq.h> |
35a17eb6 | 24 | #include <linux/msi.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/irq.h> | |
2e457ef6 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/sbus.h> |
33 | #include <asm/iommu.h> | |
34 | #include <asm/upa.h> | |
35 | #include <asm/oplib.h> | |
25c7581b | 36 | #include <asm/prom.h> |
1da177e4 LT |
37 | #include <asm/timer.h> |
38 | #include <asm/smp.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/cache.h> | |
42 | #include <asm/cpudata.h> | |
63b61452 | 43 | #include <asm/auxio.h> |
92704a1c | 44 | #include <asm/head.h> |
4a907dec | 45 | #include <asm/hypervisor.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
48 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
49 | * delivered. We must translate this into a non-vector IRQ so we can | |
50 | * set the softint on this cpu. | |
51 | * | |
52 | * To make processing these packets efficient and race free we use | |
53 | * an array of irq buckets below. The interrupt vector handler in | |
54 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
55 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
56 | * code uses CAS to get an atomic snapshot of the list and clear it | |
57 | * at the same time. | |
e18e2a00 DM |
58 | * |
59 | * If you make changes to ino_bucket, please update hand coded assembler | |
60 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 61 | */ |
e18e2a00 DM |
62 | struct ino_bucket { |
63 | /* Next handler in per-CPU IRQ worklist. We know that | |
64 | * bucket pointers have the high 32-bits clear, so to | |
65 | * save space we only store the bits we need. | |
66 | */ | |
67 | /*0x00*/unsigned int irq_chain; | |
1da177e4 | 68 | |
e18e2a00 DM |
69 | /* Virtual interrupt number assigned to this INO. */ |
70 | /*0x04*/unsigned int virt_irq; | |
71 | }; | |
72 | ||
73 | #define NUM_IVECS (IMAP_INR + 1) | |
1da177e4 LT |
74 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); |
75 | ||
e18e2a00 DM |
76 | #define __irq_ino(irq) \ |
77 | (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) | |
78 | #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) | |
79 | #define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) | |
80 | ||
1da177e4 LT |
81 | /* This has to be in the main kernel image, it cannot be |
82 | * turned into per-cpu data. The reason is that the main | |
83 | * kernel image is locked into the TLB and this structure | |
84 | * is accessed from the vectored interrupt trap handler. If | |
85 | * access to this structure takes a TLB miss it could cause | |
86 | * the 5-level sparc v9 trap stack to overflow. | |
87 | */ | |
fd0504c3 | 88 | #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist) |
1da177e4 | 89 | |
8047e247 | 90 | static unsigned int virt_to_real_irq_table[NR_IRQS]; |
8047e247 DM |
91 | |
92 | static unsigned char virt_irq_alloc(unsigned int real_irq) | |
93 | { | |
94 | unsigned char ent; | |
95 | ||
96 | BUILD_BUG_ON(NR_IRQS >= 256); | |
97 | ||
35a17eb6 DM |
98 | for (ent = 1; ent < NR_IRQS; ent++) { |
99 | if (!virt_to_real_irq_table[ent]) | |
100 | break; | |
101 | } | |
8047e247 DM |
102 | if (ent >= NR_IRQS) { |
103 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
104 | return 0; | |
105 | } | |
106 | ||
8047e247 DM |
107 | virt_to_real_irq_table[ent] = real_irq; |
108 | ||
109 | return ent; | |
110 | } | |
111 | ||
5746c99d | 112 | #ifdef CONFIG_PCI_MSI |
35a17eb6 | 113 | static void virt_irq_free(unsigned int virt_irq) |
8047e247 | 114 | { |
35a17eb6 | 115 | unsigned int real_irq; |
8047e247 | 116 | |
35a17eb6 DM |
117 | if (virt_irq >= NR_IRQS) |
118 | return; | |
119 | ||
120 | real_irq = virt_to_real_irq_table[virt_irq]; | |
121 | virt_to_real_irq_table[virt_irq] = 0; | |
122 | ||
123 | __bucket(real_irq)->virt_irq = 0; | |
8047e247 | 124 | } |
5746c99d | 125 | #endif |
8047e247 DM |
126 | |
127 | static unsigned int virt_to_real_irq(unsigned char virt_irq) | |
128 | { | |
129 | return virt_to_real_irq_table[virt_irq]; | |
130 | } | |
131 | ||
1da177e4 | 132 | /* |
e18e2a00 | 133 | * /proc/interrupts printing: |
1da177e4 | 134 | */ |
1da177e4 LT |
135 | |
136 | int show_interrupts(struct seq_file *p, void *v) | |
137 | { | |
e18e2a00 DM |
138 | int i = *(loff_t *) v, j; |
139 | struct irqaction * action; | |
1da177e4 | 140 | unsigned long flags; |
1da177e4 | 141 | |
e18e2a00 DM |
142 | if (i == 0) { |
143 | seq_printf(p, " "); | |
144 | for_each_online_cpu(j) | |
145 | seq_printf(p, "CPU%d ",j); | |
146 | seq_putc(p, '\n'); | |
147 | } | |
148 | ||
149 | if (i < NR_IRQS) { | |
150 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
151 | action = irq_desc[i].action; | |
152 | if (!action) | |
153 | goto skip; | |
154 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
155 | #ifndef CONFIG_SMP |
156 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
157 | #else | |
e18e2a00 DM |
158 | for_each_online_cpu(j) |
159 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 160 | #endif |
d1bef4ed | 161 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
162 | seq_printf(p, " %s", action->name); |
163 | ||
164 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 165 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 166 | |
1da177e4 | 167 | seq_putc(p, '\n'); |
e18e2a00 DM |
168 | skip: |
169 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 170 | } |
1da177e4 LT |
171 | return 0; |
172 | } | |
173 | ||
ebd8c56c DM |
174 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
175 | { | |
176 | unsigned int tid; | |
177 | ||
178 | if (this_is_starfire) { | |
179 | tid = starfire_translate(imap, cpuid); | |
180 | tid <<= IMAP_TID_SHIFT; | |
181 | tid &= IMAP_TID_UPA; | |
182 | } else { | |
183 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
184 | unsigned long ver; | |
185 | ||
186 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
187 | if ((ver >> 32UL) == __JALAPENO_ID || | |
188 | (ver >> 32UL) == __SERRANO_ID) { | |
189 | tid = cpuid << IMAP_TID_SHIFT; | |
190 | tid &= IMAP_TID_JBUS; | |
191 | } else { | |
192 | unsigned int a = cpuid & 0x1f; | |
193 | unsigned int n = (cpuid >> 5) & 0x1f; | |
194 | ||
195 | tid = ((a << IMAP_AID_SHIFT) | | |
196 | (n << IMAP_NID_SHIFT)); | |
197 | tid &= (IMAP_AID_SAFARI | | |
198 | IMAP_NID_SAFARI);; | |
199 | } | |
200 | } else { | |
201 | tid = cpuid << IMAP_TID_SHIFT; | |
202 | tid &= IMAP_TID_UPA; | |
203 | } | |
204 | } | |
205 | ||
206 | return tid; | |
207 | } | |
208 | ||
e18e2a00 DM |
209 | struct irq_handler_data { |
210 | unsigned long iclr; | |
211 | unsigned long imap; | |
8047e247 | 212 | |
e18e2a00 DM |
213 | void (*pre_handler)(unsigned int, void *, void *); |
214 | void *pre_handler_arg1; | |
215 | void *pre_handler_arg2; | |
216 | }; | |
1da177e4 | 217 | |
e18e2a00 | 218 | static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq) |
1da177e4 | 219 | { |
8047e247 | 220 | unsigned int real_irq = virt_to_real_irq(virt_irq); |
e18e2a00 | 221 | struct ino_bucket *bucket = NULL; |
1da177e4 | 222 | |
e18e2a00 DM |
223 | if (likely(real_irq)) |
224 | bucket = __bucket(real_irq); | |
8047e247 | 225 | |
e18e2a00 | 226 | return bucket; |
1da177e4 LT |
227 | } |
228 | ||
e18e2a00 DM |
229 | #ifdef CONFIG_SMP |
230 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 231 | { |
a53da52f | 232 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 233 | int cpuid; |
088dd1f8 | 234 | |
e18e2a00 DM |
235 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
236 | static int irq_rover; | |
237 | static DEFINE_SPINLOCK(irq_rover_lock); | |
238 | unsigned long flags; | |
1da177e4 | 239 | |
e18e2a00 DM |
240 | /* Round-robin distribution... */ |
241 | do_round_robin: | |
242 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 243 | |
e18e2a00 DM |
244 | while (!cpu_online(irq_rover)) { |
245 | if (++irq_rover >= NR_CPUS) | |
246 | irq_rover = 0; | |
247 | } | |
248 | cpuid = irq_rover; | |
249 | do { | |
250 | if (++irq_rover >= NR_CPUS) | |
251 | irq_rover = 0; | |
252 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 253 | |
e18e2a00 DM |
254 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
255 | } else { | |
256 | cpumask_t tmp; | |
088dd1f8 | 257 | |
e18e2a00 | 258 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 259 | |
e18e2a00 DM |
260 | if (cpus_empty(tmp)) |
261 | goto do_round_robin; | |
088dd1f8 | 262 | |
e18e2a00 | 263 | cpuid = first_cpu(tmp); |
1da177e4 | 264 | } |
088dd1f8 | 265 | |
e18e2a00 DM |
266 | return cpuid; |
267 | } | |
268 | #else | |
269 | static int irq_choose_cpu(unsigned int virt_irq) | |
270 | { | |
271 | return real_hard_smp_processor_id(); | |
1da177e4 | 272 | } |
e18e2a00 | 273 | #endif |
1da177e4 | 274 | |
e18e2a00 | 275 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 276 | { |
68c92186 | 277 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 278 | |
e18e2a00 | 279 | if (likely(data)) { |
861fe906 | 280 | unsigned long cpuid, imap, val; |
e18e2a00 | 281 | unsigned int tid; |
e3999574 | 282 | |
e18e2a00 DM |
283 | cpuid = irq_choose_cpu(virt_irq); |
284 | imap = data->imap; | |
e3999574 | 285 | |
e18e2a00 | 286 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 287 | |
861fe906 DM |
288 | val = upa_readq(imap); |
289 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
290 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
291 | val |= tid | IMAP_VALID; | |
292 | upa_writeq(val, imap); | |
e3999574 | 293 | } |
e3999574 DM |
294 | } |
295 | ||
e18e2a00 | 296 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 297 | { |
68c92186 | 298 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 299 | |
e18e2a00 DM |
300 | if (likely(data)) { |
301 | unsigned long imap = data->imap; | |
861fe906 | 302 | u32 tmp = upa_readq(imap); |
1da177e4 | 303 | |
e18e2a00 | 304 | tmp &= ~IMAP_VALID; |
861fe906 | 305 | upa_writeq(tmp, imap); |
088dd1f8 | 306 | } |
088dd1f8 DM |
307 | } |
308 | ||
e18e2a00 | 309 | static void sun4u_irq_end(unsigned int virt_irq) |
088dd1f8 | 310 | { |
68c92186 | 311 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
5a606b72 DM |
312 | struct irq_desc *desc = irq_desc + virt_irq; |
313 | ||
314 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
315 | return; | |
088dd1f8 | 316 | |
e18e2a00 | 317 | if (likely(data)) |
861fe906 | 318 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
319 | } |
320 | ||
e18e2a00 | 321 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 322 | { |
e18e2a00 DM |
323 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
324 | unsigned int ino = bucket - &ivector_table[0]; | |
088dd1f8 | 325 | |
e18e2a00 DM |
326 | if (likely(bucket)) { |
327 | unsigned long cpuid; | |
328 | int err; | |
088dd1f8 | 329 | |
e18e2a00 | 330 | cpuid = irq_choose_cpu(virt_irq); |
088dd1f8 | 331 | |
e18e2a00 DM |
332 | err = sun4v_intr_settarget(ino, cpuid); |
333 | if (err != HV_EOK) | |
334 | printk("sun4v_intr_settarget(%x,%lu): err(%d)\n", | |
335 | ino, cpuid, err); | |
a357b8f4 DM |
336 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
337 | if (err != HV_EOK) | |
338 | printk("sun4v_intr_setstate(%x): " | |
339 | "err(%d)\n", ino, err); | |
e18e2a00 DM |
340 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); |
341 | if (err != HV_EOK) | |
342 | printk("sun4v_intr_setenabled(%x): err(%d)\n", | |
343 | ino, err); | |
088dd1f8 | 344 | } |
088dd1f8 DM |
345 | } |
346 | ||
e18e2a00 | 347 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 348 | { |
e18e2a00 DM |
349 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
350 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 351 | |
e18e2a00 DM |
352 | if (likely(bucket)) { |
353 | int err; | |
1da177e4 | 354 | |
e18e2a00 DM |
355 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
356 | if (err != HV_EOK) | |
357 | printk("sun4v_intr_setenabled(%x): " | |
358 | "err(%d)\n", ino, err); | |
1da177e4 | 359 | } |
e18e2a00 | 360 | } |
1da177e4 | 361 | |
35a17eb6 DM |
362 | #ifdef CONFIG_PCI_MSI |
363 | static void sun4v_msi_enable(unsigned int virt_irq) | |
364 | { | |
365 | sun4v_irq_enable(virt_irq); | |
366 | unmask_msi_irq(virt_irq); | |
367 | } | |
368 | ||
369 | static void sun4v_msi_disable(unsigned int virt_irq) | |
370 | { | |
371 | mask_msi_irq(virt_irq); | |
372 | sun4v_irq_disable(virt_irq); | |
373 | } | |
374 | #endif | |
375 | ||
e18e2a00 DM |
376 | static void sun4v_irq_end(unsigned int virt_irq) |
377 | { | |
378 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
379 | unsigned int ino = bucket - &ivector_table[0]; | |
5a606b72 DM |
380 | struct irq_desc *desc = irq_desc + virt_irq; |
381 | ||
382 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
383 | return; | |
1da177e4 | 384 | |
e18e2a00 DM |
385 | if (likely(bucket)) { |
386 | int err; | |
1da177e4 | 387 | |
e18e2a00 DM |
388 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
389 | if (err != HV_EOK) | |
390 | printk("sun4v_intr_setstate(%x): " | |
391 | "err(%d)\n", ino, err); | |
1da177e4 | 392 | } |
1da177e4 LT |
393 | } |
394 | ||
4a907dec DM |
395 | static void sun4v_virq_enable(unsigned int virt_irq) |
396 | { | |
397 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
398 | unsigned int ino = bucket - &ivector_table[0]; | |
399 | ||
400 | if (likely(bucket)) { | |
401 | unsigned long cpuid, dev_handle, dev_ino; | |
402 | int err; | |
403 | ||
404 | cpuid = irq_choose_cpu(virt_irq); | |
405 | ||
406 | dev_handle = ino & IMAP_IGN; | |
407 | dev_ino = ino & IMAP_INO; | |
408 | ||
409 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
410 | if (err != HV_EOK) | |
411 | printk("sun4v_vintr_set_target(%lx,%lx,%lu): " | |
412 | "err(%d)\n", | |
413 | dev_handle, dev_ino, cpuid, err); | |
414 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
12450884 DM |
415 | HV_INTR_STATE_IDLE); |
416 | if (err != HV_EOK) | |
417 | printk("sun4v_vintr_set_state(%lx,%lx," | |
418 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
419 | dev_handle, dev_ino, err); | |
420 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
4a907dec DM |
421 | HV_INTR_ENABLED); |
422 | if (err != HV_EOK) | |
423 | printk("sun4v_vintr_set_state(%lx,%lx," | |
424 | "HV_INTR_ENABLED): err(%d)\n", | |
425 | dev_handle, dev_ino, err); | |
426 | } | |
427 | } | |
428 | ||
429 | static void sun4v_virq_disable(unsigned int virt_irq) | |
430 | { | |
431 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
432 | unsigned int ino = bucket - &ivector_table[0]; | |
433 | ||
434 | if (likely(bucket)) { | |
435 | unsigned long dev_handle, dev_ino; | |
436 | int err; | |
437 | ||
438 | dev_handle = ino & IMAP_IGN; | |
439 | dev_ino = ino & IMAP_INO; | |
440 | ||
12450884 | 441 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, |
4a907dec DM |
442 | HV_INTR_DISABLED); |
443 | if (err != HV_EOK) | |
444 | printk("sun4v_vintr_set_state(%lx,%lx," | |
445 | "HV_INTR_DISABLED): err(%d)\n", | |
446 | dev_handle, dev_ino, err); | |
447 | } | |
448 | } | |
449 | ||
450 | static void sun4v_virq_end(unsigned int virt_irq) | |
451 | { | |
452 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
453 | unsigned int ino = bucket - &ivector_table[0]; | |
5a606b72 DM |
454 | struct irq_desc *desc = irq_desc + virt_irq; |
455 | ||
456 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
457 | return; | |
4a907dec DM |
458 | |
459 | if (likely(bucket)) { | |
460 | unsigned long dev_handle, dev_ino; | |
461 | int err; | |
462 | ||
463 | dev_handle = ino & IMAP_IGN; | |
464 | dev_ino = ino & IMAP_INO; | |
465 | ||
466 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
467 | HV_INTR_STATE_IDLE); | |
468 | if (err != HV_EOK) | |
469 | printk("sun4v_vintr_set_state(%lx,%lx," | |
470 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
471 | dev_handle, dev_ino, err); | |
472 | } | |
473 | } | |
474 | ||
e18e2a00 | 475 | static void run_pre_handler(unsigned int virt_irq) |
1da177e4 | 476 | { |
e18e2a00 | 477 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
68c92186 | 478 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 479 | |
e18e2a00 DM |
480 | if (likely(data->pre_handler)) { |
481 | data->pre_handler(__irq_ino(__irq(bucket)), | |
482 | data->pre_handler_arg1, | |
483 | data->pre_handler_arg2); | |
1da177e4 | 484 | } |
088dd1f8 DM |
485 | } |
486 | ||
729e7d7e | 487 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
488 | .typename = "sun4u", |
489 | .enable = sun4u_irq_enable, | |
490 | .disable = sun4u_irq_disable, | |
491 | .end = sun4u_irq_end, | |
492 | }; | |
8047e247 | 493 | |
729e7d7e | 494 | static struct irq_chip sun4u_irq_ack = { |
e18e2a00 DM |
495 | .typename = "sun4u+ack", |
496 | .enable = sun4u_irq_enable, | |
497 | .disable = sun4u_irq_disable, | |
498 | .ack = run_pre_handler, | |
499 | .end = sun4u_irq_end, | |
500 | }; | |
088dd1f8 | 501 | |
729e7d7e | 502 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
503 | .typename = "sun4v", |
504 | .enable = sun4v_irq_enable, | |
505 | .disable = sun4v_irq_disable, | |
506 | .end = sun4v_irq_end, | |
507 | }; | |
1da177e4 | 508 | |
729e7d7e | 509 | static struct irq_chip sun4v_irq_ack = { |
e18e2a00 DM |
510 | .typename = "sun4v+ack", |
511 | .enable = sun4v_irq_enable, | |
512 | .disable = sun4v_irq_disable, | |
513 | .ack = run_pre_handler, | |
514 | .end = sun4v_irq_end, | |
515 | }; | |
1da177e4 | 516 | |
35a17eb6 DM |
517 | #ifdef CONFIG_PCI_MSI |
518 | static struct irq_chip sun4v_msi = { | |
519 | .typename = "sun4v+msi", | |
520 | .mask = mask_msi_irq, | |
521 | .unmask = unmask_msi_irq, | |
522 | .enable = sun4v_msi_enable, | |
523 | .disable = sun4v_msi_disable, | |
524 | .ack = run_pre_handler, | |
525 | .end = sun4v_irq_end, | |
526 | }; | |
527 | #endif | |
528 | ||
4a907dec DM |
529 | static struct irq_chip sun4v_virq = { |
530 | .typename = "vsun4v", | |
531 | .enable = sun4v_virq_enable, | |
532 | .disable = sun4v_virq_disable, | |
533 | .end = sun4v_virq_end, | |
534 | }; | |
535 | ||
536 | static struct irq_chip sun4v_virq_ack = { | |
537 | .typename = "vsun4v+ack", | |
538 | .enable = sun4v_virq_enable, | |
539 | .disable = sun4v_virq_disable, | |
540 | .ack = run_pre_handler, | |
541 | .end = sun4v_virq_end, | |
542 | }; | |
543 | ||
e18e2a00 DM |
544 | void irq_install_pre_handler(int virt_irq, |
545 | void (*func)(unsigned int, void *, void *), | |
546 | void *arg1, void *arg2) | |
547 | { | |
68c92186 DM |
548 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
549 | struct irq_chip *chip; | |
088dd1f8 | 550 | |
e18e2a00 DM |
551 | data->pre_handler = func; |
552 | data->pre_handler_arg1 = arg1; | |
553 | data->pre_handler_arg2 = arg2; | |
1da177e4 | 554 | |
68c92186 DM |
555 | chip = get_irq_chip(virt_irq); |
556 | if (chip == &sun4u_irq_ack || | |
4a907dec DM |
557 | chip == &sun4v_irq_ack || |
558 | chip == &sun4v_virq_ack | |
35a17eb6 DM |
559 | #ifdef CONFIG_PCI_MSI |
560 | || chip == &sun4v_msi | |
561 | #endif | |
562 | ) | |
24ac26d4 DM |
563 | return; |
564 | ||
68c92186 | 565 | chip = (chip == &sun4u_irq ? |
4a907dec DM |
566 | &sun4u_irq_ack : |
567 | (chip == &sun4v_irq ? | |
568 | &sun4v_irq_ack : &sun4v_virq_ack)); | |
68c92186 | 569 | set_irq_chip(virt_irq, chip); |
e18e2a00 | 570 | } |
1da177e4 | 571 | |
e18e2a00 DM |
572 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
573 | { | |
574 | struct ino_bucket *bucket; | |
575 | struct irq_handler_data *data; | |
e18e2a00 | 576 | int ino; |
1da177e4 | 577 | |
e18e2a00 | 578 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 579 | |
861fe906 | 580 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 DM |
581 | bucket = &ivector_table[ino]; |
582 | if (!bucket->virt_irq) { | |
583 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 584 | set_irq_chip(bucket->virt_irq, &sun4u_irq); |
fd0504c3 | 585 | } |
1da177e4 | 586 | |
68c92186 DM |
587 | data = get_irq_chip_data(bucket->virt_irq); |
588 | if (unlikely(data)) | |
e18e2a00 | 589 | goto out; |
fd0504c3 | 590 | |
e18e2a00 DM |
591 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
592 | if (unlikely(!data)) { | |
593 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
594 | prom_halt(); | |
1da177e4 | 595 | } |
68c92186 | 596 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 597 | |
e18e2a00 DM |
598 | data->imap = imap; |
599 | data->iclr = iclr; | |
1da177e4 | 600 | |
e18e2a00 DM |
601 | out: |
602 | return bucket->virt_irq; | |
603 | } | |
1da177e4 | 604 | |
4a907dec DM |
605 | static unsigned int sun4v_build_common(unsigned long sysino, |
606 | struct irq_chip *chip) | |
1da177e4 | 607 | { |
8047e247 | 608 | struct ino_bucket *bucket; |
e18e2a00 | 609 | struct irq_handler_data *data; |
8047e247 | 610 | |
e18e2a00 | 611 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 612 | |
e18e2a00 DM |
613 | bucket = &ivector_table[sysino]; |
614 | if (!bucket->virt_irq) { | |
615 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
4a907dec | 616 | set_irq_chip(bucket->virt_irq, chip); |
1da177e4 | 617 | } |
1da177e4 | 618 | |
68c92186 DM |
619 | data = get_irq_chip_data(bucket->virt_irq); |
620 | if (unlikely(data)) | |
1da177e4 | 621 | goto out; |
1da177e4 | 622 | |
e18e2a00 DM |
623 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
624 | if (unlikely(!data)) { | |
625 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
626 | prom_halt(); | |
627 | } | |
68c92186 | 628 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 629 | |
e18e2a00 DM |
630 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
631 | * is done by hypervisor calls on sun4v platforms, not by direct | |
632 | * register accesses. | |
633 | */ | |
634 | data->imap = ~0UL; | |
635 | data->iclr = ~0UL; | |
1da177e4 | 636 | |
e18e2a00 DM |
637 | out: |
638 | return bucket->virt_irq; | |
639 | } | |
1da177e4 | 640 | |
4a907dec DM |
641 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
642 | { | |
643 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
644 | ||
645 | return sun4v_build_common(sysino, &sun4v_irq); | |
646 | } | |
647 | ||
648 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
649 | { | |
650 | unsigned long sysino, hv_err; | |
651 | ||
652 | BUG_ON(devhandle & ~IMAP_IGN); | |
653 | BUG_ON(devino & ~IMAP_INO); | |
654 | ||
655 | sysino = devhandle | devino; | |
656 | ||
657 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, sysino); | |
658 | if (hv_err) { | |
659 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
660 | "err=%lu\n", devhandle, devino, hv_err); | |
661 | prom_halt(); | |
662 | } | |
663 | ||
664 | return sun4v_build_common(sysino, &sun4v_virq); | |
665 | } | |
666 | ||
35a17eb6 DM |
667 | #ifdef CONFIG_PCI_MSI |
668 | unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, | |
669 | unsigned int msi_start, unsigned int msi_end) | |
670 | { | |
671 | struct ino_bucket *bucket; | |
672 | struct irq_handler_data *data; | |
673 | unsigned long sysino; | |
674 | unsigned int devino; | |
675 | ||
676 | BUG_ON(tlb_type != hypervisor); | |
677 | ||
678 | /* Find a free devino in the given range. */ | |
679 | for (devino = msi_start; devino < msi_end; devino++) { | |
680 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
681 | bucket = &ivector_table[sysino]; | |
682 | if (!bucket->virt_irq) | |
683 | break; | |
684 | } | |
685 | if (devino >= msi_end) | |
686 | return 0; | |
687 | ||
688 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
689 | bucket = &ivector_table[sysino]; | |
690 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
691 | *virt_irq_p = bucket->virt_irq; | |
692 | set_irq_chip(bucket->virt_irq, &sun4v_msi); | |
693 | ||
694 | data = get_irq_chip_data(bucket->virt_irq); | |
695 | if (unlikely(data)) | |
696 | return devino; | |
697 | ||
698 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); | |
699 | if (unlikely(!data)) { | |
700 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
701 | prom_halt(); | |
702 | } | |
703 | set_irq_chip_data(bucket->virt_irq, data); | |
704 | ||
705 | data->imap = ~0UL; | |
706 | data->iclr = ~0UL; | |
707 | ||
708 | return devino; | |
709 | } | |
710 | ||
711 | void sun4v_destroy_msi(unsigned int virt_irq) | |
712 | { | |
713 | virt_irq_free(virt_irq); | |
714 | } | |
715 | #endif | |
716 | ||
e18e2a00 DM |
717 | void ack_bad_irq(unsigned int virt_irq) |
718 | { | |
719 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
720 | unsigned int ino = 0xdeadbeef; | |
ab66a50e | 721 | |
e18e2a00 DM |
722 | if (bucket) |
723 | ino = bucket - &ivector_table[0]; | |
6a76267f | 724 | |
e18e2a00 DM |
725 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
726 | ino, virt_irq); | |
1da177e4 LT |
727 | } |
728 | ||
1da177e4 LT |
729 | void handler_irq(int irq, struct pt_regs *regs) |
730 | { | |
e18e2a00 | 731 | struct ino_bucket *bucket; |
6d24c8dc | 732 | struct pt_regs *old_regs; |
1da177e4 | 733 | |
1da177e4 | 734 | clear_softint(1 << irq); |
1da177e4 | 735 | |
6d24c8dc | 736 | old_regs = set_irq_regs(regs); |
1da177e4 | 737 | irq_enter(); |
1da177e4 LT |
738 | |
739 | /* Sliiiick... */ | |
e18e2a00 DM |
740 | bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0)); |
741 | while (bucket) { | |
742 | struct ino_bucket *next = __bucket(bucket->irq_chain); | |
1da177e4 | 743 | |
e18e2a00 | 744 | bucket->irq_chain = 0; |
6d24c8dc | 745 | __do_IRQ(bucket->virt_irq); |
fd0504c3 | 746 | |
e18e2a00 | 747 | bucket = next; |
1da177e4 | 748 | } |
e18e2a00 | 749 | |
1da177e4 | 750 | irq_exit(); |
6d24c8dc | 751 | set_irq_regs(old_regs); |
1da177e4 LT |
752 | } |
753 | ||
cdd5186f DM |
754 | struct sun5_timer { |
755 | u64 count0; | |
756 | u64 limit0; | |
757 | u64 count1; | |
758 | u64 limit1; | |
759 | }; | |
1da177e4 | 760 | |
cdd5186f | 761 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
762 | static u64 prom_limit0, prom_limit1; |
763 | ||
764 | static void map_prom_timers(void) | |
765 | { | |
25c7581b | 766 | struct device_node *dp; |
6a23acf3 | 767 | const unsigned int *addr; |
1da177e4 LT |
768 | |
769 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
770 | dp = of_find_node_by_path("/"); |
771 | dp = dp->child; | |
772 | while (dp) { | |
773 | if (!strcmp(dp->name, "counter-timer")) | |
774 | break; | |
775 | dp = dp->sibling; | |
776 | } | |
1da177e4 LT |
777 | |
778 | /* Assume if node is not present, PROM uses different tick mechanism | |
779 | * which we should not care about. | |
780 | */ | |
25c7581b | 781 | if (!dp) { |
1da177e4 LT |
782 | prom_timers = (struct sun5_timer *) 0; |
783 | return; | |
784 | } | |
785 | ||
786 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
787 | addr = of_get_property(dp, "address", NULL); |
788 | if (!addr) { | |
1da177e4 LT |
789 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
790 | prom_timers = (struct sun5_timer *) 0; | |
791 | return; | |
792 | } | |
793 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
794 | } | |
795 | ||
796 | static void kill_prom_timer(void) | |
797 | { | |
798 | if (!prom_timers) | |
799 | return; | |
800 | ||
801 | /* Save them away for later. */ | |
802 | prom_limit0 = prom_timers->limit0; | |
803 | prom_limit1 = prom_timers->limit1; | |
804 | ||
805 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
806 | * We turn both off here just to be paranoid. | |
807 | */ | |
808 | prom_timers->limit0 = 0; | |
809 | prom_timers->limit1 = 0; | |
810 | ||
811 | /* Wheee, eat the interrupt packet too... */ | |
812 | __asm__ __volatile__( | |
813 | " mov 0x40, %%g2\n" | |
814 | " ldxa [%%g0] %0, %%g1\n" | |
815 | " ldxa [%%g2] %1, %%g1\n" | |
816 | " stxa %%g0, [%%g0] %0\n" | |
817 | " membar #Sync\n" | |
818 | : /* no outputs */ | |
819 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
820 | : "g1", "g2"); | |
821 | } | |
822 | ||
1da177e4 LT |
823 | void init_irqwork_curcpu(void) |
824 | { | |
1da177e4 LT |
825 | int cpu = hard_smp_processor_id(); |
826 | ||
fd0504c3 | 827 | trap_block[cpu].irq_worklist = 0; |
1da177e4 LT |
828 | } |
829 | ||
5cbc3073 DM |
830 | /* Please be very careful with register_one_mondo() and |
831 | * sun4v_register_mondo_queues(). | |
832 | * | |
833 | * On SMP this gets invoked from the CPU trampoline before | |
834 | * the cpu has fully taken over the trap table from OBP, | |
835 | * and it's kernel stack + %g6 thread register state is | |
836 | * not fully cooked yet. | |
837 | * | |
838 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
839 | * from these two routines. | |
840 | */ | |
841 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 842 | { |
5cbc3073 | 843 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
844 | unsigned long status; |
845 | ||
846 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
847 | if (status != HV_EOK) { | |
848 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
849 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
850 | prom_halt(); |
851 | } | |
852 | } | |
853 | ||
b5a37e96 | 854 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 855 | { |
b5a37e96 DM |
856 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
857 | ||
5cbc3073 DM |
858 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
859 | tb->cpu_mondo_qmask); | |
860 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
861 | tb->dev_mondo_qmask); | |
862 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
863 | tb->resum_qmask); | |
864 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
865 | tb->nonresum_qmask); | |
b5a37e96 DM |
866 | } |
867 | ||
5cbc3073 | 868 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask, int use_bootmem) |
b5a37e96 | 869 | { |
5cbc3073 DM |
870 | unsigned long size = PAGE_ALIGN(qmask + 1); |
871 | unsigned long order = get_order(size); | |
872 | void *p = NULL; | |
b5a37e96 | 873 | |
5cbc3073 DM |
874 | if (use_bootmem) { |
875 | p = __alloc_bootmem_low(size, size, 0); | |
876 | } else { | |
877 | struct page *page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, order); | |
878 | if (page) | |
879 | p = page_address(page); | |
880 | } | |
b5a37e96 | 881 | |
5cbc3073 | 882 | if (!p) { |
b5a37e96 DM |
883 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
884 | prom_halt(); | |
885 | } | |
886 | ||
5cbc3073 | 887 | *pa_ptr = __pa(p); |
b5a37e96 DM |
888 | } |
889 | ||
5cbc3073 | 890 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask, int use_bootmem) |
b5a37e96 | 891 | { |
5cbc3073 DM |
892 | unsigned long size = PAGE_ALIGN(qmask + 1); |
893 | unsigned long order = get_order(size); | |
894 | void *p = NULL; | |
b5a37e96 | 895 | |
5cbc3073 DM |
896 | if (use_bootmem) { |
897 | p = __alloc_bootmem_low(size, size, 0); | |
898 | } else { | |
899 | struct page *page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, order); | |
900 | if (page) | |
901 | p = page_address(page); | |
902 | } | |
5b0c0572 | 903 | |
5cbc3073 | 904 | if (!p) { |
5b0c0572 DM |
905 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
906 | prom_halt(); | |
907 | } | |
908 | ||
5cbc3073 | 909 | *pa_ptr = __pa(p); |
5b0c0572 DM |
910 | } |
911 | ||
b5a37e96 | 912 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
913 | { |
914 | #ifdef CONFIG_SMP | |
b5a37e96 | 915 | void *page; |
1d2f1f90 DM |
916 | |
917 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
918 | ||
b5a37e96 DM |
919 | if (use_bootmem) |
920 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
921 | else | |
922 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
923 | ||
1d2f1f90 DM |
924 | if (!page) { |
925 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
926 | prom_halt(); | |
927 | } | |
928 | ||
929 | tb->cpu_mondo_block_pa = __pa(page); | |
930 | tb->cpu_list_pa = __pa(page + 64); | |
931 | #endif | |
932 | } | |
933 | ||
b5a37e96 | 934 | /* Allocate and register the mondo and error queues for this cpu. */ |
72aff53f | 935 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load) |
ac29c11d | 936 | { |
ac29c11d DM |
937 | struct trap_per_cpu *tb = &trap_block[cpu]; |
938 | ||
72aff53f | 939 | if (alloc) { |
5cbc3073 DM |
940 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask, use_bootmem); |
941 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask, use_bootmem); | |
942 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask, use_bootmem); | |
943 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask, use_bootmem); | |
944 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask, use_bootmem); | |
945 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, tb->nonresum_qmask, use_bootmem); | |
1d2f1f90 | 946 | |
72aff53f DM |
947 | init_cpu_send_mondo_info(tb, use_bootmem); |
948 | } | |
1d2f1f90 | 949 | |
72aff53f DM |
950 | if (load) { |
951 | if (cpu != hard_smp_processor_id()) { | |
952 | prom_printf("SUN4V: init mondo on cpu %d not %d\n", | |
953 | cpu, hard_smp_processor_id()); | |
954 | prom_halt(); | |
955 | } | |
956 | sun4v_register_mondo_queues(cpu); | |
957 | } | |
ac29c11d DM |
958 | } |
959 | ||
e18e2a00 DM |
960 | static struct irqaction timer_irq_action = { |
961 | .name = "timer", | |
962 | }; | |
963 | ||
1da177e4 LT |
964 | /* Only invoked on boot processor. */ |
965 | void __init init_IRQ(void) | |
966 | { | |
967 | map_prom_timers(); | |
968 | kill_prom_timer(); | |
969 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
970 | ||
ac29c11d | 971 | if (tlb_type == hypervisor) |
72aff53f | 972 | sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1); |
ac29c11d | 973 | |
1da177e4 LT |
974 | /* We need to clear any IRQ's pending in the soft interrupt |
975 | * registers, a spurious one could be left around from the | |
976 | * PROM timer which we just disabled. | |
977 | */ | |
978 | clear_softint(get_softint()); | |
979 | ||
980 | /* Now that ivector table is initialized, it is safe | |
981 | * to receive IRQ vector traps. We will normally take | |
982 | * one or two right now, in case some device PROM used | |
983 | * to boot us wants to speak to us. We just ignore them. | |
984 | */ | |
985 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
986 | "or %%g1, %0, %%g1\n\t" | |
987 | "wrpr %%g1, 0x0, %%pstate" | |
988 | : /* No outputs */ | |
989 | : "i" (PSTATE_IE) | |
990 | : "g1"); | |
1da177e4 | 991 | |
e18e2a00 | 992 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 993 | } |