[deliverable/linux.git] / arch / sparc64 / kernel / pci.c

/* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
 * pci.c: UltraSparc PCI controller support.
 *
 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
 * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
 * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/capability.h>
#include <linux/errno.h>
#include <linux/smp_lock.h>
#include <linux/msi.h>
#include <linux/irq.h>
#include <linux/init.h>

#include <asm/uaccess.h>
#include <asm/pbm.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/ebus.h>
#include <asm/isa.h>
#include <asm/prom.h>

unsigned long pci_memspace_mask = 0xffffffffUL;

#ifndef CONFIG_PCI
/* A "nop" PCI implementation. */
asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
				  unsigned long off, unsigned long len,
				  unsigned char *buf)
{
	return 0;
}
asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
				   unsigned long off, unsigned long len,
				   unsigned char *buf)
{
	return 0;
}
#else

/* List of all PCI controllers found in the system. */
struct pci_controller_info *pci_controller_root = NULL;

/* Each PCI controller found gets a unique index. */
int pci_num_controllers = 0;

volatile int pci_poke_in_progress;
volatile int pci_poke_cpu = -1;
volatile int pci_poke_faulted;

static DEFINE_SPINLOCK(pci_poke_lock);

void pci_config_read8(u8 *addr, u8 *ret)
{
	unsigned long flags;
	u8 byte;

	spin_lock_irqsave(&pci_poke_lock, flags);
	pci_poke_cpu = smp_processor_id();
	pci_poke_in_progress = 1;
	pci_poke_faulted = 0;
	__asm__ __volatile__("membar #Sync\n\t"
			     "lduba [%1] %2, %0\n\t"
			     "membar #Sync"
			     : "=r" (byte)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	pci_poke_in_progress = 0;
	pci_poke_cpu = -1;
	if (!pci_poke_faulted)
		*ret = byte;
	spin_unlock_irqrestore(&pci_poke_lock, flags);
}

void pci_config_read16(u16 *addr, u16 *ret)
{
	unsigned long flags;
	u16 word;

	spin_lock_irqsave(&pci_poke_lock, flags);
	pci_poke_cpu = smp_processor_id();
	pci_poke_in_progress = 1;
	pci_poke_faulted = 0;
	__asm__ __volatile__("membar #Sync\n\t"
			     "lduha [%1] %2, %0\n\t"
			     "membar #Sync"
			     : "=r" (word)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	pci_poke_in_progress = 0;
	pci_poke_cpu = -1;
	if (!pci_poke_faulted)
		*ret = word;
	spin_unlock_irqrestore(&pci_poke_lock, flags);
}

void pci_config_read32(u32 *addr, u32 *ret)
{
	unsigned long flags;
	u32 dword;

	spin_lock_irqsave(&pci_poke_lock, flags);
	pci_poke_cpu = smp_processor_id();
	pci_poke_in_progress = 1;
	pci_poke_faulted = 0;
	__asm__ __volatile__("membar #Sync\n\t"
			     "lduwa [%1] %2, %0\n\t"
			     "membar #Sync"
			     : "=r" (dword)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	pci_poke_in_progress = 0;
	pci_poke_cpu = -1;
	if (!pci_poke_faulted)
		*ret = dword;
	spin_unlock_irqrestore(&pci_poke_lock, flags);
}

void pci_config_write8(u8 *addr, u8 val)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_poke_lock, flags);
	pci_poke_cpu = smp_processor_id();
	pci_poke_in_progress = 1;
	pci_poke_faulted = 0;
	__asm__ __volatile__("membar #Sync\n\t"
			     "stba %0, [%1] %2\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	pci_poke_in_progress = 0;
	pci_poke_cpu = -1;
	spin_unlock_irqrestore(&pci_poke_lock, flags);
}

void pci_config_write16(u16 *addr, u16 val)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_poke_lock, flags);
	pci_poke_cpu = smp_processor_id();
	pci_poke_in_progress = 1;
	pci_poke_faulted = 0;
	__asm__ __volatile__("membar #Sync\n\t"
			     "stha %0, [%1] %2\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	pci_poke_in_progress = 0;
	pci_poke_cpu = -1;
	spin_unlock_irqrestore(&pci_poke_lock, flags);
}

void pci_config_write32(u32 *addr, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_poke_lock, flags);
	pci_poke_cpu = smp_processor_id();
	pci_poke_in_progress = 1;
	pci_poke_faulted = 0;
	__asm__ __volatile__("membar #Sync\n\t"
			     "stwa %0, [%1] %2\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	pci_poke_in_progress = 0;
	pci_poke_cpu = -1;
	spin_unlock_irqrestore(&pci_poke_lock, flags);
}

/* Probe for all PCI controllers in the system. */
extern void sabre_init(struct device_node *, const char *);
extern void psycho_init(struct device_node *, const char *);
extern void schizo_init(struct device_node *, const char *);
extern void schizo_plus_init(struct device_node *, const char *);
extern void tomatillo_init(struct device_node *, const char *);
extern void sun4v_pci_init(struct device_node *, const char *);

static struct {
	char *model_name;
	void (*init)(struct device_node *, const char *);
} pci_controller_table[] __initdata = {
	{ "SUNW,sabre", sabre_init },
	{ "pci108e,a000", sabre_init },
	{ "pci108e,a001", sabre_init },
	{ "SUNW,psycho", psycho_init },
	{ "pci108e,8000", psycho_init },
	{ "SUNW,schizo", schizo_init },
	{ "pci108e,8001", schizo_init },
	{ "SUNW,schizo+", schizo_plus_init },
	{ "pci108e,8002", schizo_plus_init },
	{ "SUNW,tomatillo", tomatillo_init },
	{ "pci108e,a801", tomatillo_init },
	{ "SUNW,sun4v-pci", sun4v_pci_init },
};
#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
				  sizeof(pci_controller_table[0]))

static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
{
	int i;

	for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
		if (!strncmp(model_name,
			     pci_controller_table[i].model_name,
			     namelen)) {
			pci_controller_table[i].init(dp, model_name);
			return 1;
		}
	}

	return 0;
}

static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
{
	int i;

	for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
		if (!strncmp(model_name,
			     pci_controller_table[i].model_name,
			     namelen)) {
			return 1;
		}
	}
	return 0;
}

static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
{
	struct device_node *dp;
	int count = 0;

	for_each_node_by_name(dp, "pci") {
		struct property *prop;
		int len;

		prop = of_find_property(dp, "model", &len);
		if (!prop)
			prop = of_find_property(dp, "compatible", &len);

		if (prop) {
			const char *model = prop->value;
			int item_len = 0;

			/* Our value may be a multi-valued string in the
			 * case of some compatible properties. For sanity,
			 * only try the first one.
			 */
			while (model[item_len] && len) {
				len--;
				item_len++;
			}

			if (handler(model, item_len, dp))
				count++;
		}
	}

	return count;
}


/* Is there some PCI controller in the system?  */
int __init pcic_present(void)
{
	return pci_controller_scan(pci_is_controller);
}

struct pci_iommu_ops *pci_iommu_ops;
EXPORT_SYMBOL(pci_iommu_ops);

extern struct pci_iommu_ops pci_sun4u_iommu_ops,
	pci_sun4v_iommu_ops;

/* Find each controller in the system, attach and initialize
 * software state structure for each and link into the
 * pci_controller_root.  Setup the controller enough such
 * that bus scanning can be done.
 */
static void __init pci_controller_probe(void)
{
	if (tlb_type == hypervisor)
		pci_iommu_ops = &pci_sun4v_iommu_ops;
	else
		pci_iommu_ops = &pci_sun4u_iommu_ops;

	printk("PCI: Probing for controllers.\n");

	pci_controller_scan(pci_controller_init);
}

static void __init pci_scan_each_controller_bus(void)
{
	struct pci_controller_info *p;

	for (p = pci_controller_root; p; p = p->next)
		p->scan_bus(p);
}

extern void power_init(void);

static int __init pcibios_init(void)
{
	pci_controller_probe();
	if (pci_controller_root == NULL)
		return 0;

	pci_scan_each_controller_bus();

	isa_init();
	ebus_init();
	power_init();

	return 0;
}

subsys_initcall(pcibios_init);

void pcibios_fixup_bus(struct pci_bus *pbus)
{
	struct pci_pbm_info *pbm = pbus->sysdata;

	/* Generic PCI bus probing sets these to point at
	 * &io{port,mem}_resouce which is wrong for us.
	 */
	pbus->resource[0] = &pbm->io_space;
	pbus->resource[1] = &pbm->mem_space;
}

struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
{
	struct pci_pbm_info *pbm = pdev->bus->sysdata;
	struct resource *root = NULL;

	if (r->flags & IORESOURCE_IO)
		root = &pbm->io_space;
	if (r->flags & IORESOURCE_MEM)
		root = &pbm->mem_space;

	return root;
}

void pcibios_update_irq(struct pci_dev *pdev, int irq)
{
}

void pcibios_align_resource(void *data, struct resource *res,
			    resource_size_t size, resource_size_t align)
{
}

int pcibios_enable_device(struct pci_dev *pdev, int mask)
{
	return 0;
}

void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
			     struct resource *res)
{
	struct pci_pbm_info *pbm = pdev->bus->sysdata;
	struct resource zero_res, *root;

	zero_res.start = 0;
	zero_res.end = 0;
	zero_res.flags = res->flags;

	if (res->flags & IORESOURCE_IO)
		root = &pbm->io_space;
	else
		root = &pbm->mem_space;

	pbm->parent->resource_adjust(pdev, &zero_res, root);

	region->start = res->start - zero_res.start;
	region->end = res->end - zero_res.start;
}
EXPORT_SYMBOL(pcibios_resource_to_bus);

void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
			     struct pci_bus_region *region)
{
	struct pci_pbm_info *pbm = pdev->bus->sysdata;
	struct resource *root;

	res->start = region->start;
	res->end = region->end;

	if (res->flags & IORESOURCE_IO)
		root = &pbm->io_space;
	else
		root = &pbm->mem_space;

	pbm->parent->resource_adjust(pdev, res, root);
}
EXPORT_SYMBOL(pcibios_bus_to_resource);

char * __init pcibios_setup(char *str)
{
	return str;
}

/* Platform support for /proc/bus/pci/X/Y mmap()s. */

/* If the user uses a host-bridge as the PCI device, he may use
 * this to perform a raw mmap() of the I/O or MEM space behind
 * that controller.
 *
 * This can be useful for execution of x86 PCI bios initialization code
 * on a PCI card, like the xfree86 int10 stuff does.
 */
static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
				      enum pci_mmap_state mmap_state)
{
	struct pcidev_cookie *pcp = pdev->sysdata;
	struct pci_pbm_info *pbm;
	struct pci_controller_info *p;
	unsigned long space_size, user_offset, user_size;

	if (!pcp)
		return -ENXIO;
	pbm = pcp->pbm;
	if (!pbm)
		return -ENXIO;

	p = pbm->parent;
	if (p->pbms_same_domain) {
		unsigned long lowest, highest;

		lowest = ~0UL; highest = 0UL;
		if (mmap_state == pci_mmap_io) {
			if (p->pbm_A.io_space.flags) {
				lowest = p->pbm_A.io_space.start;
				highest = p->pbm_A.io_space.end + 1;
			}
			if (p->pbm_B.io_space.flags) {
				if (lowest > p->pbm_B.io_space.start)
					lowest = p->pbm_B.io_space.start;
				if (highest < p->pbm_B.io_space.end + 1)
					highest = p->pbm_B.io_space.end + 1;
			}
			space_size = highest - lowest;
		} else {
			if (p->pbm_A.mem_space.flags) {
				lowest = p->pbm_A.mem_space.start;
				highest = p->pbm_A.mem_space.end + 1;
			}
			if (p->pbm_B.mem_space.flags) {
				if (lowest > p->pbm_B.mem_space.start)
					lowest = p->pbm_B.mem_space.start;
				if (highest < p->pbm_B.mem_space.end + 1)
					highest = p->pbm_B.mem_space.end + 1;
			}
			space_size = highest - lowest;
		}
	} else {
		if (mmap_state == pci_mmap_io) {
			space_size = (pbm->io_space.end -
				      pbm->io_space.start) + 1;
		} else {
			space_size = (pbm->mem_space.end -
				      pbm->mem_space.start) + 1;
		}
	}

	/* Make sure the request is in range. */
	user_offset = vma->vm_pgoff << PAGE_SHIFT;
	user_size = vma->vm_end - vma->vm_start;

	if (user_offset >= space_size ||
	    (user_offset + user_size) > space_size)
		return -EINVAL;

	if (p->pbms_same_domain) {
		unsigned long lowest = ~0UL;

		if (mmap_state == pci_mmap_io) {
			if (p->pbm_A.io_space.flags)
				lowest = p->pbm_A.io_space.start;
			if (p->pbm_B.io_space.flags &&
			    lowest > p->pbm_B.io_space.start)
				lowest = p->pbm_B.io_space.start;
		} else {
			if (p->pbm_A.mem_space.flags)
				lowest = p->pbm_A.mem_space.start;
			if (p->pbm_B.mem_space.flags &&
			    lowest > p->pbm_B.mem_space.start)
				lowest = p->pbm_B.mem_space.start;
		}
		vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
	} else {
		if (mmap_state == pci_mmap_io) {
			vma->vm_pgoff = (pbm->io_space.start +
					 user_offset) >> PAGE_SHIFT;
		} else {
			vma->vm_pgoff = (pbm->mem_space.start +
					 user_offset) >> PAGE_SHIFT;
		}
	}

	return 0;
}

/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
 * to the 32-bit pci bus offset for DEV requested by the user.
 *
 * Basically, the user finds the base address for his device which he wishes
 * to mmap.  They read the 32-bit value from the config space base register,
 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 *
 * Returns negative error code on failure, zero on success.
 */
static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
				  enum pci_mmap_state mmap_state)
{
	unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
	unsigned long user32 = user_offset & pci_memspace_mask;
	unsigned long largest_base, this_base, addr32;
	int i;

	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
		return __pci_mmap_make_offset_bus(dev, vma, mmap_state);

	/* Figure out which base address this is for. */
	largest_base = 0UL;
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		struct resource *rp = &dev->resource[i];

		/* Active? */
		if (!rp->flags)
			continue;

		/* Same type? */
		if (i == PCI_ROM_RESOURCE) {
			if (mmap_state != pci_mmap_mem)
				continue;
		} else {
			if ((mmap_state == pci_mmap_io &&
			     (rp->flags & IORESOURCE_IO) == 0) ||
			    (mmap_state == pci_mmap_mem &&
			     (rp->flags & IORESOURCE_MEM) == 0))
				continue;
		}

		this_base = rp->start;

		addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;

		if (mmap_state == pci_mmap_io)
			addr32 &= 0xffffff;

		if (addr32 <= user32 && this_base > largest_base)
			largest_base = this_base;
	}

	if (largest_base == 0UL)
		return -EINVAL;

	/* Now construct the final physical address. */
	if (mmap_state == pci_mmap_io)
		vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
	else
		vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);

	return 0;
}

/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
 * mapping.
 */
static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
					    enum pci_mmap_state mmap_state)
{
	vma->vm_flags |= (VM_IO | VM_RESERVED);
}

/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 * device mapping.
 */
static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
					     enum pci_mmap_state mmap_state)
{
	/* Our io_remap_pfn_range takes care of this, do nothing.  */
}

/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
 * for this architecture.  The region in the process to map is described by vm_start
 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
 * The pci device structure is provided so that architectures may make mapping
 * decisions on a per-device or per-bus basis.
 *
 * Returns a negative error code on failure, zero on success.
 */
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state,
			int write_combine)
{
	int ret;

	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
	if (ret < 0)
		return ret;

	__pci_mmap_set_flags(dev, vma, mmap_state);
	__pci_mmap_set_pgprot(dev, vma, mmap_state);

	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	ret = io_remap_pfn_range(vma, vma->vm_start,
				 vma->vm_pgoff,
				 vma->vm_end - vma->vm_start,
				 vma->vm_page_prot);
	if (ret)
		return ret;

	return 0;
}

/* Return the domain nuber for this pci bus */

int pci_domain_nr(struct pci_bus *pbus)
{
	struct pci_pbm_info *pbm = pbus->sysdata;
	int ret;

	if (pbm == NULL || pbm->parent == NULL) {
		ret = -ENXIO;
	} else {
		struct pci_controller_info *p = pbm->parent;

		ret = p->index;
		if (p->pbms_same_domain == 0)
			ret = ((ret << 1) +
			       ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
	}

	return ret;
}
EXPORT_SYMBOL(pci_domain_nr);

#ifdef CONFIG_PCI_MSI
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
	struct pcidev_cookie *pcp = pdev->sysdata;
	struct pci_pbm_info *pbm = pcp->pbm;
	struct pci_controller_info *p = pbm->parent;
	int virt_irq, err;

	if (!pbm->msi_num || !p->setup_msi_irq)
		return -EINVAL;

	err = p->setup_msi_irq(&virt_irq, pdev, desc);
	if (err < 0)
		return err;

	return virt_irq;
}

void arch_teardown_msi_irq(unsigned int virt_irq)
{
	struct msi_desc *entry = get_irq_data(virt_irq);
	struct pci_dev *pdev = entry->dev;
	struct pcidev_cookie *pcp = pdev->sysdata;
	struct pci_pbm_info *pbm = pcp->pbm;
	struct pci_controller_info *p = pbm->parent;

	if (!pbm->msi_num || !p->setup_msi_irq)
		return;

	return p->teardown_msi_irq(virt_irq, pdev);
}
#endif /* !(CONFIG_PCI_MSI) */

#endif /* !(CONFIG_PCI) */
Commit	Line	Data
1da177e4 LT	1	/* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
	2	* pci.c: UltraSparc PCI controller support.
	3	*
	4	* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
	5	* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
	6	* Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
	7	*/
	8
1da177e4 LT	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/string.h>
	12	#include <linux/sched.h>
	13	#include <linux/capability.h>
	14	#include <linux/errno.h>
	15	#include <linux/smp_lock.h>
35a17eb6 DM	16	#include <linux/msi.h>
35a17eb6 DM	17	#include <linux/irq.h>
1da177e4 LT	18	#include <linux/init.h>
	19
	20	#include <asm/uaccess.h>
	21	#include <asm/pbm.h>
	22	#include <asm/pgtable.h>
	23	#include <asm/irq.h>
	24	#include <asm/ebus.h>
	25	#include <asm/isa.h>
e87dc350	26	#include <asm/prom.h>
1da177e4 LT	27
	28	unsigned long pci_memspace_mask = 0xffffffffUL;
	29
	30	#ifndef CONFIG_PCI
	31	/* A "nop" PCI implementation. */
	32	asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
	33	unsigned long off, unsigned long len,
	34	unsigned char *buf)
	35	{
	36	return 0;
	37	}
	38	asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
	39	unsigned long off, unsigned long len,
	40	unsigned char *buf)
	41	{
	42	return 0;
	43	}
	44	#else
	45
	46	/* List of all PCI controllers found in the system. */
	47	struct pci_controller_info *pci_controller_root = NULL;
	48
	49	/* Each PCI controller found gets a unique index. */
	50	int pci_num_controllers = 0;
	51
1da177e4 LT	52	volatile int pci_poke_in_progress;
	53	volatile int pci_poke_cpu = -1;
	54	volatile int pci_poke_faulted;
	55
	56	static DEFINE_SPINLOCK(pci_poke_lock);
	57
	58	void pci_config_read8(u8 addr, u8 ret)
	59	{
	60	unsigned long flags;
	61	u8 byte;
	62
	63	spin_lock_irqsave(&pci_poke_lock, flags);
	64	pci_poke_cpu = smp_processor_id();
	65	pci_poke_in_progress = 1;
	66	pci_poke_faulted = 0;
	67	__asm__ __volatile__("membar #Sync\n\t"
	68	"lduba [%1] %2, %0\n\t"
	69	"membar #Sync"
	70	: "=r" (byte)
	71	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	72	: "memory");
	73	pci_poke_in_progress = 0;
	74	pci_poke_cpu = -1;
	75	if (!pci_poke_faulted)
	76	*ret = byte;
	77	spin_unlock_irqrestore(&pci_poke_lock, flags);
	78	}
	79
	80	void pci_config_read16(u16 addr, u16 ret)
	81	{
	82	unsigned long flags;
	83	u16 word;
	84
	85	spin_lock_irqsave(&pci_poke_lock, flags);
	86	pci_poke_cpu = smp_processor_id();
	87	pci_poke_in_progress = 1;
	88	pci_poke_faulted = 0;
	89	__asm__ __volatile__("membar #Sync\n\t"
	90	"lduha [%1] %2, %0\n\t"
	91	"membar #Sync"
	92	: "=r" (word)
	93	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	94	: "memory");
	95	pci_poke_in_progress = 0;
	96	pci_poke_cpu = -1;
	97	if (!pci_poke_faulted)
	98	*ret = word;
	99	spin_unlock_irqrestore(&pci_poke_lock, flags);
	100	}
	101
	102	void pci_config_read32(u32 addr, u32 ret)
	103	{
	104	unsigned long flags;
	105	u32 dword;
	106
	107	spin_lock_irqsave(&pci_poke_lock, flags);
	108	pci_poke_cpu = smp_processor_id();
	109	pci_poke_in_progress = 1;
	110	pci_poke_faulted = 0;
	111	__asm__ __volatile__("membar #Sync\n\t"
	112	"lduwa [%1] %2, %0\n\t"
	113	"membar #Sync"
	114	: "=r" (dword)
	115	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
116	: "memory");
117	pci_poke_in_progress = 0;
118	pci_poke_cpu = -1;
119	if (!pci_poke_faulted)
120	*ret = dword;
121	spin_unlock_irqrestore(&pci_poke_lock, flags);
122	}
123
124	void pci_config_write8(u8 *addr, u8 val)
125	{
126	unsigned long flags;
127
128	spin_lock_irqsave(&pci_poke_lock, flags);
129	pci_poke_cpu = smp_processor_id();
130	pci_poke_in_progress = 1;
131	pci_poke_faulted = 0;
132	__asm__ __volatile__("membar #Sync\n\t"
133	"stba %0, [%1] %2\n\t"
134	"membar #Sync"
135	: /* no outputs */
136	: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
137	: "memory");
138	pci_poke_in_progress = 0;
139	pci_poke_cpu = -1;
140	spin_unlock_irqrestore(&pci_poke_lock, flags);
141	}
142
143	void pci_config_write16(u16 *addr, u16 val)
144	{
145	unsigned long flags;
146
147	spin_lock_irqsave(&pci_poke_lock, flags);
148	pci_poke_cpu = smp_processor_id();
149	pci_poke_in_progress = 1;
150	pci_poke_faulted = 0;
151	__asm__ __volatile__("membar #Sync\n\t"
152	"stha %0, [%1] %2\n\t"
153	"membar #Sync"
154	: /* no outputs */
155	: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
156	: "memory");
157	pci_poke_in_progress = 0;
158	pci_poke_cpu = -1;
159	spin_unlock_irqrestore(&pci_poke_lock, flags);
160	}
161
162	void pci_config_write32(u32 *addr, u32 val)
163	{
164	unsigned long flags;
165
166	spin_lock_irqsave(&pci_poke_lock, flags);
167	pci_poke_cpu = smp_processor_id();
168	pci_poke_in_progress = 1;
169	pci_poke_faulted = 0;
170	__asm__ __volatile__("membar #Sync\n\t"
171	"stwa %0, [%1] %2\n\t"
172	"membar #Sync"
173	: /* no outputs */
174	: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
175	: "memory");
176	pci_poke_in_progress = 0;
177	pci_poke_cpu = -1;
178	spin_unlock_irqrestore(&pci_poke_lock, flags);
179	}
180
181	/* Probe for all PCI controllers in the system. */
e87dc350 DM	182	extern void sabre_init(struct device_node , const char );
	183	extern void psycho_init(struct device_node , const char );
	184	extern void schizo_init(struct device_node , const char );
	185	extern void schizo_plus_init(struct device_node , const char );
	186	extern void tomatillo_init(struct device_node , const char );
	187	extern void sun4v_pci_init(struct device_node , const char );
1da177e4 LT	188
	189	static struct {
	190	char *model_name;
e87dc350	191	void (init)(struct device_node , const char *);
1da177e4 LT	192	} pci_controller_table[] __initdata = {
	193	{ "SUNW,sabre", sabre_init },
	194	{ "pci108e,a000", sabre_init },
	195	{ "pci108e,a001", sabre_init },
	196	{ "SUNW,psycho", psycho_init },
	197	{ "pci108e,8000", psycho_init },
	198	{ "SUNW,schizo", schizo_init },
	199	{ "pci108e,8001", schizo_init },
	200	{ "SUNW,schizo+", schizo_plus_init },
	201	{ "pci108e,8002", schizo_plus_init },
	202	{ "SUNW,tomatillo", tomatillo_init },
	203	{ "pci108e,a801", tomatillo_init },
8f6a93a1	204	{ "SUNW,sun4v-pci", sun4v_pci_init },
1da177e4 LT	205	};
	206	#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
	207	sizeof(pci_controller_table[0]))
	208
e87dc350	209	static int __init pci_controller_init(const char model_name, int namelen, struct device_node dp)
1da177e4 LT	210	{
	211	int i;
	212
	213	for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
	214	if (!strncmp(model_name,
	215	pci_controller_table[i].model_name,
	216	namelen)) {
e87dc350	217	pci_controller_table[i].init(dp, model_name);
1da177e4 LT	218	return 1;
	219	}
	220	}
1da177e4 LT	221
	222	return 0;
	223	}
	224
e87dc350	225	static int __init pci_is_controller(const char model_name, int namelen, struct device_node dp)
1da177e4 LT	226	{
	227	int i;
	228
	229	for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
	230	if (!strncmp(model_name,
	231	pci_controller_table[i].model_name,
	232	namelen)) {
	233	return 1;
	234	}
	235	}
	236	return 0;
	237	}
	238
e87dc350	239	static int __init pci_controller_scan(int (handler)(const char , int, struct device_node *))
1da177e4	240	{
e87dc350	241	struct device_node *dp;
1da177e4 LT	242	int count = 0;
1da177e4 LT	243
e87dc350 DM	244	for_each_node_by_name(dp, "pci") {
e87dc350 DM	245	struct property *prop;
1da177e4 LT	246	int len;
1da177e4 LT	247
e87dc350 DM	248	prop = of_find_property(dp, "model", &len);
	249	if (!prop)
	250	prop = of_find_property(dp, "compatible", &len);
	251
	252	if (prop) {
	253	const char *model = prop->value;
1da177e4 LT	254	int item_len = 0;
	255
	256	/* Our value may be a multi-valued string in the
	257	* case of some compatible properties. For sanity,
e87dc350 DM	258	* only try the first one.
	259	*/
	260	while (model[item_len] && len) {
1da177e4 LT	261	len--;
	262	item_len++;
	263	}
	264
e87dc350	265	if (handler(model, item_len, dp))
1da177e4 LT	266	count++;
1da177e4 LT	267	}
1da177e4 LT	268	}
	269
	270	return count;
	271	}
	272
	273
	274	/* Is there some PCI controller in the system? */
	275	int __init pcic_present(void)
	276	{
	277	return pci_controller_scan(pci_is_controller);
	278	}
	279
8f6a93a1 DM	280	struct pci_iommu_ops *pci_iommu_ops;
	281	EXPORT_SYMBOL(pci_iommu_ops);
	282
	283	extern struct pci_iommu_ops pci_sun4u_iommu_ops,
	284	pci_sun4v_iommu_ops;
	285
1da177e4 LT	286	/* Find each controller in the system, attach and initialize
	287	* software state structure for each and link into the
	288	* pci_controller_root. Setup the controller enough such
	289	* that bus scanning can be done.
	290	*/
	291	static void __init pci_controller_probe(void)
	292	{
8f6a93a1 DM	293	if (tlb_type == hypervisor)
	294	pci_iommu_ops = &pci_sun4v_iommu_ops;
	295	else
	296	pci_iommu_ops = &pci_sun4u_iommu_ops;
	297
1da177e4 LT	298	printk("PCI: Probing for controllers.\n");
	299
	300	pci_controller_scan(pci_controller_init);
	301	}
	302
	303	static void __init pci_scan_each_controller_bus(void)
	304	{
	305	struct pci_controller_info *p;
	306
	307	for (p = pci_controller_root; p; p = p->next)
	308	p->scan_bus(p);
	309	}
	310
1da177e4 LT	311	extern void power_init(void);
	312
	313	static int __init pcibios_init(void)
	314	{
	315	pci_controller_probe();
	316	if (pci_controller_root == NULL)
	317	return 0;
	318
	319	pci_scan_each_controller_bus();
	320
1da177e4 LT	321	isa_init();
1da177e4 LT	322	ebus_init();
1da177e4 LT	323	power_init();
	324
	325	return 0;
	326	}
	327
	328	subsys_initcall(pcibios_init);
	329
	330	void pcibios_fixup_bus(struct pci_bus *pbus)
	331	{
	332	struct pci_pbm_info *pbm = pbus->sysdata;
	333
	334	/* Generic PCI bus probing sets these to point at
	335	* &io{port,mem}_resouce which is wrong for us.
	336	*/
	337	pbus->resource[0] = &pbm->io_space;
	338	pbus->resource[1] = &pbm->mem_space;
	339	}
	340
085ae41f	341	struct resource pcibios_select_root(struct pci_dev pdev, struct resource *r)
1da177e4 LT	342	{
1da177e4 LT	343	struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f	344	struct resource *root = NULL;
1da177e4	345
085ae41f	346	if (r->flags & IORESOURCE_IO)
1da177e4	347	root = &pbm->io_space;
085ae41f	348	if (r->flags & IORESOURCE_MEM)
1da177e4 LT	349	root = &pbm->mem_space;
1da177e4 LT	350
085ae41f	351	return root;
1da177e4 LT	352	}
	353
	354	void pcibios_update_irq(struct pci_dev *pdev, int irq)
	355	{
	356	}
	357
	358	void pcibios_align_resource(void data, struct resource res,
e31dd6e4	359	resource_size_t size, resource_size_t align)
1da177e4 LT	360	{
	361	}
	362
	363	int pcibios_enable_device(struct pci_dev *pdev, int mask)
	364	{
	365	return 0;
	366	}
	367
	368	void pcibios_resource_to_bus(struct pci_dev pdev, struct pci_bus_region region,
	369	struct resource *res)
	370	{
	371	struct pci_pbm_info *pbm = pdev->bus->sysdata;
	372	struct resource zero_res, *root;
	373
	374	zero_res.start = 0;
	375	zero_res.end = 0;
	376	zero_res.flags = res->flags;
	377
	378	if (res->flags & IORESOURCE_IO)
	379	root = &pbm->io_space;
	380	else
	381	root = &pbm->mem_space;
	382
	383	pbm->parent->resource_adjust(pdev, &zero_res, root);
	384
	385	region->start = res->start - zero_res.start;
	386	region->end = res->end - zero_res.start;
	387	}
5fdfd42e	388	EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4 LT	389
	390	void pcibios_bus_to_resource(struct pci_dev pdev, struct resource res,
	391	struct pci_bus_region *region)
	392	{
	393	struct pci_pbm_info *pbm = pdev->bus->sysdata;
	394	struct resource *root;
	395
	396	res->start = region->start;
	397	res->end = region->end;
	398
	399	if (res->flags & IORESOURCE_IO)
	400	root = &pbm->io_space;
	401	else
	402	root = &pbm->mem_space;
	403
	404	pbm->parent->resource_adjust(pdev, res, root);
	405	}
41290c14	406	EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 LT	407
	408	char * __init pcibios_setup(char *str)
	409	{
1da177e4 LT	410	return str;
	411	}
	412
	413	/* Platform support for /proc/bus/pci/X/Y mmap()s. */
	414
	415	/* If the user uses a host-bridge as the PCI device, he may use
	416	* this to perform a raw mmap() of the I/O or MEM space behind
	417	* that controller.
	418	*
	419	* This can be useful for execution of x86 PCI bios initialization code
	420	* on a PCI card, like the xfree86 int10 stuff does.
	421	*/
	422	static int __pci_mmap_make_offset_bus(struct pci_dev pdev, struct vm_area_struct vma,
	423	enum pci_mmap_state mmap_state)
	424	{
	425	struct pcidev_cookie *pcp = pdev->sysdata;
	426	struct pci_pbm_info *pbm;
	427	struct pci_controller_info *p;
	428	unsigned long space_size, user_offset, user_size;
	429
	430	if (!pcp)
	431	return -ENXIO;
	432	pbm = pcp->pbm;
	433	if (!pbm)
	434	return -ENXIO;
	435
	436	p = pbm->parent;
	437	if (p->pbms_same_domain) {
	438	unsigned long lowest, highest;
	439
	440	lowest = ~0UL; highest = 0UL;
	441	if (mmap_state == pci_mmap_io) {
	442	if (p->pbm_A.io_space.flags) {
	443	lowest = p->pbm_A.io_space.start;
	444	highest = p->pbm_A.io_space.end + 1;
	445	}
	446	if (p->pbm_B.io_space.flags) {
	447	if (lowest > p->pbm_B.io_space.start)
	448	lowest = p->pbm_B.io_space.start;
	449	if (highest < p->pbm_B.io_space.end + 1)
	450	highest = p->pbm_B.io_space.end + 1;
	451	}
	452	space_size = highest - lowest;
	453	} else {
	454	if (p->pbm_A.mem_space.flags) {
	455	lowest = p->pbm_A.mem_space.start;
	456	highest = p->pbm_A.mem_space.end + 1;
	457	}
	458	if (p->pbm_B.mem_space.flags) {
	459	if (lowest > p->pbm_B.mem_space.start)
	460	lowest = p->pbm_B.mem_space.start;
	461	if (highest < p->pbm_B.mem_space.end + 1)
	462	highest = p->pbm_B.mem_space.end + 1;
	463	}
	464	space_size = highest - lowest;
	465	}
	466	} else {
	467	if (mmap_state == pci_mmap_io) {
	468	space_size = (pbm->io_space.end -
	469	pbm->io_space.start) + 1;
	470	} else {
	471	space_size = (pbm->mem_space.end -
	472	pbm->mem_space.start) + 1;
	473	}
474	}
475
476	/* Make sure the request is in range. */
477	user_offset = vma->vm_pgoff << PAGE_SHIFT;
478	user_size = vma->vm_end - vma->vm_start;
479
480	if (user_offset >= space_size \|\|
481	(user_offset + user_size) > space_size)
482	return -EINVAL;
483
484	if (p->pbms_same_domain) {
485	unsigned long lowest = ~0UL;
486
487	if (mmap_state == pci_mmap_io) {
488	if (p->pbm_A.io_space.flags)
489	lowest = p->pbm_A.io_space.start;
490	if (p->pbm_B.io_space.flags &&
491	lowest > p->pbm_B.io_space.start)
492	lowest = p->pbm_B.io_space.start;
493	} else {
494	if (p->pbm_A.mem_space.flags)
495	lowest = p->pbm_A.mem_space.start;
496	if (p->pbm_B.mem_space.flags &&
497	lowest > p->pbm_B.mem_space.start)
498	lowest = p->pbm_B.mem_space.start;
499	}
500	vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
501	} else {
502	if (mmap_state == pci_mmap_io) {
503	vma->vm_pgoff = (pbm->io_space.start +
504	user_offset) >> PAGE_SHIFT;
505	} else {
506	vma->vm_pgoff = (pbm->mem_space.start +
507	user_offset) >> PAGE_SHIFT;
508	}
509	}
510
511	return 0;
512	}
513
514	/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
515	* to the 32-bit pci bus offset for DEV requested by the user.
516	*
517	* Basically, the user finds the base address for his device which he wishes
518	* to mmap. They read the 32-bit value from the config space base register,
519	* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
520	* offset parameter of mmap on /proc/bus/pci/XXX for that device.
521	*
522	* Returns negative error code on failure, zero on success.
523	*/
524	static int __pci_mmap_make_offset(struct pci_dev dev, struct vm_area_struct vma,
525	enum pci_mmap_state mmap_state)
526	{
527	unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
528	unsigned long user32 = user_offset & pci_memspace_mask;
529	unsigned long largest_base, this_base, addr32;
530	int i;
531
532	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
533	return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
534
535	/* Figure out which base address this is for. */
536	largest_base = 0UL;
537	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
538	struct resource *rp = &dev->resource[i];
539
540	/* Active? */
541	if (!rp->flags)
542	continue;
543
544	/* Same type? */
545	if (i == PCI_ROM_RESOURCE) {
546	if (mmap_state != pci_mmap_mem)
547	continue;
548	} else {
549	if ((mmap_state == pci_mmap_io &&
550	(rp->flags & IORESOURCE_IO) == 0) \|\|
551	(mmap_state == pci_mmap_mem &&
552	(rp->flags & IORESOURCE_MEM) == 0))
553	continue;
554	}
555
556	this_base = rp->start;
557
558	addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
559
560	if (mmap_state == pci_mmap_io)
561	addr32 &= 0xffffff;
562
563	if (addr32 <= user32 && this_base > largest_base)
564	largest_base = this_base;
565	}
566
567	if (largest_base == 0UL)
568	return -EINVAL;
569
570	/* Now construct the final physical address. */
571	if (mmap_state == pci_mmap_io)
572	vma->vm_pgoff = (((largest_base & ~0xffffffUL) \| user32) >> PAGE_SHIFT);
573	else
574	vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) \| user32) >> PAGE_SHIFT);
575
576	return 0;
577	}
578
579	/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
580	* mapping.
581	*/
582	static void __pci_mmap_set_flags(struct pci_dev dev, struct vm_area_struct vma,
583	enum pci_mmap_state mmap_state)
584	{
585	vma->vm_flags \|= (VM_IO \| VM_RESERVED);
586	}
587
588	/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
589	* device mapping.
590	*/
591	static void __pci_mmap_set_pgprot(struct pci_dev dev, struct vm_area_struct vma,
592	enum pci_mmap_state mmap_state)
593	{
a7a6cac2	594	/* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4 LT	595	}
	596
	597	/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
	598	* for this architecture. The region in the process to map is described by vm_start
	599	* and vm_end members of VMA, the base physical address is found in vm_pgoff.
	600	* The pci device structure is provided so that architectures may make mapping
	601	* decisions on a per-device or per-bus basis.
	602	*
	603	* Returns a negative error code on failure, zero on success.
	604	*/
	605	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	606	enum pci_mmap_state mmap_state,
	607	int write_combine)
	608	{
	609	int ret;
	610
	611	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
	612	if (ret < 0)
	613	return ret;
	614
	615	__pci_mmap_set_flags(dev, vma, mmap_state);
	616	__pci_mmap_set_pgprot(dev, vma, mmap_state);
	617
14778d90	618	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4 LT	619	ret = io_remap_pfn_range(vma, vma->vm_start,
	620	vma->vm_pgoff,
	621	vma->vm_end - vma->vm_start,
	622	vma->vm_page_prot);
	623	if (ret)
	624	return ret;
	625
1da177e4 LT	626	return 0;
	627	}
	628
	629	/* Return the domain nuber for this pci bus */
	630
	631	int pci_domain_nr(struct pci_bus *pbus)
	632	{
	633	struct pci_pbm_info *pbm = pbus->sysdata;
	634	int ret;
	635
	636	if (pbm == NULL \|\| pbm->parent == NULL) {
	637	ret = -ENXIO;
	638	} else {
	639	struct pci_controller_info *p = pbm->parent;
	640
	641	ret = p->index;
	642	if (p->pbms_same_domain == 0)
	643	ret = ((ret << 1) +
	644	((pbm == &pbm->parent->pbm_B) ? 1 : 0));
	645	}
	646
	647	return ret;
	648	}
	649	EXPORT_SYMBOL(pci_domain_nr);
	650
35a17eb6 DM	651	#ifdef CONFIG_PCI_MSI
	652	int arch_setup_msi_irq(struct pci_dev pdev, struct msi_desc desc)
	653	{
	654	struct pcidev_cookie *pcp = pdev->sysdata;
	655	struct pci_pbm_info *pbm = pcp->pbm;
	656	struct pci_controller_info *p = pbm->parent;
	657	int virt_irq, err;
	658
	659	if (!pbm->msi_num \|\| !p->setup_msi_irq)
	660	return -EINVAL;
	661
	662	err = p->setup_msi_irq(&virt_irq, pdev, desc);
	663	if (err < 0)
	664	return err;
	665
	666	return virt_irq;
	667	}
	668
	669	void arch_teardown_msi_irq(unsigned int virt_irq)
	670	{
	671	struct msi_desc *entry = get_irq_data(virt_irq);
	672	struct pci_dev *pdev = entry->dev;
	673	struct pcidev_cookie *pcp = pdev->sysdata;
	674	struct pci_pbm_info *pbm = pcp->pbm;
	675	struct pci_controller_info *p = pbm->parent;
	676
	677	if (!pbm->msi_num \|\| !p->setup_msi_irq)
	678	return;
	679
	680	return p->teardown_msi_irq(virt_irq, pdev);
	681	}
	682	#endif /* !(CONFIG_PCI_MSI) */
	683
1da177e4	684	#endif /* !(CONFIG_PCI) */