Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/smp_lock.h> | |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | ||
22 | #include <asm/uaccess.h> | |
23 | #include <asm/pbm.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/irq.h> | |
26 | #include <asm/ebus.h> | |
27 | #include <asm/isa.h> | |
e87dc350 | 28 | #include <asm/prom.h> |
01f94c4a | 29 | #include <asm/apb.h> |
1da177e4 | 30 | |
1e8a8cc5 DM |
31 | #include "pci_impl.h" |
32 | ||
1da177e4 LT |
33 | unsigned long pci_memspace_mask = 0xffffffffUL; |
34 | ||
35 | #ifndef CONFIG_PCI | |
36 | /* A "nop" PCI implementation. */ | |
37 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
38 | unsigned long off, unsigned long len, | |
39 | unsigned char *buf) | |
40 | { | |
41 | return 0; | |
42 | } | |
43 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
44 | unsigned long off, unsigned long len, | |
45 | unsigned char *buf) | |
46 | { | |
47 | return 0; | |
48 | } | |
49 | #else | |
50 | ||
51 | /* List of all PCI controllers found in the system. */ | |
52 | struct pci_controller_info *pci_controller_root = NULL; | |
53 | ||
54 | /* Each PCI controller found gets a unique index. */ | |
55 | int pci_num_controllers = 0; | |
56 | ||
1da177e4 LT |
57 | volatile int pci_poke_in_progress; |
58 | volatile int pci_poke_cpu = -1; | |
59 | volatile int pci_poke_faulted; | |
60 | ||
61 | static DEFINE_SPINLOCK(pci_poke_lock); | |
62 | ||
63 | void pci_config_read8(u8 *addr, u8 *ret) | |
64 | { | |
65 | unsigned long flags; | |
66 | u8 byte; | |
67 | ||
68 | spin_lock_irqsave(&pci_poke_lock, flags); | |
69 | pci_poke_cpu = smp_processor_id(); | |
70 | pci_poke_in_progress = 1; | |
71 | pci_poke_faulted = 0; | |
72 | __asm__ __volatile__("membar #Sync\n\t" | |
73 | "lduba [%1] %2, %0\n\t" | |
74 | "membar #Sync" | |
75 | : "=r" (byte) | |
76 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
77 | : "memory"); | |
78 | pci_poke_in_progress = 0; | |
79 | pci_poke_cpu = -1; | |
80 | if (!pci_poke_faulted) | |
81 | *ret = byte; | |
82 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
83 | } | |
84 | ||
85 | void pci_config_read16(u16 *addr, u16 *ret) | |
86 | { | |
87 | unsigned long flags; | |
88 | u16 word; | |
89 | ||
90 | spin_lock_irqsave(&pci_poke_lock, flags); | |
91 | pci_poke_cpu = smp_processor_id(); | |
92 | pci_poke_in_progress = 1; | |
93 | pci_poke_faulted = 0; | |
94 | __asm__ __volatile__("membar #Sync\n\t" | |
95 | "lduha [%1] %2, %0\n\t" | |
96 | "membar #Sync" | |
97 | : "=r" (word) | |
98 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
99 | : "memory"); | |
100 | pci_poke_in_progress = 0; | |
101 | pci_poke_cpu = -1; | |
102 | if (!pci_poke_faulted) | |
103 | *ret = word; | |
104 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
105 | } | |
106 | ||
107 | void pci_config_read32(u32 *addr, u32 *ret) | |
108 | { | |
109 | unsigned long flags; | |
110 | u32 dword; | |
111 | ||
112 | spin_lock_irqsave(&pci_poke_lock, flags); | |
113 | pci_poke_cpu = smp_processor_id(); | |
114 | pci_poke_in_progress = 1; | |
115 | pci_poke_faulted = 0; | |
116 | __asm__ __volatile__("membar #Sync\n\t" | |
117 | "lduwa [%1] %2, %0\n\t" | |
118 | "membar #Sync" | |
119 | : "=r" (dword) | |
120 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
121 | : "memory"); | |
122 | pci_poke_in_progress = 0; | |
123 | pci_poke_cpu = -1; | |
124 | if (!pci_poke_faulted) | |
125 | *ret = dword; | |
126 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
127 | } | |
128 | ||
129 | void pci_config_write8(u8 *addr, u8 val) | |
130 | { | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&pci_poke_lock, flags); | |
134 | pci_poke_cpu = smp_processor_id(); | |
135 | pci_poke_in_progress = 1; | |
136 | pci_poke_faulted = 0; | |
137 | __asm__ __volatile__("membar #Sync\n\t" | |
138 | "stba %0, [%1] %2\n\t" | |
139 | "membar #Sync" | |
140 | : /* no outputs */ | |
141 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
142 | : "memory"); | |
143 | pci_poke_in_progress = 0; | |
144 | pci_poke_cpu = -1; | |
145 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
146 | } | |
147 | ||
148 | void pci_config_write16(u16 *addr, u16 val) | |
149 | { | |
150 | unsigned long flags; | |
151 | ||
152 | spin_lock_irqsave(&pci_poke_lock, flags); | |
153 | pci_poke_cpu = smp_processor_id(); | |
154 | pci_poke_in_progress = 1; | |
155 | pci_poke_faulted = 0; | |
156 | __asm__ __volatile__("membar #Sync\n\t" | |
157 | "stha %0, [%1] %2\n\t" | |
158 | "membar #Sync" | |
159 | : /* no outputs */ | |
160 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
161 | : "memory"); | |
162 | pci_poke_in_progress = 0; | |
163 | pci_poke_cpu = -1; | |
164 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
165 | } | |
166 | ||
167 | void pci_config_write32(u32 *addr, u32 val) | |
168 | { | |
169 | unsigned long flags; | |
170 | ||
171 | spin_lock_irqsave(&pci_poke_lock, flags); | |
172 | pci_poke_cpu = smp_processor_id(); | |
173 | pci_poke_in_progress = 1; | |
174 | pci_poke_faulted = 0; | |
175 | __asm__ __volatile__("membar #Sync\n\t" | |
176 | "stwa %0, [%1] %2\n\t" | |
177 | "membar #Sync" | |
178 | : /* no outputs */ | |
179 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
180 | : "memory"); | |
181 | pci_poke_in_progress = 0; | |
182 | pci_poke_cpu = -1; | |
183 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
184 | } | |
185 | ||
186 | /* Probe for all PCI controllers in the system. */ | |
e87dc350 DM |
187 | extern void sabre_init(struct device_node *, const char *); |
188 | extern void psycho_init(struct device_node *, const char *); | |
189 | extern void schizo_init(struct device_node *, const char *); | |
190 | extern void schizo_plus_init(struct device_node *, const char *); | |
191 | extern void tomatillo_init(struct device_node *, const char *); | |
192 | extern void sun4v_pci_init(struct device_node *, const char *); | |
861fe906 | 193 | extern void fire_pci_init(struct device_node *, const char *); |
1da177e4 LT |
194 | |
195 | static struct { | |
196 | char *model_name; | |
e87dc350 | 197 | void (*init)(struct device_node *, const char *); |
1da177e4 LT |
198 | } pci_controller_table[] __initdata = { |
199 | { "SUNW,sabre", sabre_init }, | |
200 | { "pci108e,a000", sabre_init }, | |
201 | { "pci108e,a001", sabre_init }, | |
202 | { "SUNW,psycho", psycho_init }, | |
203 | { "pci108e,8000", psycho_init }, | |
204 | { "SUNW,schizo", schizo_init }, | |
205 | { "pci108e,8001", schizo_init }, | |
206 | { "SUNW,schizo+", schizo_plus_init }, | |
207 | { "pci108e,8002", schizo_plus_init }, | |
208 | { "SUNW,tomatillo", tomatillo_init }, | |
209 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 210 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
861fe906 | 211 | { "pciex108e,80f0", fire_pci_init }, |
1da177e4 LT |
212 | }; |
213 | #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ | |
214 | sizeof(pci_controller_table[0])) | |
215 | ||
e87dc350 | 216 | static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
217 | { |
218 | int i; | |
219 | ||
220 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
221 | if (!strncmp(model_name, | |
222 | pci_controller_table[i].model_name, | |
223 | namelen)) { | |
e87dc350 | 224 | pci_controller_table[i].init(dp, model_name); |
1da177e4 LT |
225 | return 1; |
226 | } | |
227 | } | |
1da177e4 LT |
228 | |
229 | return 0; | |
230 | } | |
231 | ||
e87dc350 | 232 | static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
233 | { |
234 | int i; | |
235 | ||
236 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
237 | if (!strncmp(model_name, | |
238 | pci_controller_table[i].model_name, | |
239 | namelen)) { | |
240 | return 1; | |
241 | } | |
242 | } | |
243 | return 0; | |
244 | } | |
245 | ||
e87dc350 | 246 | static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *)) |
1da177e4 | 247 | { |
e87dc350 | 248 | struct device_node *dp; |
1da177e4 LT |
249 | int count = 0; |
250 | ||
e87dc350 DM |
251 | for_each_node_by_name(dp, "pci") { |
252 | struct property *prop; | |
1da177e4 LT |
253 | int len; |
254 | ||
e87dc350 DM |
255 | prop = of_find_property(dp, "model", &len); |
256 | if (!prop) | |
257 | prop = of_find_property(dp, "compatible", &len); | |
258 | ||
259 | if (prop) { | |
260 | const char *model = prop->value; | |
1da177e4 LT |
261 | int item_len = 0; |
262 | ||
263 | /* Our value may be a multi-valued string in the | |
264 | * case of some compatible properties. For sanity, | |
e87dc350 DM |
265 | * only try the first one. |
266 | */ | |
267 | while (model[item_len] && len) { | |
1da177e4 LT |
268 | len--; |
269 | item_len++; | |
270 | } | |
271 | ||
e87dc350 | 272 | if (handler(model, item_len, dp)) |
1da177e4 LT |
273 | count++; |
274 | } | |
1da177e4 LT |
275 | } |
276 | ||
277 | return count; | |
278 | } | |
279 | ||
280 | ||
281 | /* Is there some PCI controller in the system? */ | |
282 | int __init pcic_present(void) | |
283 | { | |
284 | return pci_controller_scan(pci_is_controller); | |
285 | } | |
286 | ||
c6e87566 | 287 | const struct pci_iommu_ops *pci_iommu_ops; |
8f6a93a1 DM |
288 | EXPORT_SYMBOL(pci_iommu_ops); |
289 | ||
c6e87566 | 290 | extern const struct pci_iommu_ops pci_sun4u_iommu_ops, |
8f6a93a1 DM |
291 | pci_sun4v_iommu_ops; |
292 | ||
1da177e4 LT |
293 | /* Find each controller in the system, attach and initialize |
294 | * software state structure for each and link into the | |
295 | * pci_controller_root. Setup the controller enough such | |
296 | * that bus scanning can be done. | |
297 | */ | |
298 | static void __init pci_controller_probe(void) | |
299 | { | |
8f6a93a1 DM |
300 | if (tlb_type == hypervisor) |
301 | pci_iommu_ops = &pci_sun4v_iommu_ops; | |
302 | else | |
303 | pci_iommu_ops = &pci_sun4u_iommu_ops; | |
304 | ||
1da177e4 LT |
305 | printk("PCI: Probing for controllers.\n"); |
306 | ||
307 | pci_controller_scan(pci_controller_init); | |
308 | } | |
309 | ||
a2fb23af DM |
310 | static unsigned long pci_parse_of_flags(u32 addr0) |
311 | { | |
312 | unsigned long flags = 0; | |
313 | ||
314 | if (addr0 & 0x02000000) { | |
315 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
316 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
317 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
318 | if (addr0 & 0x40000000) | |
319 | flags |= IORESOURCE_PREFETCH | |
320 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
321 | } else if (addr0 & 0x01000000) | |
322 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
323 | return flags; | |
324 | } | |
325 | ||
326 | /* The of_device layer has translated all of the assigned-address properties | |
327 | * into physical address resources, we only have to figure out the register | |
328 | * mapping. | |
329 | */ | |
330 | static void pci_parse_of_addrs(struct of_device *op, | |
331 | struct device_node *node, | |
332 | struct pci_dev *dev) | |
333 | { | |
334 | struct resource *op_res; | |
335 | const u32 *addrs; | |
336 | int proplen; | |
337 | ||
338 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
339 | if (!addrs) | |
340 | return; | |
341 | printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs); | |
342 | op_res = &op->resource[0]; | |
343 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
344 | struct resource *res; | |
345 | unsigned long flags; | |
346 | int i; | |
347 | ||
348 | flags = pci_parse_of_flags(addrs[0]); | |
349 | if (!flags) | |
350 | continue; | |
351 | i = addrs[0] & 0xff; | |
352 | printk(" start: %lx, end: %lx, i: %x\n", | |
353 | op_res->start, op_res->end, i); | |
354 | ||
355 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
356 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
357 | } else if (i == dev->rom_base_reg) { | |
358 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
359 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
360 | } else { | |
361 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
362 | continue; | |
363 | } | |
364 | res->start = op_res->start; | |
365 | res->end = op_res->end; | |
366 | res->flags = flags; | |
367 | res->name = pci_name(dev); | |
368 | } | |
369 | } | |
370 | ||
371 | struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, | |
372 | struct device_node *node, | |
97b3cf05 DM |
373 | struct pci_bus *bus, int devfn, |
374 | int host_controller) | |
a2fb23af DM |
375 | { |
376 | struct dev_archdata *sd; | |
377 | struct pci_dev *dev; | |
378 | const char *type; | |
01f94c4a | 379 | u32 class; |
a2fb23af DM |
380 | |
381 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
382 | if (!dev) | |
383 | return NULL; | |
384 | ||
385 | sd = &dev->dev.archdata; | |
386 | sd->iommu = pbm->iommu; | |
387 | sd->stc = &pbm->stc; | |
388 | sd->host_controller = pbm; | |
389 | sd->prom_node = node; | |
390 | sd->op = of_find_device_by_node(node); | |
391 | sd->msi_num = 0xffffffff; | |
392 | ||
393 | type = of_get_property(node, "device_type", NULL); | |
394 | if (type == NULL) | |
395 | type = ""; | |
396 | ||
28f57e77 DM |
397 | printk(" create device, devfn: %x, type: %s hostcontroller(%d)\n", |
398 | devfn, type, host_controller); | |
a2fb23af DM |
399 | |
400 | dev->bus = bus; | |
401 | dev->sysdata = node; | |
402 | dev->dev.parent = bus->bridge; | |
403 | dev->dev.bus = &pci_bus_type; | |
404 | dev->devfn = devfn; | |
405 | dev->multifunction = 0; /* maybe a lie? */ | |
406 | ||
97b3cf05 DM |
407 | if (host_controller) { |
408 | dev->vendor = 0x108e; | |
409 | dev->device = 0x8000; | |
410 | dev->subsystem_vendor = 0x0000; | |
411 | dev->subsystem_device = 0x0000; | |
412 | dev->cfg_size = 256; | |
28f57e77 DM |
413 | dev->class = PCI_CLASS_BRIDGE_HOST << 8; |
414 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
415 | 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 DM |
416 | } else { |
417 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); | |
418 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
419 | dev->subsystem_vendor = | |
420 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
421 | dev->subsystem_device = | |
422 | of_getintprop_default(node, "subsystem-id", 0); | |
423 | ||
424 | dev->cfg_size = pci_cfg_space_size(dev); | |
01f94c4a | 425 | |
97b3cf05 DM |
426 | /* We can't actually use the firmware value, we have |
427 | * to read what is in the register right now. One | |
428 | * reason is that in the case of IDE interfaces the | |
429 | * firmware can sample the value before the the IDE | |
430 | * interface is programmed into native mode. | |
431 | */ | |
432 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
433 | dev->class = class >> 8; | |
28f57e77 DM |
434 | |
435 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
436 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 | 437 | } |
28f57e77 DM |
438 | printk(" class: 0x%x device name: %s\n", |
439 | dev->class, pci_name(dev)); | |
a2fb23af | 440 | |
861fe906 DM |
441 | /* I have seen IDE devices which will not respond to |
442 | * the bmdma simplex check reads if bus mastering is | |
443 | * disabled. | |
444 | */ | |
445 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
446 | pci_set_master(dev); | |
447 | ||
a2fb23af DM |
448 | dev->current_state = 4; /* unknown power state */ |
449 | dev->error_state = pci_channel_io_normal; | |
450 | ||
97b3cf05 | 451 | if (host_controller) { |
a2fb23af DM |
452 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
453 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
97b3cf05 | 454 | dev->irq = PCI_IRQ_NONE; |
a2fb23af | 455 | } else { |
97b3cf05 DM |
456 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
457 | /* a PCI-PCI bridge */ | |
458 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
459 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
460 | } else if (!strcmp(type, "cardbus")) { | |
461 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
462 | } else { | |
463 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
464 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 465 | |
97b3cf05 DM |
466 | dev->irq = sd->op->irqs[0]; |
467 | if (dev->irq == 0xffffffff) | |
468 | dev->irq = PCI_IRQ_NONE; | |
469 | } | |
a2fb23af | 470 | } |
a2fb23af DM |
471 | pci_parse_of_addrs(sd->op, node, dev); |
472 | ||
473 | printk(" adding to system ...\n"); | |
474 | ||
475 | pci_device_add(dev, bus); | |
476 | ||
477 | return dev; | |
478 | } | |
479 | ||
01f94c4a DM |
480 | static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
481 | { | |
482 | u32 idx, first, last; | |
483 | ||
484 | first = 8; | |
485 | last = 0; | |
486 | for (idx = 0; idx < 8; idx++) { | |
487 | if ((map & (1 << idx)) != 0) { | |
488 | if (first > idx) | |
489 | first = idx; | |
490 | if (last < idx) | |
491 | last = idx; | |
492 | } | |
493 | } | |
494 | ||
495 | *first_p = first; | |
496 | *last_p = last; | |
497 | } | |
498 | ||
0bae5f81 DM |
499 | static void __init pci_resource_adjust(struct resource *res, |
500 | struct resource *root) | |
501 | { | |
502 | res->start += root->start; | |
503 | res->end += root->start; | |
504 | } | |
505 | ||
01f94c4a DM |
506 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
507 | * a proper 'ranges' property. | |
508 | */ | |
509 | static void __init apb_fake_ranges(struct pci_dev *dev, | |
510 | struct pci_bus *bus, | |
511 | struct pci_pbm_info *pbm) | |
512 | { | |
513 | struct resource *res; | |
514 | u32 first, last; | |
515 | u8 map; | |
516 | ||
517 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
518 | apb_calc_first_last(map, &first, &last); | |
519 | res = bus->resource[0]; | |
520 | res->start = (first << 21); | |
521 | res->end = (last << 21) + ((1 << 21) - 1); | |
522 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 523 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
524 | |
525 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
526 | apb_calc_first_last(map, &first, &last); | |
527 | res = bus->resource[1]; | |
528 | res->start = (first << 21); | |
529 | res->end = (last << 21) + ((1 << 21) - 1); | |
530 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 531 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
532 | } |
533 | ||
a2fb23af DM |
534 | static void __init pci_of_scan_bus(struct pci_pbm_info *pbm, |
535 | struct device_node *node, | |
536 | struct pci_bus *bus); | |
537 | ||
538 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
539 | ||
540 | void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, | |
541 | struct device_node *node, | |
542 | struct pci_dev *dev) | |
543 | { | |
544 | struct pci_bus *bus; | |
545 | const u32 *busrange, *ranges; | |
01f94c4a | 546 | int len, i, simba; |
a2fb23af DM |
547 | struct resource *res; |
548 | unsigned int flags; | |
549 | u64 size; | |
550 | ||
551 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
552 | ||
553 | /* parse bus-range property */ | |
554 | busrange = of_get_property(node, "bus-range", &len); | |
555 | if (busrange == NULL || len != 8) { | |
556 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
557 | node->full_name); | |
558 | return; | |
559 | } | |
560 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 561 | simba = 0; |
a2fb23af | 562 | if (ranges == NULL) { |
a165b420 | 563 | const char *model = of_get_property(node, "model", NULL); |
01f94c4a DM |
564 | if (model && !strcmp(model, "SUNW,simba")) { |
565 | simba = 1; | |
566 | } else { | |
567 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", | |
568 | node->full_name); | |
569 | return; | |
570 | } | |
a2fb23af DM |
571 | } |
572 | ||
573 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
574 | if (!bus) { | |
575 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
576 | node->full_name); | |
577 | return; | |
578 | } | |
579 | ||
580 | bus->primary = dev->bus->number; | |
581 | bus->subordinate = busrange[1]; | |
582 | bus->bridge_ctl = 0; | |
583 | ||
01f94c4a | 584 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
585 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
586 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
587 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
588 | res->flags = 0; | |
589 | bus->resource[i] = res; | |
590 | ++res; | |
591 | } | |
01f94c4a DM |
592 | if (simba) { |
593 | apb_fake_ranges(dev, bus, pbm); | |
594 | goto simba_cont; | |
595 | } | |
a2fb23af DM |
596 | i = 1; |
597 | for (; len >= 32; len -= 32, ranges += 8) { | |
598 | struct resource *root; | |
599 | ||
600 | flags = pci_parse_of_flags(ranges[0]); | |
601 | size = GET_64BIT(ranges, 6); | |
602 | if (flags == 0 || size == 0) | |
603 | continue; | |
604 | if (flags & IORESOURCE_IO) { | |
605 | res = bus->resource[0]; | |
606 | if (res->flags) { | |
607 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
608 | " for bridge %s\n", node->full_name); | |
609 | continue; | |
610 | } | |
611 | root = &pbm->io_space; | |
612 | } else { | |
613 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
614 | printk(KERN_ERR "PCI: too many memory ranges" | |
615 | " for bridge %s\n", node->full_name); | |
616 | continue; | |
617 | } | |
618 | res = bus->resource[i]; | |
619 | ++i; | |
620 | root = &pbm->mem_space; | |
621 | } | |
622 | ||
623 | res->start = GET_64BIT(ranges, 1); | |
624 | res->end = res->start + size - 1; | |
625 | res->flags = flags; | |
626 | ||
627 | /* Another way to implement this would be to add an of_device | |
628 | * layer routine that can calculate a resource for a given | |
629 | * range property value in a PCI device. | |
630 | */ | |
0bae5f81 | 631 | pci_resource_adjust(res, root); |
a2fb23af | 632 | } |
01f94c4a | 633 | simba_cont: |
a2fb23af DM |
634 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
635 | bus->number); | |
636 | printk(" bus name: %s\n", bus->name); | |
637 | ||
638 | pci_of_scan_bus(pbm, node, bus); | |
639 | } | |
640 | ||
641 | static void __init pci_of_scan_bus(struct pci_pbm_info *pbm, | |
642 | struct device_node *node, | |
643 | struct pci_bus *bus) | |
644 | { | |
645 | struct device_node *child; | |
646 | const u32 *reg; | |
647 | int reglen, devfn; | |
648 | struct pci_dev *dev; | |
649 | ||
650 | printk("PCI: scan_bus[%s] bus no %d\n", | |
651 | node->full_name, bus->number); | |
652 | ||
653 | child = NULL; | |
654 | while ((child = of_get_next_child(node, child)) != NULL) { | |
655 | printk(" * %s\n", child->full_name); | |
656 | reg = of_get_property(child, "reg", ®len); | |
657 | if (reg == NULL || reglen < 20) | |
658 | continue; | |
659 | devfn = (reg[0] >> 8) & 0xff; | |
660 | ||
661 | /* create a new pci_dev for this device */ | |
97b3cf05 | 662 | dev = of_create_pci_dev(pbm, child, bus, devfn, 0); |
a2fb23af DM |
663 | if (!dev) |
664 | continue; | |
665 | printk("PCI: dev header type: %x\n", dev->hdr_type); | |
666 | ||
667 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
668 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
669 | of_scan_pci_bridge(pbm, child, dev); | |
670 | } | |
671 | } | |
672 | ||
673 | static ssize_t | |
674 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
675 | { | |
676 | struct pci_dev *pdev; | |
677 | struct device_node *dp; | |
678 | ||
679 | pdev = to_pci_dev(dev); | |
680 | dp = pdev->dev.archdata.prom_node; | |
681 | ||
682 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
683 | } | |
684 | ||
685 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
686 | ||
687 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
688 | { | |
689 | struct pci_dev *dev; | |
a378fd0e | 690 | struct pci_bus *child_bus; |
a2fb23af DM |
691 | int err; |
692 | ||
693 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
694 | /* we don't really care if we can create this file or | |
695 | * not, but we need to assign the result of the call | |
696 | * or the world will fall under alien invasion and | |
697 | * everybody will be frozen on a spaceship ready to be | |
698 | * eaten on alpha centauri by some green and jelly | |
699 | * humanoid. | |
700 | */ | |
701 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
702 | } | |
a378fd0e DM |
703 | list_for_each_entry(child_bus, &bus->children, node) |
704 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
705 | } |
706 | ||
97b3cf05 DM |
707 | int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
708 | unsigned int devfn, | |
709 | int where, int size, | |
710 | u32 *value) | |
711 | { | |
712 | static u8 fake_pci_config[] = { | |
713 | 0x8e, 0x10, /* Vendor: 0x108e (Sun) */ | |
714 | 0x00, 0x80, /* Device: 0x8000 (PBM) */ | |
715 | 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */ | |
716 | 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */ | |
717 | 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */ | |
718 | 0x00, /* Cacheline: 0x00 */ | |
719 | 0x40, /* Latency: 0x40 */ | |
720 | 0x00, /* Header-Type: 0x00 normal */ | |
721 | }; | |
722 | ||
723 | *value = 0; | |
724 | if (where >= 0 && where < sizeof(fake_pci_config) && | |
725 | (where + size) >= 0 && | |
726 | (where + size) < sizeof(fake_pci_config) && | |
727 | size <= sizeof(u32)) { | |
728 | while (size--) { | |
729 | *value <<= 8; | |
730 | *value |= fake_pci_config[where + size]; | |
731 | } | |
732 | } | |
733 | ||
734 | return PCIBIOS_SUCCESSFUL; | |
735 | } | |
736 | ||
737 | int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, | |
738 | unsigned int devfn, | |
739 | int where, int size, | |
740 | u32 value) | |
741 | { | |
742 | return PCIBIOS_SUCCESSFUL; | |
743 | } | |
744 | ||
a2fb23af DM |
745 | struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm) |
746 | { | |
747 | struct pci_controller_info *p = pbm->parent; | |
748 | struct device_node *node = pbm->prom_node; | |
97b3cf05 | 749 | struct pci_dev *host_pdev; |
a2fb23af DM |
750 | struct pci_bus *bus; |
751 | ||
752 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
753 | ||
754 | /* XXX parent device? XXX */ | |
755 | bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm); | |
756 | if (!bus) { | |
757 | printk(KERN_ERR "Failed to create bus for %s\n", | |
758 | node->full_name); | |
759 | return NULL; | |
760 | } | |
761 | bus->secondary = pbm->pci_first_busno; | |
762 | bus->subordinate = pbm->pci_last_busno; | |
763 | ||
764 | bus->resource[0] = &pbm->io_space; | |
765 | bus->resource[1] = &pbm->mem_space; | |
766 | ||
97b3cf05 DM |
767 | /* Create the dummy host bridge and link it in. */ |
768 | host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1); | |
769 | bus->self = host_pdev; | |
770 | ||
a2fb23af DM |
771 | pci_of_scan_bus(pbm, node, bus); |
772 | pci_bus_add_devices(bus); | |
773 | pci_bus_register_of_sysfs(bus); | |
774 | ||
775 | return bus; | |
776 | } | |
777 | ||
1da177e4 LT |
778 | static void __init pci_scan_each_controller_bus(void) |
779 | { | |
780 | struct pci_controller_info *p; | |
781 | ||
782 | for (p = pci_controller_root; p; p = p->next) | |
783 | p->scan_bus(p); | |
784 | } | |
785 | ||
1da177e4 LT |
786 | extern void power_init(void); |
787 | ||
788 | static int __init pcibios_init(void) | |
789 | { | |
790 | pci_controller_probe(); | |
791 | if (pci_controller_root == NULL) | |
792 | return 0; | |
793 | ||
794 | pci_scan_each_controller_bus(); | |
795 | ||
1da177e4 LT |
796 | isa_init(); |
797 | ebus_init(); | |
1da177e4 LT |
798 | power_init(); |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | subsys_initcall(pcibios_init); | |
804 | ||
f6b45da1 | 805 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
806 | { |
807 | struct pci_pbm_info *pbm = pbus->sysdata; | |
808 | ||
809 | /* Generic PCI bus probing sets these to point at | |
810 | * &io{port,mem}_resouce which is wrong for us. | |
811 | */ | |
812 | pbus->resource[0] = &pbm->io_space; | |
813 | pbus->resource[1] = &pbm->mem_space; | |
814 | } | |
815 | ||
085ae41f | 816 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
817 | { |
818 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 819 | struct resource *root = NULL; |
1da177e4 | 820 | |
085ae41f | 821 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 822 | root = &pbm->io_space; |
085ae41f | 823 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
824 | root = &pbm->mem_space; |
825 | ||
085ae41f | 826 | return root; |
1da177e4 LT |
827 | } |
828 | ||
829 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
830 | { | |
831 | } | |
832 | ||
833 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 834 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
835 | { |
836 | } | |
837 | ||
a2fb23af | 838 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 839 | { |
a2fb23af DM |
840 | u16 cmd, oldcmd; |
841 | int i; | |
842 | ||
843 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
844 | oldcmd = cmd; | |
845 | ||
846 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
847 | struct resource *res = &dev->resource[i]; | |
848 | ||
849 | /* Only set up the requested stuff */ | |
850 | if (!(mask & (1<<i))) | |
851 | continue; | |
852 | ||
853 | if (res->flags & IORESOURCE_IO) | |
854 | cmd |= PCI_COMMAND_IO; | |
855 | if (res->flags & IORESOURCE_MEM) | |
856 | cmd |= PCI_COMMAND_MEMORY; | |
857 | } | |
858 | ||
859 | if (cmd != oldcmd) { | |
860 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
861 | pci_name(dev), cmd); | |
862 | /* Enable the appropriate bits in the PCI command register. */ | |
863 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
864 | } | |
1da177e4 LT |
865 | return 0; |
866 | } | |
867 | ||
868 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
869 | struct resource *res) | |
870 | { | |
871 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
872 | struct resource zero_res, *root; | |
873 | ||
874 | zero_res.start = 0; | |
875 | zero_res.end = 0; | |
876 | zero_res.flags = res->flags; | |
877 | ||
878 | if (res->flags & IORESOURCE_IO) | |
879 | root = &pbm->io_space; | |
880 | else | |
881 | root = &pbm->mem_space; | |
882 | ||
0bae5f81 | 883 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
884 | |
885 | region->start = res->start - zero_res.start; | |
886 | region->end = res->end - zero_res.start; | |
887 | } | |
5fdfd42e | 888 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
889 | |
890 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
891 | struct pci_bus_region *region) | |
892 | { | |
893 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
894 | struct resource *root; | |
895 | ||
896 | res->start = region->start; | |
897 | res->end = region->end; | |
898 | ||
899 | if (res->flags & IORESOURCE_IO) | |
900 | root = &pbm->io_space; | |
901 | else | |
902 | root = &pbm->mem_space; | |
903 | ||
0bae5f81 | 904 | pci_resource_adjust(res, root); |
1da177e4 | 905 | } |
41290c14 | 906 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 907 | |
f6b45da1 | 908 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 909 | { |
1da177e4 LT |
910 | return str; |
911 | } | |
912 | ||
913 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
914 | ||
915 | /* If the user uses a host-bridge as the PCI device, he may use | |
916 | * this to perform a raw mmap() of the I/O or MEM space behind | |
917 | * that controller. | |
918 | * | |
919 | * This can be useful for execution of x86 PCI bios initialization code | |
920 | * on a PCI card, like the xfree86 int10 stuff does. | |
921 | */ | |
922 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
923 | enum pci_mmap_state mmap_state) | |
924 | { | |
a2fb23af | 925 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
926 | struct pci_controller_info *p; |
927 | unsigned long space_size, user_offset, user_size; | |
928 | ||
1da177e4 | 929 | p = pbm->parent; |
3875c5c0 DM |
930 | if (mmap_state == pci_mmap_io) { |
931 | space_size = (pbm->io_space.end - | |
932 | pbm->io_space.start) + 1; | |
1da177e4 | 933 | } else { |
3875c5c0 DM |
934 | space_size = (pbm->mem_space.end - |
935 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
936 | } |
937 | ||
938 | /* Make sure the request is in range. */ | |
939 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
940 | user_size = vma->vm_end - vma->vm_start; | |
941 | ||
942 | if (user_offset >= space_size || | |
943 | (user_offset + user_size) > space_size) | |
944 | return -EINVAL; | |
945 | ||
3875c5c0 DM |
946 | if (mmap_state == pci_mmap_io) { |
947 | vma->vm_pgoff = (pbm->io_space.start + | |
948 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 949 | } else { |
3875c5c0 DM |
950 | vma->vm_pgoff = (pbm->mem_space.start + |
951 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
952 | } |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
957 | /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding | |
958 | * to the 32-bit pci bus offset for DEV requested by the user. | |
959 | * | |
960 | * Basically, the user finds the base address for his device which he wishes | |
961 | * to mmap. They read the 32-bit value from the config space base register, | |
962 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
963 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
964 | * | |
965 | * Returns negative error code on failure, zero on success. | |
966 | */ | |
967 | static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, | |
968 | enum pci_mmap_state mmap_state) | |
969 | { | |
970 | unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
971 | unsigned long user32 = user_offset & pci_memspace_mask; | |
972 | unsigned long largest_base, this_base, addr32; | |
973 | int i; | |
974 | ||
975 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
976 | return __pci_mmap_make_offset_bus(dev, vma, mmap_state); | |
977 | ||
978 | /* Figure out which base address this is for. */ | |
979 | largest_base = 0UL; | |
980 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
981 | struct resource *rp = &dev->resource[i]; | |
982 | ||
983 | /* Active? */ | |
984 | if (!rp->flags) | |
985 | continue; | |
986 | ||
987 | /* Same type? */ | |
988 | if (i == PCI_ROM_RESOURCE) { | |
989 | if (mmap_state != pci_mmap_mem) | |
990 | continue; | |
991 | } else { | |
992 | if ((mmap_state == pci_mmap_io && | |
993 | (rp->flags & IORESOURCE_IO) == 0) || | |
994 | (mmap_state == pci_mmap_mem && | |
995 | (rp->flags & IORESOURCE_MEM) == 0)) | |
996 | continue; | |
997 | } | |
998 | ||
999 | this_base = rp->start; | |
1000 | ||
1001 | addr32 = (this_base & PAGE_MASK) & pci_memspace_mask; | |
1002 | ||
1003 | if (mmap_state == pci_mmap_io) | |
1004 | addr32 &= 0xffffff; | |
1005 | ||
1006 | if (addr32 <= user32 && this_base > largest_base) | |
1007 | largest_base = this_base; | |
1008 | } | |
1009 | ||
1010 | if (largest_base == 0UL) | |
1011 | return -EINVAL; | |
1012 | ||
1013 | /* Now construct the final physical address. */ | |
1014 | if (mmap_state == pci_mmap_io) | |
1015 | vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT); | |
1016 | else | |
1017 | vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
1023 | * mapping. | |
1024 | */ | |
1025 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
1026 | enum pci_mmap_state mmap_state) | |
1027 | { | |
1028 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
1029 | } | |
1030 | ||
1031 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
1032 | * device mapping. | |
1033 | */ | |
1034 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
1035 | enum pci_mmap_state mmap_state) | |
1036 | { | |
a7a6cac2 | 1037 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
1038 | } |
1039 | ||
1040 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
1041 | * for this architecture. The region in the process to map is described by vm_start | |
1042 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
1043 | * The pci device structure is provided so that architectures may make mapping | |
1044 | * decisions on a per-device or per-bus basis. | |
1045 | * | |
1046 | * Returns a negative error code on failure, zero on success. | |
1047 | */ | |
1048 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1049 | enum pci_mmap_state mmap_state, | |
1050 | int write_combine) | |
1051 | { | |
1052 | int ret; | |
1053 | ||
1054 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
1055 | if (ret < 0) | |
1056 | return ret; | |
1057 | ||
1058 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
1059 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
1060 | ||
14778d90 | 1061 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
1062 | ret = io_remap_pfn_range(vma, vma->vm_start, |
1063 | vma->vm_pgoff, | |
1064 | vma->vm_end - vma->vm_start, | |
1065 | vma->vm_page_prot); | |
1066 | if (ret) | |
1067 | return ret; | |
1068 | ||
1da177e4 LT |
1069 | return 0; |
1070 | } | |
1071 | ||
1072 | /* Return the domain nuber for this pci bus */ | |
1073 | ||
1074 | int pci_domain_nr(struct pci_bus *pbus) | |
1075 | { | |
1076 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1077 | int ret; | |
1078 | ||
1079 | if (pbm == NULL || pbm->parent == NULL) { | |
1080 | ret = -ENXIO; | |
1081 | } else { | |
1082 | struct pci_controller_info *p = pbm->parent; | |
1083 | ||
1084 | ret = p->index; | |
3875c5c0 DM |
1085 | ret = ((ret << 1) + |
1086 | ((pbm == &pbm->parent->pbm_B) ? 1 : 0)); | |
1da177e4 LT |
1087 | } |
1088 | ||
1089 | return ret; | |
1090 | } | |
1091 | EXPORT_SYMBOL(pci_domain_nr); | |
1092 | ||
35a17eb6 DM |
1093 | #ifdef CONFIG_PCI_MSI |
1094 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1095 | { | |
a2fb23af | 1096 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 DM |
1097 | struct pci_controller_info *p = pbm->parent; |
1098 | int virt_irq, err; | |
1099 | ||
1100 | if (!pbm->msi_num || !p->setup_msi_irq) | |
1101 | return -EINVAL; | |
1102 | ||
1103 | err = p->setup_msi_irq(&virt_irq, pdev, desc); | |
7fe3730d | 1104 | if (err) |
35a17eb6 DM |
1105 | return err; |
1106 | ||
7fe3730d | 1107 | return 0; |
35a17eb6 DM |
1108 | } |
1109 | ||
1110 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1111 | { | |
abfd336c | 1112 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1113 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1114 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 DM |
1115 | struct pci_controller_info *p = pbm->parent; |
1116 | ||
1117 | if (!pbm->msi_num || !p->setup_msi_irq) | |
1118 | return; | |
1119 | ||
1120 | return p->teardown_msi_irq(virt_irq, pdev); | |
1121 | } | |
1122 | #endif /* !(CONFIG_PCI_MSI) */ | |
1123 | ||
f6d0f9ea DM |
1124 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1125 | { | |
a2fb23af | 1126 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1127 | } |
1128 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1129 | ||
1da177e4 | 1130 | #endif /* !(CONFIG_PCI) */ |