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[SPARC64]: Kill PBM intmap software state.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_psycho.c
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9fd8b647 1/* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14
15#include <asm/pbm.h>
16#include <asm/iommu.h>
17#include <asm/irq.h>
18#include <asm/starfire.h>
e87dc350 19#include <asm/prom.h>
2b1e5978 20#include <asm/of_device.h>
1da177e4
LT		 21
22#include "pci_impl.h"
23#include "iommu_common.h"
24
25/* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29#define psycho_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44/* Misc. PSYCHO PCI controller register offsets and definitions. */
45#define PSYCHO_CONTROL 0x0010UL
46#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55#define PSYCHO_PCIA_CTRL 0x2000UL
56#define PSYCHO_PCIB_CTRL 0x4000UL
57#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69
70/* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78#define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89{
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95}
96
97static int psycho_out_of_range(struct pci_pbm_info *pbm,
98 unsigned char bus,
99 unsigned char devfn)
100{
101 return ((pbm->parent == 0) ||
102 ((pbm == &pbm->parent->pbm_B) &&
103 (bus == pbm->pci_first_busno) &&
104 PCI_SLOT(devfn) > 8) ||
105 ((pbm == &pbm->parent->pbm_A) &&
106 (bus == pbm->pci_first_busno) &&
107 PCI_SLOT(devfn) > 8));
108}
109
110/* PSYCHO PCI configuration space accessors. */
111
112static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
113 int where, int size, u32 *value)
114{
115 struct pci_pbm_info *pbm = bus_dev->sysdata;
116 unsigned char bus = bus_dev->number;
117 u32 *addr;
118 u16 tmp16;
119 u8 tmp8;
120
121 switch (size) {
122 case 1:
123 *value = 0xff;
124 break;
125 case 2:
126 *value = 0xffff;
127 break;
128 case 4:
129 *value = 0xffffffff;
130 break;
131 }
132
133 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
134 if (!addr)
135 return PCIBIOS_SUCCESSFUL;
136
137 if (psycho_out_of_range(pbm, bus, devfn))
138 return PCIBIOS_SUCCESSFUL;
139 switch (size) {
140 case 1:
141 pci_config_read8((u8 *)addr, &tmp8);
142 *value = (u32) tmp8;
143 break;
144
145 case 2:
146 if (where & 0x01) {
147 printk("pci_read_config_word: misaligned reg [%x]\n",
148 where);
149 return PCIBIOS_SUCCESSFUL;
150 }
151 pci_config_read16((u16 *)addr, &tmp16);
152 *value = (u32) tmp16;
153 break;
154
155 case 4:
156 if (where & 0x03) {
157 printk("pci_read_config_dword: misaligned reg [%x]\n",
158 where);
159 return PCIBIOS_SUCCESSFUL;
160 }
161 pci_config_read32(addr, value);
162 break;
163 }
164 return PCIBIOS_SUCCESSFUL;
165}
166
167static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
168 int where, int size, u32 value)
169{
170 struct pci_pbm_info *pbm = bus_dev->sysdata;
171 unsigned char bus = bus_dev->number;
172 u32 *addr;
173
174 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
175 if (!addr)
176 return PCIBIOS_SUCCESSFUL;
177
178 if (psycho_out_of_range(pbm, bus, devfn))
179 return PCIBIOS_SUCCESSFUL;
180
181 switch (size) {
182 case 1:
183 pci_config_write8((u8 *)addr, value);
184 break;
185
186 case 2:
187 if (where & 0x01) {
188 printk("pci_write_config_word: misaligned reg [%x]\n",
189 where);
190 return PCIBIOS_SUCCESSFUL;
191 }
192 pci_config_write16((u16 *)addr, value);
193 break;
194
195 case 4:
196 if (where & 0x03) {
197 printk("pci_write_config_dword: misaligned reg [%x]\n",
198 where);
199 return PCIBIOS_SUCCESSFUL;
200 }
201 pci_config_write32(addr, value);
202 }
203 return PCIBIOS_SUCCESSFUL;
204}
205
206static struct pci_ops psycho_ops = {
207 .read = psycho_read_pci_cfg,
208 .write = psycho_write_pci_cfg,
209};
210
1da177e4
LT		 211/* PSYCHO error handling support. */
212enum psycho_error_type {
213 UE_ERR, CE_ERR, PCI_ERR
214};
215
216/* Helper function of IOMMU error checking, which checks out
217 * the state of the streaming buffers. The IOMMU lock is
218 * held when this is called.
219 *
220 * For the PCI error case we know which PBM (and thus which
221 * streaming buffer) caused the error, but for the uncorrectable
222 * error case we do not. So we always check both streaming caches.
223 */
224#define PSYCHO_STRBUF_CONTROL_A 0x2800UL
225#define PSYCHO_STRBUF_CONTROL_B 0x4800UL
226#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
227#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
228#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
229#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
230#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
231#define PSYCHO_STRBUF_FLUSH_A 0x2808UL
232#define PSYCHO_STRBUF_FLUSH_B 0x4808UL
233#define PSYCHO_STRBUF_FSYNC_A 0x2810UL
234#define PSYCHO_STRBUF_FSYNC_B 0x4810UL
235#define PSYCHO_STC_DATA_A 0xb000UL
236#define PSYCHO_STC_DATA_B 0xc000UL
237#define PSYCHO_STC_ERR_A 0xb400UL
238#define PSYCHO_STC_ERR_B 0xc400UL
239#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
240#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
241#define PSYCHO_STC_TAG_A 0xb800UL
242#define PSYCHO_STC_TAG_B 0xc800UL
243#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
244#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
245#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
246#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
247#define PSYCHO_STC_LINE_A 0xb900UL
248#define PSYCHO_STC_LINE_B 0xc900UL
249#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
250#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
251#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
252#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
253#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
254#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
255
256static DEFINE_SPINLOCK(stc_buf_lock);
257static unsigned long stc_error_buf[128];
258static unsigned long stc_tag_buf[16];
259static unsigned long stc_line_buf[16];
260
261static void __psycho_check_one_stc(struct pci_controller_info *p,
262 struct pci_pbm_info *pbm,
263 int is_pbm_a)
264{
265 struct pci_strbuf *strbuf = &pbm->stc;
266 unsigned long regbase = p->pbm_A.controller_regs;
267 unsigned long err_base, tag_base, line_base;
268 u64 control;
269 int i;
270
271 if (is_pbm_a) {
272 err_base = regbase + PSYCHO_STC_ERR_A;
273 tag_base = regbase + PSYCHO_STC_TAG_A;
274 line_base = regbase + PSYCHO_STC_LINE_A;
275 } else {
276 err_base = regbase + PSYCHO_STC_ERR_B;
277 tag_base = regbase + PSYCHO_STC_TAG_B;
278 line_base = regbase + PSYCHO_STC_LINE_B;
279 }
280
281 spin_lock(&stc_buf_lock);
282
283 /* This is __REALLY__ dangerous. When we put the
284 * streaming buffer into diagnostic mode to probe
285 * it's tags and error status, we _must_ clear all
286 * of the line tag valid bits before re-enabling
287 * the streaming buffer. If any dirty data lives
288 * in the STC when we do this, we will end up
289 * invalidating it before it has a chance to reach
290 * main memory.
291 */
292 control = psycho_read(strbuf->strbuf_control);
293 psycho_write(strbuf->strbuf_control,
294 (control | PSYCHO_STRBUF_CTRL_DENAB));
295 for (i = 0; i < 128; i++) {
296 unsigned long val;
297
298 val = psycho_read(err_base + (i * 8UL));
299 psycho_write(err_base + (i * 8UL), 0UL);
300 stc_error_buf[i] = val;
301 }
302 for (i = 0; i < 16; i++) {
303 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
304 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
305 psycho_write(tag_base + (i * 8UL), 0UL);
306 psycho_write(line_base + (i * 8UL), 0UL);
307 }
308
309 /* OK, state is logged, exit diagnostic mode. */
310 psycho_write(strbuf->strbuf_control, control);
311
312 for (i = 0; i < 16; i++) {
313 int j, saw_error, first, last;
314
315 saw_error = 0;
316 first = i * 8;
317 last = first + 8;
318 for (j = first; j < last; j++) {
319 unsigned long errval = stc_error_buf[j];
320 if (errval != 0) {
321 saw_error++;
322 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
323 p->index,
324 (is_pbm_a ? 'A' : 'B'),
325 j,
326 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
327 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
328 }
329 }
330 if (saw_error != 0) {
331 unsigned long tagval = stc_tag_buf[i];
332 unsigned long lineval = stc_line_buf[i];
333 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
334 p->index,
335 (is_pbm_a ? 'A' : 'B'),
336 i,
337 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
338 (tagval & PSYCHO_STCTAG_VPN),
339 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
340 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
341 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
342 "V(%d)FOFN(%d)]\n",
343 p->index,
344 (is_pbm_a ? 'A' : 'B'),
345 i,
346 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
347 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
348 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
349 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
350 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
351 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
352 }
353 }
354
355 spin_unlock(&stc_buf_lock);
356}
357
358static void __psycho_check_stc_error(struct pci_controller_info *p,
359 unsigned long afsr,
360 unsigned long afar,
361 enum psycho_error_type type)
362{
363 struct pci_pbm_info *pbm;
364
365 pbm = &p->pbm_A;
366 if (pbm->stc.strbuf_enabled)
367 __psycho_check_one_stc(p, pbm, 1);
368
369 pbm = &p->pbm_B;
370 if (pbm->stc.strbuf_enabled)
371 __psycho_check_one_stc(p, pbm, 0);
372}
373
374/* When an Uncorrectable Error or a PCI Error happens, we
375 * interrogate the IOMMU state to see if it is the cause.
376 */
377#define PSYCHO_IOMMU_CONTROL 0x0200UL
378#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
379#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
380#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
381#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
382#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
383#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
384#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
385#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
386#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
387#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
388#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
389#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
390#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
391#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
392#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
393#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
394#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
395#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
396#define PSYCHO_IOMMU_TSBBASE 0x0208UL
397#define PSYCHO_IOMMU_FLUSH 0x0210UL
398#define PSYCHO_IOMMU_TAG 0xa580UL
399#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
400#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
401#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
402#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
403#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
404#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
405#define PSYCHO_IOMMU_DATA 0xa600UL
406#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
407#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
408#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
409static void psycho_check_iommu_error(struct pci_controller_info *p,
410 unsigned long afsr,
411 unsigned long afar,
412 enum psycho_error_type type)
413{
414 struct pci_iommu *iommu = p->pbm_A.iommu;
415 unsigned long iommu_tag[16];
416 unsigned long iommu_data[16];
417 unsigned long flags;
418 u64 control;
419 int i;
420
421 spin_lock_irqsave(&iommu->lock, flags);
422 control = psycho_read(iommu->iommu_control);
423 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
424 char *type_string;
425
426 /* Clear the error encountered bit. */
427 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
428 psycho_write(iommu->iommu_control, control);
429
430 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
431 case 0:
432 type_string = "Protection Error";
433 break;
434 case 1:
435 type_string = "Invalid Error";
436 break;
437 case 2:
438 type_string = "TimeOut Error";
439 break;
440 case 3:
441 default:
442 type_string = "ECC Error";
443 break;
444 };
445 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
446 p->index, type_string);
447
448 /* Put the IOMMU into diagnostic mode and probe
449 * it's TLB for entries with error status.
450 *
451 * It is very possible for another DVMA to occur
452 * while we do this probe, and corrupt the system
453 * further. But we are so screwed at this point
454 * that we are likely to crash hard anyways, so
455 * get as much diagnostic information to the
456 * console as we can.
457 */
458 psycho_write(iommu->iommu_control,
459 control | PSYCHO_IOMMU_CTRL_DENAB);
460 for (i = 0; i < 16; i++) {
461 unsigned long base = p->pbm_A.controller_regs;
462
463 iommu_tag[i] =
464 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
465 iommu_data[i] =
466 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
467
468 /* Now clear out the entry. */
469 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
470 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
471 }
472
473 /* Leave diagnostic mode. */
474 psycho_write(iommu->iommu_control, control);
475
476 for (i = 0; i < 16; i++) {
477 unsigned long tag, data;
478
479 tag = iommu_tag[i];
480 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
481 continue;
482
483 data = iommu_data[i];
484 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
485 case 0:
486 type_string = "Protection Error";
487 break;
488 case 1:
489 type_string = "Invalid Error";
490 break;
491 case 2:
492 type_string = "TimeOut Error";
493 break;
494 case 3:
495 default:
496 type_string = "ECC Error";
497 break;
498 };
499 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
500 p->index, i, type_string,
501 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
502 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
503 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
504 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
505 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
506 p->index, i,
507 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
508 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
509 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
510 }
511 }
512 __psycho_check_stc_error(p, afsr, afar, type);
513 spin_unlock_irqrestore(&iommu->lock, flags);
514}
515
516/* Uncorrectable Errors. Cause of the error and the address are
517 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
518 * relating to UPA interface transactions.
519 */
520#define PSYCHO_UE_AFSR 0x0030UL
521#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
522#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
523#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
524#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
525#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
526#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
527#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
528#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
529#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
530#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
531#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
532#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
533#define PSYCHO_UE_AFAR 0x0038UL
534
6d24c8dc 535static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
1da177e4
LT		 536{
537 struct pci_controller_info *p = dev_id;
538 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
539 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
540 unsigned long afsr, afar, error_bits;
541 int reported;
542
543 /* Latch uncorrectable error status. */
544 afar = psycho_read(afar_reg);
545 afsr = psycho_read(afsr_reg);
546
547 /* Clear the primary/secondary error status bits. */
548 error_bits = afsr &
549 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
550 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
551 if (!error_bits)
552 return IRQ_NONE;
553 psycho_write(afsr_reg, error_bits);
554
555 /* Log the error. */
556 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
557 p->index,
558 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
559 "PIO" :
560 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
561 "DMA Read" :
562 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
563 "DMA Write" : "???")))));
564 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
565 p->index,
566 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
567 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
568 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
569 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
570 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
571 printk("PSYCHO%d: UE Secondary errors [", p->index);
572 reported = 0;
573 if (afsr & PSYCHO_UEAFSR_SPIO) {
574 reported++;
575 printk("(PIO)");
576 }
577 if (afsr & PSYCHO_UEAFSR_SDRD) {
578 reported++;
579 printk("(DMA Read)");
580 }
581 if (afsr & PSYCHO_UEAFSR_SDWR) {
582 reported++;
583 printk("(DMA Write)");
584 }
585 if (!reported)
586 printk("(none)");
587 printk("]\n");
588
589 /* Interrogate IOMMU for error status. */
590 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
591
592 return IRQ_HANDLED;
593}
594
595/* Correctable Errors. */
596#define PSYCHO_CE_AFSR 0x0040UL
597#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
598#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
599#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
600#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
601#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
602#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
603#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
604#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
605#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
606#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
607#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
608#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
609#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
610#define PSYCHO_CE_AFAR 0x0040UL
611
6d24c8dc 612static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
1da177e4
LT		 613{
614 struct pci_controller_info *p = dev_id;
615 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
616 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
617 unsigned long afsr, afar, error_bits;
618 int reported;
619
620 /* Latch error status. */
621 afar = psycho_read(afar_reg);
622 afsr = psycho_read(afsr_reg);
623
624 /* Clear primary/secondary error status bits. */
625 error_bits = afsr &
626 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
627 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
628 if (!error_bits)
629 return IRQ_NONE;
630 psycho_write(afsr_reg, error_bits);
631
632 /* Log the error. */
633 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
634 p->index,
635 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
636 "PIO" :
637 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
638 "DMA Read" :
639 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
640 "DMA Write" : "???")))));
641
642 /* XXX Use syndrome and afar to print out module string just like
643 * XXX UDB CE trap handler does... -DaveM
644 */
645 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
646 "UPA_MID[%02lx] was_block(%d)\n",
647 p->index,
648 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
649 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
650 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
651 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
652 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
653 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
654 printk("PSYCHO%d: CE Secondary errors [", p->index);
655 reported = 0;
656 if (afsr & PSYCHO_CEAFSR_SPIO) {
657 reported++;
658 printk("(PIO)");
659 }
660 if (afsr & PSYCHO_CEAFSR_SDRD) {
661 reported++;
662 printk("(DMA Read)");
663 }
664 if (afsr & PSYCHO_CEAFSR_SDWR) {
665 reported++;
666 printk("(DMA Write)");
667 }
668 if (!reported)
669 printk("(none)");
670 printk("]\n");
671
672 return IRQ_HANDLED;
673}
674
675/* PCI Errors. They are signalled by the PCI bus module since they
676 * are associated with a specific bus segment.
677 */
678#define PSYCHO_PCI_AFSR_A 0x2010UL
679#define PSYCHO_PCI_AFSR_B 0x4010UL
680#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
681#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
682#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
683#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
684#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
685#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
686#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
687#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
688#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
689#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
690#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
691#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
692#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
693#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
694#define PSYCHO_PCI_AFAR_A 0x2018UL
695#define PSYCHO_PCI_AFAR_B 0x4018UL
696
697static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
698{
699 unsigned long csr_reg, csr, csr_error_bits;
700 irqreturn_t ret = IRQ_NONE;
701 u16 stat;
702
703 if (is_pbm_a) {
704 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
705 } else {
706 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
707 }
708 csr = psycho_read(csr_reg);
709 csr_error_bits =
710 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
711 if (csr_error_bits) {
712 /* Clear the errors. */
713 psycho_write(csr_reg, csr);
714
715 /* Log 'em. */
716 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
717 printk("%s: PCI streaming byte hole error asserted.\n",
718 pbm->name);
719 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
720 printk("%s: PCI SERR signal asserted.\n", pbm->name);
721 ret = IRQ_HANDLED;
722 }
723 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
724 if (stat & (PCI_STATUS_PARITY |
725 PCI_STATUS_SIG_TARGET_ABORT |
726 PCI_STATUS_REC_TARGET_ABORT |
727 PCI_STATUS_REC_MASTER_ABORT |
728 PCI_STATUS_SIG_SYSTEM_ERROR)) {
729 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
730 pbm->name, stat);
731 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
732 ret = IRQ_HANDLED;
733 }
734 return ret;
735}
736
6d24c8dc 737static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 738{
739 struct pci_pbm_info *pbm = dev_id;
740 struct pci_controller_info *p = pbm->parent;
741 unsigned long afsr_reg, afar_reg;
742 unsigned long afsr, afar, error_bits;
743 int is_pbm_a, reported;
744
745 is_pbm_a = (pbm == &pbm->parent->pbm_A);
746 if (is_pbm_a) {
747 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
748 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
749 } else {
750 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
751 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
752 }
753
754 /* Latch error status. */
755 afar = psycho_read(afar_reg);
756 afsr = psycho_read(afsr_reg);
757
758 /* Clear primary/secondary error status bits. */
759 error_bits = afsr &
760 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
761 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
762 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
763 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
764 if (!error_bits)
765 return psycho_pcierr_intr_other(pbm, is_pbm_a);
766 psycho_write(afsr_reg, error_bits);
767
768 /* Log the error. */
769 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
770 p->index, (is_pbm_a ? 'A' : 'B'),
771 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
772 "Master Abort" :
773 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
774 "Target Abort" :
775 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
776 "Excessive Retries" :
777 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
778 "Parity Error" : "???"))))));
779 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
780 p->index, (is_pbm_a ? 'A' : 'B'),
781 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
782 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
783 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
784 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
785 p->index, (is_pbm_a ? 'A' : 'B'), afar);
786 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
787 p->index, (is_pbm_a ? 'A' : 'B'));
788 reported = 0;
789 if (afsr & PSYCHO_PCIAFSR_SMA) {
790 reported++;
791 printk("(Master Abort)");
792 }
793 if (afsr & PSYCHO_PCIAFSR_STA) {
794 reported++;
795 printk("(Target Abort)");
796 }
797 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
798 reported++;
799 printk("(Excessive Retries)");
800 }
801 if (afsr & PSYCHO_PCIAFSR_SPERR) {
802 reported++;
803 printk("(Parity Error)");
804 }
805 if (!reported)
806 printk("(none)");
807 printk("]\n");
808
809 /* For the error types shown, scan PBM's PCI bus for devices
810 * which have logged that error type.
811 */
812
813 /* If we see a Target Abort, this could be the result of an
814 * IOMMU translation error of some sort. It is extremely
815 * useful to log this information as usually it indicates
816 * a bug in the IOMMU support code or a PCI device driver.
817 */
818 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
819 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
820 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
821 }
822 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
823 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
824
825 /* For excessive retries, PSYCHO/PBM will abort the device
826 * and there is no way to specifically check for excessive
827 * retries in the config space status registers. So what
828 * we hope is that we'll catch it via the master/target
829 * abort events.
830 */
831
832 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
833 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
834
835 return IRQ_HANDLED;
836}
837
838/* XXX What about PowerFail/PowerManagement??? -DaveM */
839#define PSYCHO_ECC_CTRL 0x0020
840#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
841#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
842#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
085ae41f 843static void psycho_register_error_handlers(struct pci_controller_info *p)
1da177e4
LT		 844{
845 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
2b1e5978 846 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 847 unsigned long base = p->pbm_A.controller_regs;
1da177e4
LT		 848 u64 tmp;
849
2b1e5978
DM		 850 if (!op)
851 return;
1da177e4 852
2b1e5978
DM		 853 /* Psycho interrupt property order is:
854 * 0: PCIERR PBM B INO
855 * 1: UE ERR
856 * 2: CE ERR
857 * 3: POWER FAIL
858 * 4: SPARE HARDWARE
859 * 5: PCIERR PBM A INO
860 */
1da177e4 861
2b1e5978
DM		 862 if (op->num_irqs < 6)
863 return;
1da177e4 864
d356d7f4
TG		 865 request_irq(op->irqs[1], psycho_ue_intr, IRQF_SHARED, "PSYCHO UE", p);
866 request_irq(op->irqs[2], psycho_ce_intr, IRQF_SHARED, "PSYCHO CE", p);
867 request_irq(op->irqs[5], psycho_pcierr_intr, IRQF_SHARED,
2b1e5978 868 "PSYCHO PCIERR-A", &p->pbm_A);
d356d7f4 869 request_irq(op->irqs[0], psycho_pcierr_intr, IRQF_SHARED,
2b1e5978 870 "PSYCHO PCIERR-B", &p->pbm_B);
1da177e4
LT		 871
872 /* Enable UE and CE interrupts for controller. */
873 psycho_write(base + PSYCHO_ECC_CTRL,
874 (PSYCHO_ECCCTRL_EE |
875 PSYCHO_ECCCTRL_UE |
876 PSYCHO_ECCCTRL_CE));
877
878 /* Enable PCI Error interrupts and clear error
879 * bits for each PBM.
880 */
881 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
882 tmp |= (PSYCHO_PCICTRL_SERR |
883 PSYCHO_PCICTRL_SBH_ERR |
884 PSYCHO_PCICTRL_EEN);
885 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
886 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
887
888 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
889 tmp |= (PSYCHO_PCICTRL_SERR |
890 PSYCHO_PCICTRL_SBH_ERR |
891 PSYCHO_PCICTRL_EEN);
892 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
893 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
894}
895
896/* PSYCHO boot time probing and initialization. */
085ae41f
DM		 897static void psycho_resource_adjust(struct pci_dev *pdev,
898 struct resource *res,
899 struct resource *root)
1da177e4
LT		 900{
901 res->start += root->start;
902 res->end += root->start;
903}
904
085ae41f 905static void psycho_base_address_update(struct pci_dev *pdev, int resource)
1da177e4 906{
a2fb23af 907 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 908 struct resource *res, *root;
909 u32 reg;
910 int where, size, is_64bit;
911
912 res = &pdev->resource[resource];
913 if (resource < 6) {
914 where = PCI_BASE_ADDRESS_0 + (resource * 4);
915 } else if (resource == PCI_ROM_RESOURCE) {
916 where = pdev->rom_base_reg;
917 } else {
918 /* Somebody might have asked allocation of a non-standard resource */
919 return;
920 }
921
922 is_64bit = 0;
923 if (res->flags & IORESOURCE_IO)
924 root = &pbm->io_space;
925 else {
926 root = &pbm->mem_space;
927 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
928 == PCI_BASE_ADDRESS_MEM_TYPE_64)
929 is_64bit = 1;
930 }
931
932 size = res->end - res->start;
933 pci_read_config_dword(pdev, where, &reg);
934 reg = ((reg & size) |
935 (((u32)(res->start - root->start)) & ~size));
936 if (resource == PCI_ROM_RESOURCE) {
937 reg |= PCI_ROM_ADDRESS_ENABLE;
938 res->flags |= IORESOURCE_ROM_ENABLE;
939 }
940 pci_write_config_dword(pdev, where, reg);
941
942 /* This knows that the upper 32-bits of the address
943 * must be zero. Our PCI common layer enforces this.
944 */
945 if (is_64bit)
946 pci_write_config_dword(pdev, where + 4, 0);
947}
948
085ae41f 949static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 950{
951 u8 *addr;
952
953 /* Set cache-line size to 64 bytes, this is actually
954 * a nop but I do it for completeness.
955 */
956 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
957 0, PCI_CACHE_LINE_SIZE);
958 pci_config_write8(addr, 64 / sizeof(u32));
959
960 /* Set PBM latency timer to 64 PCI clocks. */
961 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
962 0, PCI_LATENCY_TIMER);
963 pci_config_write8(addr, 64);
964}
965
085ae41f
DM		 966static void pbm_scan_bus(struct pci_controller_info *p,
967 struct pci_pbm_info *pbm)
1da177e4 968{
a2fb23af 969 pbm->pci_bus = pci_scan_one_pbm(pbm);
1da177e4
LT		 970}
971
085ae41f 972static void psycho_scan_bus(struct pci_controller_info *p)
1da177e4
LT		 973{
974 pbm_config_busmastering(&p->pbm_B);
975 p->pbm_B.is_66mhz_capable = 0;
976 pbm_config_busmastering(&p->pbm_A);
977 p->pbm_A.is_66mhz_capable = 1;
978 pbm_scan_bus(p, &p->pbm_B);
979 pbm_scan_bus(p, &p->pbm_A);
980
981 /* After the PCI bus scan is complete, we can register
982 * the error interrupt handlers.
983 */
984 psycho_register_error_handlers(p);
985}
986
085ae41f 987static void psycho_iommu_init(struct pci_controller_info *p)
1da177e4
LT		 988{
989 struct pci_iommu *iommu = p->pbm_A.iommu;
51e85136 990 unsigned long i;
1da177e4
LT		 991 u64 control;
992
1da177e4
LT		 993 /* Register addresses. */
994 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
995 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
996 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
997 /* PSYCHO's IOMMU lacks ctx flushing. */
998 iommu->iommu_ctxflush = 0;
999
1000 /* We use the main control register of PSYCHO as the write
1001 * completion register.
1002 */
1003 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
1004
1005 /*
1006 * Invalidate TLB Entries.
1007 */
1008 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1009 control |= PSYCHO_IOMMU_CTRL_DENAB;
1010 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1011 for(i = 0; i < 16; i++) {
1012 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
1013 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1014 }
1015
1016 /* Leave diag mode enabled for full-flushing done
1017 * in pci_iommu.c
1018 */
51e85136 1019 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1da177e4 1020
51e85136
DM		 1021 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
1022 __pa(iommu->page_table));
1da177e4
LT		 1023
1024 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1025 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
1026 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
1027 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1028
1029 /* If necessary, hook us up for starfire IRQ translations. */
51e85136 1030 if (this_is_starfire)
286bbe87 1031 starfire_hookup(p->pbm_A.portid);
1da177e4
LT		 1032}
1033
1034#define PSYCHO_IRQ_RETRY 0x1a00UL
1035#define PSYCHO_PCIA_DIAG 0x2020UL
1036#define PSYCHO_PCIB_DIAG 0x4020UL
1037#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
1038#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
1039#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
1040#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
1041#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
1042#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
1043#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
1044#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1045
1046static void psycho_controller_hwinit(struct pci_controller_info *p)
1047{
1048 u64 tmp;
1049
864ae180 1050 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1da177e4
LT		 1051
1052 /* Enable arbiter for all PCI slots. */
1053 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1054 tmp |= PSYCHO_PCICTRL_AEN;
1055 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1056
1057 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1058 tmp |= PSYCHO_PCICTRL_AEN;
1059 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1060
1061 /* Disable DMA write / PIO read synchronization on
1062 * both PCI bus segments.
1063 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1064 */
1065 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1066 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1067 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1068
1069 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1070 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1071 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1072}
1073
1da177e4
LT		 1074static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1075 struct pci_pbm_info *pbm,
1076 int is_pbm_a)
1077{
1078 unsigned long base = pbm->controller_regs;
1079 u64 control;
1080
1081 if (is_pbm_a) {
1082 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1083 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1084 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1085 } else {
1086 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1087 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1088 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1089 }
1090 /* PSYCHO's streaming buffer lacks ctx flushing. */
1091 pbm->stc.strbuf_ctxflush = 0;
1092 pbm->stc.strbuf_ctxmatch_base = 0;
1093
1094 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1095 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1096 + 63UL)
1097 & ~63UL);
1098 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1099 __pa(pbm->stc.strbuf_flushflag);
1100
1101 /* Enable the streaming buffer. We have to be careful
1102 * just in case OBP left it with LRU locking enabled.
1103 *
1104 * It is possible to control if PBM will be rerun on
1105 * line misses. Currently I just retain whatever setting
1106 * OBP left us with. All checks so far show it having
1107 * a value of zero.
1108 */
1109#undef PSYCHO_STRBUF_RERUN_ENABLE
1110#undef PSYCHO_STRBUF_RERUN_DISABLE
1111 control = psycho_read(pbm->stc.strbuf_control);
1112 control |= PSYCHO_STRBUF_CTRL_ENAB;
1113 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1114#ifdef PSYCHO_STRBUF_RERUN_ENABLE
1115 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1116#else
1117#ifdef PSYCHO_STRBUF_RERUN_DISABLE
1118 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1119#endif
1120#endif
1121 psycho_write(pbm->stc.strbuf_control, control);
1122
1123 pbm->stc.strbuf_enabled = 1;
1124}
1125
1126#define PSYCHO_IOSPACE_A 0x002000000UL
1127#define PSYCHO_IOSPACE_B 0x002010000UL
1128#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1129#define PSYCHO_MEMSPACE_A 0x100000000UL
1130#define PSYCHO_MEMSPACE_B 0x180000000UL
1131#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1132
1133static void psycho_pbm_init(struct pci_controller_info *p,
e87dc350 1134 struct device_node *dp, int is_pbm_a)
1da177e4 1135{
e87dc350
DM		 1136 unsigned int *busrange;
1137 struct property *prop;
1da177e4 1138 struct pci_pbm_info *pbm;
e87dc350 1139 int len;
1da177e4
LT		 1140
1141 if (is_pbm_a) {
1142 pbm = &p->pbm_A;
1143 pbm->pci_first_slot = 1;
1da177e4
LT		 1144 } else {
1145 pbm = &p->pbm_B;
1146 pbm->pci_first_slot = 2;
1da177e4
LT		 1147 }
1148
1149 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
e87dc350
DM		 1150 pbm->chip_version = 0;
1151 prop = of_find_property(dp, "version#", NULL);
1152 if (prop)
1153 pbm->chip_version = *(int *) prop->value;
1154 pbm->chip_revision = 0;
1155 prop = of_find_property(dp, "module-revision#", NULL);
1156 if (prop)
1157 pbm->chip_revision = *(int *) prop->value;
1da177e4 1158
9fd8b647 1159 pci_determine_mem_io_space(pbm);
1da177e4
LT		 1160
1161 pbm->parent = p;
e87dc350
DM		 1162 pbm->prom_node = dp;
1163 pbm->name = dp->full_name;
1164
1165 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1166 pbm->name,
1167 pbm->chip_version, pbm->chip_revision);
1168
1169 prop = of_find_property(dp, "ranges", &len);
1170 if (prop) {
1171 pbm->pbm_ranges = prop->value;
1da177e4 1172 pbm->num_pbm_ranges =
e87dc350
DM		 1173 (len / sizeof(struct linux_prom_pci_ranges));
1174 } else {
1da177e4 1175 pbm->num_pbm_ranges = 0;
e87dc350 1176 }
1da177e4 1177
e87dc350
DM		 1178 prop = of_find_property(dp, "bus-range", NULL);
1179 busrange = prop->value;
1da177e4
LT		 1180 pbm->pci_first_busno = busrange[0];
1181 pbm->pci_last_busno = busrange[1];
1182
1183 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1184}
1185
1186#define PSYCHO_CONFIGSPACE 0x001000000UL
1187
e87dc350 1188void psycho_init(struct device_node *dp, char *model_name)
1da177e4 1189{
e87dc350 1190 struct linux_prom64_registers *pr_regs;
1da177e4
LT		 1191 struct pci_controller_info *p;
1192 struct pci_iommu *iommu;
e87dc350 1193 struct property *prop;
1da177e4 1194 u32 upa_portid;
e87dc350 1195 int is_pbm_a;
1da177e4 1196
e87dc350
DM		 1197 upa_portid = 0xff;
1198 prop = of_find_property(dp, "upa-portid", NULL);
1199 if (prop)
1200 upa_portid = *(u32 *) prop->value;
1da177e4
LT		 1201
1202 for(p = pci_controller_root; p; p = p->next) {
1203 if (p->pbm_A.portid == upa_portid) {
e87dc350
DM		 1204 is_pbm_a = (p->pbm_A.prom_node == NULL);
1205 psycho_pbm_init(p, dp, is_pbm_a);
1da177e4
LT		 1206 return;
1207 }
1208 }
1209
9132983a 1210 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1da177e4
LT		 1211 if (!p) {
1212 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1213 prom_halt();
1214 }
9132983a 1215 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1da177e4
LT		 1216 if (!iommu) {
1217 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1218 prom_halt();
1219 }
1da177e4
LT		 1220 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1221
1222 p->next = pci_controller_root;
1223 pci_controller_root = p;
1224
1225 p->pbm_A.portid = upa_portid;
1226 p->pbm_B.portid = upa_portid;
1227 p->index = pci_num_controllers++;
1228 p->pbms_same_domain = 0;
1229 p->scan_bus = psycho_scan_bus;
1da177e4
LT		 1230 p->base_address_update = psycho_base_address_update;
1231 p->resource_adjust = psycho_resource_adjust;
1232 p->pci_ops = &psycho_ops;
1233
e87dc350
DM		 1234 prop = of_find_property(dp, "reg", NULL);
1235 pr_regs = prop->value;
1da177e4
LT		 1236
1237 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1238 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1da177e4
LT		 1239
1240 p->pbm_A.config_space = p->pbm_B.config_space =
1241 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1da177e4
LT		 1242
1243 /*
1244 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1245 * we need to adjust our MEM space mask.
1246 */
1247 pci_memspace_mask = 0x7fffffffUL;
1248
1249 psycho_controller_hwinit(p);
1250
1251 psycho_iommu_init(p);
1252
1253 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
e87dc350 1254 psycho_pbm_init(p, dp, is_pbm_a);
1da177e4 1255}
Linux kernel - Deliverables
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