Commit | Line | Data |
---|---|---|
8f6a93a1 DM |
1 | /* pci_sun4v.c: SUN4V specific PCI controller support. |
2 | * | |
9fd8b647 | 3 | * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net) |
8f6a93a1 DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/types.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/interrupt.h> | |
18397944 | 12 | #include <linux/percpu.h> |
35a17eb6 DM |
13 | #include <linux/irq.h> |
14 | #include <linux/msi.h> | |
8f6a93a1 DM |
15 | |
16 | #include <asm/pbm.h> | |
17 | #include <asm/iommu.h> | |
18 | #include <asm/irq.h> | |
19 | #include <asm/upa.h> | |
20 | #include <asm/pstate.h> | |
21 | #include <asm/oplib.h> | |
22 | #include <asm/hypervisor.h> | |
e87dc350 | 23 | #include <asm/prom.h> |
8f6a93a1 DM |
24 | |
25 | #include "pci_impl.h" | |
26 | #include "iommu_common.h" | |
27 | ||
bade5622 DM |
28 | #include "pci_sun4v.h" |
29 | ||
7c8f486a | 30 | #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64)) |
18397944 | 31 | |
6a32fd4d DM |
32 | struct pci_iommu_batch { |
33 | struct pci_dev *pdev; /* Device mapping is for. */ | |
34 | unsigned long prot; /* IOMMU page protections */ | |
35 | unsigned long entry; /* Index into IOTSB. */ | |
36 | u64 *pglist; /* List of physical pages */ | |
37 | unsigned long npages; /* Number of pages in list. */ | |
18397944 DM |
38 | }; |
39 | ||
6a32fd4d DM |
40 | static DEFINE_PER_CPU(struct pci_iommu_batch, pci_iommu_batch); |
41 | ||
42 | /* Interrupts must be disabled. */ | |
43 | static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry) | |
44 | { | |
45 | struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch); | |
46 | ||
47 | p->pdev = pdev; | |
48 | p->prot = prot; | |
49 | p->entry = entry; | |
50 | p->npages = 0; | |
51 | } | |
52 | ||
53 | /* Interrupts must be disabled. */ | |
54 | static long pci_iommu_batch_flush(struct pci_iommu_batch *p) | |
55 | { | |
a2fb23af DM |
56 | struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller; |
57 | unsigned long devhandle = pbm->devhandle; | |
6a32fd4d DM |
58 | unsigned long prot = p->prot; |
59 | unsigned long entry = p->entry; | |
60 | u64 *pglist = p->pglist; | |
61 | unsigned long npages = p->npages; | |
62 | ||
d82965c1 | 63 | while (npages != 0) { |
6a32fd4d DM |
64 | long num; |
65 | ||
66 | num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry), | |
67 | npages, prot, __pa(pglist)); | |
68 | if (unlikely(num < 0)) { | |
69 | if (printk_ratelimit()) | |
70 | printk("pci_iommu_batch_flush: IOMMU map of " | |
71 | "[%08lx:%08lx:%lx:%lx:%lx] failed with " | |
72 | "status %ld\n", | |
73 | devhandle, HV_PCI_TSBID(0, entry), | |
74 | npages, prot, __pa(pglist), num); | |
75 | return -1; | |
76 | } | |
77 | ||
78 | entry += num; | |
79 | npages -= num; | |
80 | pglist += num; | |
d82965c1 | 81 | } |
6a32fd4d DM |
82 | |
83 | p->entry = entry; | |
84 | p->npages = 0; | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
89 | /* Interrupts must be disabled. */ | |
90 | static inline long pci_iommu_batch_add(u64 phys_page) | |
91 | { | |
92 | struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch); | |
93 | ||
94 | BUG_ON(p->npages >= PGLIST_NENTS); | |
95 | ||
96 | p->pglist[p->npages++] = phys_page; | |
97 | if (p->npages == PGLIST_NENTS) | |
98 | return pci_iommu_batch_flush(p); | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
103 | /* Interrupts must be disabled. */ | |
104 | static inline long pci_iommu_batch_end(void) | |
105 | { | |
106 | struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch); | |
107 | ||
108 | BUG_ON(p->npages >= PGLIST_NENTS); | |
109 | ||
110 | return pci_iommu_batch_flush(p); | |
111 | } | |
18397944 DM |
112 | |
113 | static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages) | |
114 | { | |
115 | unsigned long n, i, start, end, limit; | |
116 | int pass; | |
117 | ||
118 | limit = arena->limit; | |
119 | start = arena->hint; | |
120 | pass = 0; | |
121 | ||
122 | again: | |
123 | n = find_next_zero_bit(arena->map, limit, start); | |
124 | end = n + npages; | |
125 | if (unlikely(end >= limit)) { | |
126 | if (likely(pass < 1)) { | |
127 | limit = start; | |
128 | start = 0; | |
129 | pass++; | |
130 | goto again; | |
131 | } else { | |
132 | /* Scanned the whole thing, give up. */ | |
133 | return -1; | |
134 | } | |
135 | } | |
136 | ||
137 | for (i = n; i < end; i++) { | |
138 | if (test_bit(i, arena->map)) { | |
139 | start = i + 1; | |
140 | goto again; | |
141 | } | |
142 | } | |
143 | ||
144 | for (i = n; i < end; i++) | |
145 | __set_bit(i, arena->map); | |
146 | ||
147 | arena->hint = end; | |
148 | ||
149 | return n; | |
150 | } | |
151 | ||
152 | static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages) | |
153 | { | |
154 | unsigned long i; | |
155 | ||
156 | for (i = base; i < (base + npages); i++) | |
157 | __clear_bit(i, arena->map); | |
158 | } | |
159 | ||
42f14237 | 160 | static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp) |
8f6a93a1 | 161 | { |
18397944 | 162 | struct pci_iommu *iommu; |
7c8f486a | 163 | unsigned long flags, order, first_page, npages, n; |
18397944 DM |
164 | void *ret; |
165 | long entry; | |
18397944 DM |
166 | |
167 | size = IO_PAGE_ALIGN(size); | |
168 | order = get_order(size); | |
6a32fd4d | 169 | if (unlikely(order >= MAX_ORDER)) |
18397944 DM |
170 | return NULL; |
171 | ||
172 | npages = size >> IO_PAGE_SHIFT; | |
18397944 | 173 | |
42f14237 | 174 | first_page = __get_free_pages(gfp, order); |
6a32fd4d | 175 | if (unlikely(first_page == 0UL)) |
18397944 | 176 | return NULL; |
e7a0453e | 177 | |
18397944 DM |
178 | memset((char *)first_page, 0, PAGE_SIZE << order); |
179 | ||
a2fb23af | 180 | iommu = pdev->dev.archdata.iommu; |
18397944 DM |
181 | |
182 | spin_lock_irqsave(&iommu->lock, flags); | |
183 | entry = pci_arena_alloc(&iommu->arena, npages); | |
184 | spin_unlock_irqrestore(&iommu->lock, flags); | |
185 | ||
6a32fd4d DM |
186 | if (unlikely(entry < 0L)) |
187 | goto arena_alloc_fail; | |
18397944 DM |
188 | |
189 | *dma_addrp = (iommu->page_table_map_base + | |
190 | (entry << IO_PAGE_SHIFT)); | |
191 | ret = (void *) first_page; | |
192 | first_page = __pa(first_page); | |
193 | ||
6a32fd4d | 194 | local_irq_save(flags); |
18397944 | 195 | |
6a32fd4d DM |
196 | pci_iommu_batch_start(pdev, |
197 | (HV_PCI_MAP_ATTR_READ | | |
198 | HV_PCI_MAP_ATTR_WRITE), | |
199 | entry); | |
18397944 | 200 | |
6a32fd4d DM |
201 | for (n = 0; n < npages; n++) { |
202 | long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE)); | |
203 | if (unlikely(err < 0L)) | |
204 | goto iommu_map_fail; | |
205 | } | |
18397944 | 206 | |
6a32fd4d DM |
207 | if (unlikely(pci_iommu_batch_end() < 0L)) |
208 | goto iommu_map_fail; | |
18397944 | 209 | |
6a32fd4d | 210 | local_irq_restore(flags); |
18397944 DM |
211 | |
212 | return ret; | |
6a32fd4d DM |
213 | |
214 | iommu_map_fail: | |
215 | /* Interrupts are disabled. */ | |
216 | spin_lock(&iommu->lock); | |
217 | pci_arena_free(&iommu->arena, entry, npages); | |
218 | spin_unlock_irqrestore(&iommu->lock, flags); | |
219 | ||
220 | arena_alloc_fail: | |
221 | free_pages(first_page, order); | |
222 | return NULL; | |
8f6a93a1 DM |
223 | } |
224 | ||
225 | static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma) | |
226 | { | |
a2fb23af | 227 | struct pci_pbm_info *pbm; |
18397944 | 228 | struct pci_iommu *iommu; |
7c8f486a DM |
229 | unsigned long flags, order, npages, entry; |
230 | u32 devhandle; | |
18397944 DM |
231 | |
232 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
a2fb23af DM |
233 | iommu = pdev->dev.archdata.iommu; |
234 | pbm = pdev->dev.archdata.host_controller; | |
235 | devhandle = pbm->devhandle; | |
18397944 DM |
236 | entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); |
237 | ||
238 | spin_lock_irqsave(&iommu->lock, flags); | |
239 | ||
240 | pci_arena_free(&iommu->arena, entry, npages); | |
241 | ||
242 | do { | |
243 | unsigned long num; | |
244 | ||
245 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
246 | npages); | |
247 | entry += num; | |
248 | npages -= num; | |
249 | } while (npages != 0); | |
250 | ||
251 | spin_unlock_irqrestore(&iommu->lock, flags); | |
252 | ||
253 | order = get_order(size); | |
254 | if (order < 10) | |
255 | free_pages((unsigned long)cpu, order); | |
8f6a93a1 DM |
256 | } |
257 | ||
258 | static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction) | |
259 | { | |
18397944 DM |
260 | struct pci_iommu *iommu; |
261 | unsigned long flags, npages, oaddr; | |
7c8f486a | 262 | unsigned long i, base_paddr; |
6a32fd4d | 263 | u32 bus_addr, ret; |
18397944 DM |
264 | unsigned long prot; |
265 | long entry; | |
18397944 | 266 | |
a2fb23af | 267 | iommu = pdev->dev.archdata.iommu; |
18397944 DM |
268 | |
269 | if (unlikely(direction == PCI_DMA_NONE)) | |
270 | goto bad; | |
271 | ||
272 | oaddr = (unsigned long)ptr; | |
273 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); | |
274 | npages >>= IO_PAGE_SHIFT; | |
18397944 DM |
275 | |
276 | spin_lock_irqsave(&iommu->lock, flags); | |
277 | entry = pci_arena_alloc(&iommu->arena, npages); | |
278 | spin_unlock_irqrestore(&iommu->lock, flags); | |
279 | ||
280 | if (unlikely(entry < 0L)) | |
281 | goto bad; | |
282 | ||
283 | bus_addr = (iommu->page_table_map_base + | |
284 | (entry << IO_PAGE_SHIFT)); | |
285 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
286 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
287 | prot = HV_PCI_MAP_ATTR_READ; | |
288 | if (direction != PCI_DMA_TODEVICE) | |
289 | prot |= HV_PCI_MAP_ATTR_WRITE; | |
290 | ||
6a32fd4d | 291 | local_irq_save(flags); |
18397944 | 292 | |
6a32fd4d | 293 | pci_iommu_batch_start(pdev, prot, entry); |
18397944 | 294 | |
6a32fd4d DM |
295 | for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) { |
296 | long err = pci_iommu_batch_add(base_paddr); | |
297 | if (unlikely(err < 0L)) | |
298 | goto iommu_map_fail; | |
299 | } | |
300 | if (unlikely(pci_iommu_batch_end() < 0L)) | |
301 | goto iommu_map_fail; | |
18397944 | 302 | |
6a32fd4d | 303 | local_irq_restore(flags); |
18397944 DM |
304 | |
305 | return ret; | |
306 | ||
307 | bad: | |
308 | if (printk_ratelimit()) | |
309 | WARN_ON(1); | |
310 | return PCI_DMA_ERROR_CODE; | |
6a32fd4d DM |
311 | |
312 | iommu_map_fail: | |
313 | /* Interrupts are disabled. */ | |
314 | spin_lock(&iommu->lock); | |
315 | pci_arena_free(&iommu->arena, entry, npages); | |
316 | spin_unlock_irqrestore(&iommu->lock, flags); | |
317 | ||
318 | return PCI_DMA_ERROR_CODE; | |
8f6a93a1 DM |
319 | } |
320 | ||
321 | static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) | |
322 | { | |
a2fb23af | 323 | struct pci_pbm_info *pbm; |
18397944 | 324 | struct pci_iommu *iommu; |
7c8f486a | 325 | unsigned long flags, npages; |
18397944 | 326 | long entry; |
7c8f486a | 327 | u32 devhandle; |
18397944 DM |
328 | |
329 | if (unlikely(direction == PCI_DMA_NONE)) { | |
330 | if (printk_ratelimit()) | |
331 | WARN_ON(1); | |
332 | return; | |
333 | } | |
334 | ||
a2fb23af DM |
335 | iommu = pdev->dev.archdata.iommu; |
336 | pbm = pdev->dev.archdata.host_controller; | |
337 | devhandle = pbm->devhandle; | |
18397944 DM |
338 | |
339 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
340 | npages >>= IO_PAGE_SHIFT; | |
341 | bus_addr &= IO_PAGE_MASK; | |
342 | ||
343 | spin_lock_irqsave(&iommu->lock, flags); | |
344 | ||
345 | entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT; | |
346 | pci_arena_free(&iommu->arena, entry, npages); | |
347 | ||
348 | do { | |
349 | unsigned long num; | |
350 | ||
351 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
352 | npages); | |
353 | entry += num; | |
354 | npages -= num; | |
355 | } while (npages != 0); | |
356 | ||
357 | spin_unlock_irqrestore(&iommu->lock, flags); | |
358 | } | |
359 | ||
360 | #define SG_ENT_PHYS_ADDRESS(SG) \ | |
361 | (__pa(page_address((SG)->page)) + (SG)->offset) | |
362 | ||
6a32fd4d | 363 | static inline long fill_sg(long entry, struct pci_dev *pdev, |
18397944 DM |
364 | struct scatterlist *sg, |
365 | int nused, int nelems, unsigned long prot) | |
366 | { | |
367 | struct scatterlist *dma_sg = sg; | |
368 | struct scatterlist *sg_end = sg + nelems; | |
6a32fd4d DM |
369 | unsigned long flags; |
370 | int i; | |
371 | ||
372 | local_irq_save(flags); | |
373 | ||
374 | pci_iommu_batch_start(pdev, prot, entry); | |
18397944 | 375 | |
18397944 DM |
376 | for (i = 0; i < nused; i++) { |
377 | unsigned long pteval = ~0UL; | |
378 | u32 dma_npages; | |
379 | ||
380 | dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) + | |
381 | dma_sg->dma_length + | |
382 | ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT; | |
383 | do { | |
384 | unsigned long offset; | |
385 | signed int len; | |
386 | ||
387 | /* If we are here, we know we have at least one | |
388 | * more page to map. So walk forward until we | |
389 | * hit a page crossing, and begin creating new | |
390 | * mappings from that spot. | |
391 | */ | |
392 | for (;;) { | |
393 | unsigned long tmp; | |
394 | ||
395 | tmp = SG_ENT_PHYS_ADDRESS(sg); | |
396 | len = sg->length; | |
397 | if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) { | |
398 | pteval = tmp & IO_PAGE_MASK; | |
399 | offset = tmp & (IO_PAGE_SIZE - 1UL); | |
400 | break; | |
401 | } | |
402 | if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) { | |
403 | pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK; | |
404 | offset = 0UL; | |
405 | len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL))); | |
406 | break; | |
407 | } | |
408 | sg++; | |
409 | } | |
410 | ||
411 | pteval = (pteval & IOPTE_PAGE); | |
412 | while (len > 0) { | |
6a32fd4d DM |
413 | long err; |
414 | ||
415 | err = pci_iommu_batch_add(pteval); | |
416 | if (unlikely(err < 0L)) | |
417 | goto iommu_map_failed; | |
418 | ||
18397944 DM |
419 | pteval += IO_PAGE_SIZE; |
420 | len -= (IO_PAGE_SIZE - offset); | |
421 | offset = 0; | |
422 | dma_npages--; | |
423 | } | |
424 | ||
425 | pteval = (pteval & IOPTE_PAGE) + len; | |
426 | sg++; | |
427 | ||
428 | /* Skip over any tail mappings we've fully mapped, | |
429 | * adjusting pteval along the way. Stop when we | |
430 | * detect a page crossing event. | |
431 | */ | |
432 | while (sg < sg_end && | |
433 | (pteval << (64 - IO_PAGE_SHIFT)) != 0UL && | |
434 | (pteval == SG_ENT_PHYS_ADDRESS(sg)) && | |
435 | ((pteval ^ | |
436 | (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) { | |
437 | pteval += sg->length; | |
438 | sg++; | |
439 | } | |
440 | if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL) | |
441 | pteval = ~0UL; | |
442 | } while (dma_npages != 0); | |
443 | dma_sg++; | |
444 | } | |
445 | ||
6a32fd4d DM |
446 | if (unlikely(pci_iommu_batch_end() < 0L)) |
447 | goto iommu_map_failed; | |
18397944 | 448 | |
6a32fd4d DM |
449 | local_irq_restore(flags); |
450 | return 0; | |
18397944 | 451 | |
6a32fd4d DM |
452 | iommu_map_failed: |
453 | local_irq_restore(flags); | |
454 | return -1L; | |
8f6a93a1 DM |
455 | } |
456 | ||
457 | static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) | |
458 | { | |
18397944 | 459 | struct pci_iommu *iommu; |
7c8f486a | 460 | unsigned long flags, npages, prot; |
6a32fd4d | 461 | u32 dma_base; |
18397944 | 462 | struct scatterlist *sgtmp; |
6a32fd4d | 463 | long entry, err; |
18397944 DM |
464 | int used; |
465 | ||
466 | /* Fast path single entry scatterlists. */ | |
467 | if (nelems == 1) { | |
468 | sglist->dma_address = | |
469 | pci_4v_map_single(pdev, | |
470 | (page_address(sglist->page) + sglist->offset), | |
471 | sglist->length, direction); | |
472 | if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE)) | |
473 | return 0; | |
474 | sglist->dma_length = sglist->length; | |
475 | return 1; | |
476 | } | |
477 | ||
a2fb23af | 478 | iommu = pdev->dev.archdata.iommu; |
18397944 DM |
479 | |
480 | if (unlikely(direction == PCI_DMA_NONE)) | |
481 | goto bad; | |
482 | ||
483 | /* Step 1: Prepare scatter list. */ | |
484 | npages = prepare_sg(sglist, nelems); | |
18397944 DM |
485 | |
486 | /* Step 2: Allocate a cluster and context, if necessary. */ | |
487 | spin_lock_irqsave(&iommu->lock, flags); | |
488 | entry = pci_arena_alloc(&iommu->arena, npages); | |
489 | spin_unlock_irqrestore(&iommu->lock, flags); | |
490 | ||
491 | if (unlikely(entry < 0L)) | |
492 | goto bad; | |
493 | ||
494 | dma_base = iommu->page_table_map_base + | |
495 | (entry << IO_PAGE_SHIFT); | |
496 | ||
497 | /* Step 3: Normalize DMA addresses. */ | |
498 | used = nelems; | |
499 | ||
500 | sgtmp = sglist; | |
501 | while (used && sgtmp->dma_length) { | |
502 | sgtmp->dma_address += dma_base; | |
503 | sgtmp++; | |
504 | used--; | |
505 | } | |
506 | used = nelems - used; | |
507 | ||
508 | /* Step 4: Create the mappings. */ | |
509 | prot = HV_PCI_MAP_ATTR_READ; | |
510 | if (direction != PCI_DMA_TODEVICE) | |
511 | prot |= HV_PCI_MAP_ATTR_WRITE; | |
512 | ||
6a32fd4d DM |
513 | err = fill_sg(entry, pdev, sglist, used, nelems, prot); |
514 | if (unlikely(err < 0L)) | |
515 | goto iommu_map_failed; | |
18397944 DM |
516 | |
517 | return used; | |
518 | ||
519 | bad: | |
520 | if (printk_ratelimit()) | |
521 | WARN_ON(1); | |
522 | return 0; | |
6a32fd4d DM |
523 | |
524 | iommu_map_failed: | |
525 | spin_lock_irqsave(&iommu->lock, flags); | |
526 | pci_arena_free(&iommu->arena, entry, npages); | |
527 | spin_unlock_irqrestore(&iommu->lock, flags); | |
528 | ||
529 | return 0; | |
8f6a93a1 DM |
530 | } |
531 | ||
532 | static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) | |
533 | { | |
a2fb23af | 534 | struct pci_pbm_info *pbm; |
18397944 | 535 | struct pci_iommu *iommu; |
7c8f486a | 536 | unsigned long flags, i, npages; |
18397944 | 537 | long entry; |
7c8f486a | 538 | u32 devhandle, bus_addr; |
18397944 DM |
539 | |
540 | if (unlikely(direction == PCI_DMA_NONE)) { | |
541 | if (printk_ratelimit()) | |
542 | WARN_ON(1); | |
543 | } | |
544 | ||
a2fb23af DM |
545 | iommu = pdev->dev.archdata.iommu; |
546 | pbm = pdev->dev.archdata.host_controller; | |
547 | devhandle = pbm->devhandle; | |
18397944 DM |
548 | |
549 | bus_addr = sglist->dma_address & IO_PAGE_MASK; | |
550 | ||
551 | for (i = 1; i < nelems; i++) | |
552 | if (sglist[i].dma_length == 0) | |
553 | break; | |
554 | i--; | |
555 | npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - | |
556 | bus_addr) >> IO_PAGE_SHIFT; | |
557 | ||
558 | entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
559 | ||
560 | spin_lock_irqsave(&iommu->lock, flags); | |
561 | ||
562 | pci_arena_free(&iommu->arena, entry, npages); | |
563 | ||
564 | do { | |
565 | unsigned long num; | |
566 | ||
567 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
568 | npages); | |
569 | entry += num; | |
570 | npages -= num; | |
571 | } while (npages != 0); | |
572 | ||
573 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8f6a93a1 DM |
574 | } |
575 | ||
576 | static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) | |
577 | { | |
18397944 | 578 | /* Nothing to do... */ |
8f6a93a1 DM |
579 | } |
580 | ||
581 | static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) | |
582 | { | |
18397944 | 583 | /* Nothing to do... */ |
8f6a93a1 DM |
584 | } |
585 | ||
586 | struct pci_iommu_ops pci_sun4v_iommu_ops = { | |
587 | .alloc_consistent = pci_4v_alloc_consistent, | |
588 | .free_consistent = pci_4v_free_consistent, | |
589 | .map_single = pci_4v_map_single, | |
590 | .unmap_single = pci_4v_unmap_single, | |
591 | .map_sg = pci_4v_map_sg, | |
592 | .unmap_sg = pci_4v_unmap_sg, | |
593 | .dma_sync_single_for_cpu = pci_4v_dma_sync_single_for_cpu, | |
594 | .dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu, | |
595 | }; | |
596 | ||
46b30493 DM |
597 | static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func) |
598 | { | |
059833eb DM |
599 | if (bus < pbm->pci_first_busno || |
600 | bus > pbm->pci_last_busno) | |
601 | return 1; | |
a2fb23af | 602 | return 0; |
059833eb DM |
603 | } |
604 | ||
bade5622 DM |
605 | static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
606 | int where, int size, u32 *value) | |
607 | { | |
7eae642f | 608 | struct pci_pbm_info *pbm = bus_dev->sysdata; |
059833eb | 609 | u32 devhandle = pbm->devhandle; |
7eae642f DM |
610 | unsigned int bus = bus_dev->number; |
611 | unsigned int device = PCI_SLOT(devfn); | |
612 | unsigned int func = PCI_FUNC(devfn); | |
613 | unsigned long ret; | |
614 | ||
987b6de7 | 615 | if (pci_sun4v_out_of_range(pbm, bus, device, func)) { |
059833eb DM |
616 | ret = ~0UL; |
617 | } else { | |
618 | ret = pci_sun4v_config_get(devhandle, | |
619 | HV_PCI_DEVICE_BUILD(bus, device, func), | |
620 | where, size); | |
10804828 | 621 | #if 0 |
987b6de7 | 622 | printk("rcfg: [%x:%x:%x:%d]=[%lx]\n", |
10804828 DM |
623 | devhandle, HV_PCI_DEVICE_BUILD(bus, device, func), |
624 | where, size, ret); | |
625 | #endif | |
059833eb | 626 | } |
7eae642f DM |
627 | switch (size) { |
628 | case 1: | |
629 | *value = ret & 0xff; | |
630 | break; | |
631 | case 2: | |
632 | *value = ret & 0xffff; | |
633 | break; | |
634 | case 4: | |
635 | *value = ret & 0xffffffff; | |
636 | break; | |
637 | }; | |
638 | ||
639 | ||
640 | return PCIBIOS_SUCCESSFUL; | |
bade5622 DM |
641 | } |
642 | ||
643 | static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
644 | int where, int size, u32 value) | |
645 | { | |
7eae642f | 646 | struct pci_pbm_info *pbm = bus_dev->sysdata; |
059833eb | 647 | u32 devhandle = pbm->devhandle; |
7eae642f DM |
648 | unsigned int bus = bus_dev->number; |
649 | unsigned int device = PCI_SLOT(devfn); | |
650 | unsigned int func = PCI_FUNC(devfn); | |
651 | unsigned long ret; | |
652 | ||
987b6de7 | 653 | if (pci_sun4v_out_of_range(pbm, bus, device, func)) { |
059833eb DM |
654 | /* Do nothing. */ |
655 | } else { | |
656 | ret = pci_sun4v_config_put(devhandle, | |
657 | HV_PCI_DEVICE_BUILD(bus, device, func), | |
658 | where, size, value); | |
10804828 | 659 | #if 0 |
987b6de7 | 660 | printk("wcfg: [%x:%x:%x:%d] v[%x] == [%lx]\n", |
10804828 DM |
661 | devhandle, HV_PCI_DEVICE_BUILD(bus, device, func), |
662 | where, size, value, ret); | |
663 | #endif | |
059833eb | 664 | } |
7eae642f | 665 | return PCIBIOS_SUCCESSFUL; |
bade5622 DM |
666 | } |
667 | ||
668 | static struct pci_ops pci_sun4v_ops = { | |
669 | .read = pci_sun4v_read_pci_cfg, | |
670 | .write = pci_sun4v_write_pci_cfg, | |
671 | }; | |
672 | ||
673 | ||
c2609267 DM |
674 | static void pbm_scan_bus(struct pci_controller_info *p, |
675 | struct pci_pbm_info *pbm) | |
676 | { | |
a2fb23af | 677 | pbm->pci_bus = pci_scan_one_pbm(pbm); |
c2609267 DM |
678 | } |
679 | ||
bade5622 DM |
680 | static void pci_sun4v_scan_bus(struct pci_controller_info *p) |
681 | { | |
e87dc350 DM |
682 | struct property *prop; |
683 | struct device_node *dp; | |
684 | ||
685 | if ((dp = p->pbm_A.prom_node) != NULL) { | |
686 | prop = of_find_property(dp, "66mhz-capable", NULL); | |
687 | p->pbm_A.is_66mhz_capable = (prop != NULL); | |
c2609267 DM |
688 | |
689 | pbm_scan_bus(p, &p->pbm_A); | |
690 | } | |
e87dc350 DM |
691 | if ((dp = p->pbm_B.prom_node) != NULL) { |
692 | prop = of_find_property(dp, "66mhz-capable", NULL); | |
693 | p->pbm_B.is_66mhz_capable = (prop != NULL); | |
c2609267 DM |
694 | |
695 | pbm_scan_bus(p, &p->pbm_B); | |
696 | } | |
697 | ||
698 | /* XXX register error interrupt handlers XXX */ | |
bade5622 DM |
699 | } |
700 | ||
bade5622 DM |
701 | static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource) |
702 | { | |
a2fb23af | 703 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
bade5622 DM |
704 | struct resource *res, *root; |
705 | u32 reg; | |
706 | int where, size, is_64bit; | |
707 | ||
708 | res = &pdev->resource[resource]; | |
709 | if (resource < 6) { | |
710 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | |
711 | } else if (resource == PCI_ROM_RESOURCE) { | |
712 | where = pdev->rom_base_reg; | |
713 | } else { | |
714 | /* Somebody might have asked allocation of a non-standard resource */ | |
715 | return; | |
716 | } | |
717 | ||
c2609267 | 718 | /* XXX 64-bit MEM handling is not %100 correct... XXX */ |
bade5622 DM |
719 | is_64bit = 0; |
720 | if (res->flags & IORESOURCE_IO) | |
721 | root = &pbm->io_space; | |
722 | else { | |
723 | root = &pbm->mem_space; | |
724 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | |
725 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | |
726 | is_64bit = 1; | |
727 | } | |
728 | ||
729 | size = res->end - res->start; | |
730 | pci_read_config_dword(pdev, where, ®); | |
731 | reg = ((reg & size) | | |
732 | (((u32)(res->start - root->start)) & ~size)); | |
733 | if (resource == PCI_ROM_RESOURCE) { | |
734 | reg |= PCI_ROM_ADDRESS_ENABLE; | |
735 | res->flags |= IORESOURCE_ROM_ENABLE; | |
736 | } | |
737 | pci_write_config_dword(pdev, where, reg); | |
738 | ||
739 | /* This knows that the upper 32-bits of the address | |
740 | * must be zero. Our PCI common layer enforces this. | |
741 | */ | |
742 | if (is_64bit) | |
743 | pci_write_config_dword(pdev, where + 4, 0); | |
744 | } | |
745 | ||
bade5622 DM |
746 | static void pci_sun4v_resource_adjust(struct pci_dev *pdev, |
747 | struct resource *res, | |
748 | struct resource *root) | |
749 | { | |
750 | res->start += root->start; | |
751 | res->end += root->start; | |
752 | } | |
753 | ||
e7a0453e DM |
754 | static unsigned long probe_existing_entries(struct pci_pbm_info *pbm, |
755 | struct pci_iommu *iommu) | |
18397944 DM |
756 | { |
757 | struct pci_iommu_arena *arena = &iommu->arena; | |
e7a0453e | 758 | unsigned long i, cnt = 0; |
7c8f486a | 759 | u32 devhandle; |
18397944 DM |
760 | |
761 | devhandle = pbm->devhandle; | |
762 | for (i = 0; i < arena->limit; i++) { | |
763 | unsigned long ret, io_attrs, ra; | |
764 | ||
765 | ret = pci_sun4v_iommu_getmap(devhandle, | |
766 | HV_PCI_TSBID(0, i), | |
767 | &io_attrs, &ra); | |
e7a0453e | 768 | if (ret == HV_EOK) { |
c2a5a46b DM |
769 | if (page_in_phys_avail(ra)) { |
770 | pci_sun4v_iommu_demap(devhandle, | |
771 | HV_PCI_TSBID(0, i), 1); | |
772 | } else { | |
773 | cnt++; | |
774 | __set_bit(i, arena->map); | |
775 | } | |
e7a0453e | 776 | } |
18397944 | 777 | } |
e7a0453e DM |
778 | |
779 | return cnt; | |
18397944 DM |
780 | } |
781 | ||
bade5622 DM |
782 | static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm) |
783 | { | |
18397944 | 784 | struct pci_iommu *iommu = pbm->iommu; |
e87dc350 | 785 | struct property *prop; |
18397944 DM |
786 | unsigned long num_tsb_entries, sz; |
787 | u32 vdma[2], dma_mask, dma_offset; | |
e87dc350 DM |
788 | int tsbsize; |
789 | ||
790 | prop = of_find_property(pbm->prom_node, "virtual-dma", NULL); | |
791 | if (prop) { | |
792 | u32 *val = prop->value; | |
18397944 | 793 | |
e87dc350 DM |
794 | vdma[0] = val[0]; |
795 | vdma[1] = val[1]; | |
796 | } else { | |
18397944 DM |
797 | /* No property, use default values. */ |
798 | vdma[0] = 0x80000000; | |
799 | vdma[1] = 0x80000000; | |
800 | } | |
801 | ||
802 | dma_mask = vdma[0]; | |
803 | switch (vdma[1]) { | |
804 | case 0x20000000: | |
805 | dma_mask |= 0x1fffffff; | |
806 | tsbsize = 64; | |
807 | break; | |
808 | ||
809 | case 0x40000000: | |
810 | dma_mask |= 0x3fffffff; | |
811 | tsbsize = 128; | |
812 | break; | |
813 | ||
814 | case 0x80000000: | |
815 | dma_mask |= 0x7fffffff; | |
e7a0453e | 816 | tsbsize = 256; |
18397944 DM |
817 | break; |
818 | ||
819 | default: | |
820 | prom_printf("PCI-SUN4V: strange virtual-dma size.\n"); | |
821 | prom_halt(); | |
822 | }; | |
823 | ||
e7a0453e DM |
824 | tsbsize *= (8 * 1024); |
825 | ||
18397944 DM |
826 | num_tsb_entries = tsbsize / sizeof(iopte_t); |
827 | ||
828 | dma_offset = vdma[0]; | |
829 | ||
830 | /* Setup initial software IOMMU state. */ | |
831 | spin_lock_init(&iommu->lock); | |
832 | iommu->ctx_lowest_free = 1; | |
833 | iommu->page_table_map_base = dma_offset; | |
834 | iommu->dma_addr_mask = dma_mask; | |
835 | ||
836 | /* Allocate and initialize the free area map. */ | |
837 | sz = num_tsb_entries / 8; | |
838 | sz = (sz + 7UL) & ~7UL; | |
982c2064 | 839 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
18397944 DM |
840 | if (!iommu->arena.map) { |
841 | prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n"); | |
842 | prom_halt(); | |
843 | } | |
18397944 DM |
844 | iommu->arena.limit = num_tsb_entries; |
845 | ||
e7a0453e | 846 | sz = probe_existing_entries(pbm, iommu); |
c2a5a46b DM |
847 | if (sz) |
848 | printk("%s: Imported %lu TSB entries from OBP\n", | |
849 | pbm->name, sz); | |
bade5622 DM |
850 | } |
851 | ||
10804828 DM |
852 | static void pci_sun4v_get_bus_range(struct pci_pbm_info *pbm) |
853 | { | |
e87dc350 DM |
854 | struct property *prop; |
855 | unsigned int *busrange; | |
856 | ||
857 | prop = of_find_property(pbm->prom_node, "bus-range", NULL); | |
858 | ||
859 | busrange = prop->value; | |
10804828 DM |
860 | |
861 | pbm->pci_first_busno = busrange[0]; | |
862 | pbm->pci_last_busno = busrange[1]; | |
863 | ||
864 | } | |
865 | ||
35a17eb6 DM |
866 | #ifdef CONFIG_PCI_MSI |
867 | struct pci_sun4v_msiq_entry { | |
868 | u64 version_type; | |
869 | #define MSIQ_VERSION_MASK 0xffffffff00000000UL | |
870 | #define MSIQ_VERSION_SHIFT 32 | |
871 | #define MSIQ_TYPE_MASK 0x00000000000000ffUL | |
872 | #define MSIQ_TYPE_SHIFT 0 | |
873 | #define MSIQ_TYPE_NONE 0x00 | |
874 | #define MSIQ_TYPE_MSG 0x01 | |
875 | #define MSIQ_TYPE_MSI32 0x02 | |
876 | #define MSIQ_TYPE_MSI64 0x03 | |
877 | #define MSIQ_TYPE_INTX 0x08 | |
878 | #define MSIQ_TYPE_NONE2 0xff | |
879 | ||
880 | u64 intx_sysino; | |
881 | u64 reserved1; | |
882 | u64 stick; | |
883 | u64 req_id; /* bus/device/func */ | |
884 | #define MSIQ_REQID_BUS_MASK 0xff00UL | |
885 | #define MSIQ_REQID_BUS_SHIFT 8 | |
886 | #define MSIQ_REQID_DEVICE_MASK 0x00f8UL | |
887 | #define MSIQ_REQID_DEVICE_SHIFT 3 | |
888 | #define MSIQ_REQID_FUNC_MASK 0x0007UL | |
889 | #define MSIQ_REQID_FUNC_SHIFT 0 | |
890 | ||
891 | u64 msi_address; | |
892 | ||
893 | /* The format of this value is message type dependant. | |
894 | * For MSI bits 15:0 are the data from the MSI packet. | |
895 | * For MSI-X bits 31:0 are the data from the MSI packet. | |
896 | * For MSG, the message code and message routing code where: | |
897 | * bits 39:32 is the bus/device/fn of the msg target-id | |
898 | * bits 18:16 is the message routing code | |
899 | * bits 7:0 is the message code | |
900 | * For INTx the low order 2-bits are: | |
901 | * 00 - INTA | |
902 | * 01 - INTB | |
903 | * 10 - INTC | |
904 | * 11 - INTD | |
905 | */ | |
906 | u64 msi_data; | |
907 | ||
908 | u64 reserved2; | |
909 | }; | |
910 | ||
911 | /* For now this just runs as a pre-handler for the real interrupt handler. | |
912 | * So we just walk through the queue and ACK all the entries, update the | |
913 | * head pointer, and return. | |
914 | * | |
915 | * In the longer term it would be nice to do something more integrated | |
916 | * wherein we can pass in some of this MSI info to the drivers. This | |
917 | * would be most useful for PCIe fabric error messages, although we could | |
918 | * invoke those directly from the loop here in order to pass the info around. | |
919 | */ | |
920 | static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2) | |
921 | { | |
922 | struct pci_pbm_info *pbm = data1; | |
923 | struct pci_sun4v_msiq_entry *base, *ep; | |
924 | unsigned long msiqid, orig_head, head, type, err; | |
925 | ||
926 | msiqid = (unsigned long) data2; | |
927 | ||
928 | head = 0xdeadbeef; | |
929 | err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head); | |
930 | if (unlikely(err)) | |
931 | goto hv_error_get; | |
932 | ||
933 | if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))) | |
934 | goto bad_offset; | |
935 | ||
936 | head /= sizeof(struct pci_sun4v_msiq_entry); | |
937 | orig_head = head; | |
938 | base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * | |
939 | (pbm->msiq_ent_count * | |
940 | sizeof(struct pci_sun4v_msiq_entry)))); | |
941 | ep = &base[head]; | |
942 | while ((ep->version_type & MSIQ_TYPE_MASK) != 0) { | |
943 | type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT; | |
944 | if (unlikely(type != MSIQ_TYPE_MSI32 && | |
945 | type != MSIQ_TYPE_MSI64)) | |
946 | goto bad_type; | |
947 | ||
948 | pci_sun4v_msi_setstate(pbm->devhandle, | |
949 | ep->msi_data /* msi_num */, | |
950 | HV_MSISTATE_IDLE); | |
951 | ||
952 | /* Clear the entry. */ | |
953 | ep->version_type &= ~MSIQ_TYPE_MASK; | |
954 | ||
955 | /* Go to next entry in ring. */ | |
956 | head++; | |
957 | if (head >= pbm->msiq_ent_count) | |
958 | head = 0; | |
959 | ep = &base[head]; | |
960 | } | |
961 | ||
962 | if (likely(head != orig_head)) { | |
963 | /* ACK entries by updating head pointer. */ | |
964 | head *= sizeof(struct pci_sun4v_msiq_entry); | |
965 | err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head); | |
966 | if (unlikely(err)) | |
967 | goto hv_error_set; | |
968 | } | |
969 | return; | |
970 | ||
971 | hv_error_set: | |
972 | printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err); | |
973 | goto hv_error_cont; | |
974 | ||
975 | hv_error_get: | |
976 | printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err); | |
977 | ||
978 | hv_error_cont: | |
979 | printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n", | |
980 | pbm->devhandle, msiqid, head); | |
981 | return; | |
982 | ||
983 | bad_offset: | |
984 | printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n", | |
985 | head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)); | |
986 | return; | |
987 | ||
988 | bad_type: | |
989 | printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type); | |
990 | return; | |
991 | } | |
992 | ||
993 | static int msi_bitmap_alloc(struct pci_pbm_info *pbm) | |
994 | { | |
995 | unsigned long size, bits_per_ulong; | |
996 | ||
997 | bits_per_ulong = sizeof(unsigned long) * 8; | |
998 | size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1); | |
999 | size /= 8; | |
1000 | BUG_ON(size % sizeof(unsigned long)); | |
1001 | ||
1002 | pbm->msi_bitmap = kzalloc(size, GFP_KERNEL); | |
1003 | if (!pbm->msi_bitmap) | |
1004 | return -ENOMEM; | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static void msi_bitmap_free(struct pci_pbm_info *pbm) | |
1010 | { | |
1011 | kfree(pbm->msi_bitmap); | |
1012 | pbm->msi_bitmap = NULL; | |
1013 | } | |
1014 | ||
1015 | static int msi_queue_alloc(struct pci_pbm_info *pbm) | |
1016 | { | |
1017 | unsigned long q_size, alloc_size, pages, order; | |
1018 | int i; | |
1019 | ||
1020 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); | |
1021 | alloc_size = (pbm->msiq_num * q_size); | |
1022 | order = get_order(alloc_size); | |
1023 | pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order); | |
1024 | if (pages == 0UL) { | |
1025 | printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n", | |
1026 | order); | |
1027 | return -ENOMEM; | |
1028 | } | |
1029 | memset((char *)pages, 0, PAGE_SIZE << order); | |
1030 | pbm->msi_queues = (void *) pages; | |
1031 | ||
1032 | for (i = 0; i < pbm->msiq_num; i++) { | |
1033 | unsigned long err, base = __pa(pages + (i * q_size)); | |
1034 | unsigned long ret1, ret2; | |
1035 | ||
1036 | err = pci_sun4v_msiq_conf(pbm->devhandle, | |
1037 | pbm->msiq_first + i, | |
1038 | base, pbm->msiq_ent_count); | |
1039 | if (err) { | |
1040 | printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n", | |
1041 | err); | |
1042 | goto h_error; | |
1043 | } | |
1044 | ||
1045 | err = pci_sun4v_msiq_info(pbm->devhandle, | |
1046 | pbm->msiq_first + i, | |
1047 | &ret1, &ret2); | |
1048 | if (err) { | |
1049 | printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n", | |
1050 | err); | |
1051 | goto h_error; | |
1052 | } | |
1053 | if (ret1 != base || ret2 != pbm->msiq_ent_count) { | |
1054 | printk(KERN_ERR "MSI: Bogus qconf " | |
1055 | "expected[%lx:%x] got[%lx:%lx]\n", | |
1056 | base, pbm->msiq_ent_count, | |
1057 | ret1, ret2); | |
1058 | goto h_error; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | ||
1064 | h_error: | |
1065 | free_pages(pages, order); | |
1066 | return -EINVAL; | |
1067 | } | |
1068 | ||
1069 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) | |
1070 | { | |
6a23acf3 | 1071 | const u32 *val; |
35a17eb6 DM |
1072 | int len; |
1073 | ||
1074 | val = of_get_property(pbm->prom_node, "#msi-eqs", &len); | |
1075 | if (!val || len != 4) | |
1076 | goto no_msi; | |
1077 | pbm->msiq_num = *val; | |
1078 | if (pbm->msiq_num) { | |
6a23acf3 | 1079 | const struct msiq_prop { |
35a17eb6 DM |
1080 | u32 first_msiq; |
1081 | u32 num_msiq; | |
1082 | u32 first_devino; | |
1083 | } *mqp; | |
6a23acf3 | 1084 | const struct msi_range_prop { |
35a17eb6 DM |
1085 | u32 first_msi; |
1086 | u32 num_msi; | |
1087 | } *mrng; | |
6a23acf3 | 1088 | const struct addr_range_prop { |
35a17eb6 DM |
1089 | u32 msi32_high; |
1090 | u32 msi32_low; | |
1091 | u32 msi32_len; | |
1092 | u32 msi64_high; | |
1093 | u32 msi64_low; | |
1094 | u32 msi64_len; | |
1095 | } *arng; | |
1096 | ||
1097 | val = of_get_property(pbm->prom_node, "msi-eq-size", &len); | |
1098 | if (!val || len != 4) | |
1099 | goto no_msi; | |
1100 | ||
1101 | pbm->msiq_ent_count = *val; | |
1102 | ||
1103 | mqp = of_get_property(pbm->prom_node, | |
1104 | "msi-eq-to-devino", &len); | |
1105 | if (!mqp || len != sizeof(struct msiq_prop)) | |
1106 | goto no_msi; | |
1107 | ||
1108 | pbm->msiq_first = mqp->first_msiq; | |
1109 | pbm->msiq_first_devino = mqp->first_devino; | |
1110 | ||
1111 | val = of_get_property(pbm->prom_node, "#msi", &len); | |
1112 | if (!val || len != 4) | |
1113 | goto no_msi; | |
1114 | pbm->msi_num = *val; | |
1115 | ||
1116 | mrng = of_get_property(pbm->prom_node, "msi-ranges", &len); | |
1117 | if (!mrng || len != sizeof(struct msi_range_prop)) | |
1118 | goto no_msi; | |
1119 | pbm->msi_first = mrng->first_msi; | |
1120 | ||
1121 | val = of_get_property(pbm->prom_node, "msi-data-mask", &len); | |
1122 | if (!val || len != 4) | |
1123 | goto no_msi; | |
1124 | pbm->msi_data_mask = *val; | |
1125 | ||
1126 | val = of_get_property(pbm->prom_node, "msix-data-width", &len); | |
1127 | if (!val || len != 4) | |
1128 | goto no_msi; | |
1129 | pbm->msix_data_width = *val; | |
1130 | ||
1131 | arng = of_get_property(pbm->prom_node, "msi-address-ranges", | |
1132 | &len); | |
1133 | if (!arng || len != sizeof(struct addr_range_prop)) | |
1134 | goto no_msi; | |
1135 | pbm->msi32_start = ((u64)arng->msi32_high << 32) | | |
1136 | (u64) arng->msi32_low; | |
1137 | pbm->msi64_start = ((u64)arng->msi64_high << 32) | | |
1138 | (u64) arng->msi64_low; | |
1139 | pbm->msi32_len = arng->msi32_len; | |
1140 | pbm->msi64_len = arng->msi64_len; | |
1141 | ||
1142 | if (msi_bitmap_alloc(pbm)) | |
1143 | goto no_msi; | |
1144 | ||
1145 | if (msi_queue_alloc(pbm)) { | |
1146 | msi_bitmap_free(pbm); | |
1147 | goto no_msi; | |
1148 | } | |
1149 | ||
1150 | printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] " | |
1151 | "devino[0x%x]\n", | |
1152 | pbm->name, | |
1153 | pbm->msiq_first, pbm->msiq_num, | |
1154 | pbm->msiq_ent_count, | |
1155 | pbm->msiq_first_devino); | |
1156 | printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] " | |
1157 | "width[%u]\n", | |
1158 | pbm->name, | |
1159 | pbm->msi_first, pbm->msi_num, pbm->msi_data_mask, | |
1160 | pbm->msix_data_width); | |
1161 | printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] " | |
1162 | "addr64[0x%lx:0x%x]\n", | |
1163 | pbm->name, | |
1164 | pbm->msi32_start, pbm->msi32_len, | |
1165 | pbm->msi64_start, pbm->msi64_len); | |
1166 | printk(KERN_INFO "%s: MSI queues at RA [%p]\n", | |
1167 | pbm->name, | |
1168 | pbm->msi_queues); | |
1169 | } | |
1170 | ||
1171 | return; | |
1172 | ||
1173 | no_msi: | |
1174 | pbm->msiq_num = 0; | |
1175 | printk(KERN_INFO "%s: No MSI support.\n", pbm->name); | |
1176 | } | |
1177 | ||
1178 | static int alloc_msi(struct pci_pbm_info *pbm) | |
1179 | { | |
1180 | int i; | |
1181 | ||
1182 | for (i = 0; i < pbm->msi_num; i++) { | |
1183 | if (!test_and_set_bit(i, pbm->msi_bitmap)) | |
1184 | return i + pbm->msi_first; | |
1185 | } | |
1186 | ||
1187 | return -ENOENT; | |
1188 | } | |
1189 | ||
1190 | static void free_msi(struct pci_pbm_info *pbm, int msi_num) | |
1191 | { | |
1192 | msi_num -= pbm->msi_first; | |
1193 | clear_bit(msi_num, pbm->msi_bitmap); | |
1194 | } | |
1195 | ||
1196 | static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p, | |
1197 | struct pci_dev *pdev, | |
1198 | struct msi_desc *entry) | |
1199 | { | |
a2fb23af | 1200 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 DM |
1201 | unsigned long devino, msiqid; |
1202 | struct msi_msg msg; | |
1203 | int msi_num, err; | |
1204 | ||
1205 | *virt_irq_p = 0; | |
1206 | ||
1207 | msi_num = alloc_msi(pbm); | |
1208 | if (msi_num < 0) | |
1209 | return msi_num; | |
1210 | ||
1211 | devino = sun4v_build_msi(pbm->devhandle, virt_irq_p, | |
1212 | pbm->msiq_first_devino, | |
1213 | (pbm->msiq_first_devino + | |
1214 | pbm->msiq_num)); | |
1215 | err = -ENOMEM; | |
1216 | if (!devino) | |
1217 | goto out_err; | |
1218 | ||
1219 | set_irq_msi(*virt_irq_p, entry); | |
1220 | ||
1221 | msiqid = ((devino - pbm->msiq_first_devino) + | |
1222 | pbm->msiq_first); | |
1223 | ||
1224 | err = -EINVAL; | |
1225 | if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) | |
1226 | if (err) | |
1227 | goto out_err; | |
1228 | ||
1229 | if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) | |
1230 | goto out_err; | |
1231 | ||
1232 | if (pci_sun4v_msi_setmsiq(pbm->devhandle, | |
1233 | msi_num, msiqid, | |
1234 | (entry->msi_attrib.is_64 ? | |
1235 | HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32))) | |
1236 | goto out_err; | |
1237 | ||
1238 | if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE)) | |
1239 | goto out_err; | |
1240 | ||
1241 | if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID)) | |
1242 | goto out_err; | |
1243 | ||
a2fb23af | 1244 | pdev->dev.archdata.msi_num = msi_num; |
35a17eb6 DM |
1245 | |
1246 | if (entry->msi_attrib.is_64) { | |
1247 | msg.address_hi = pbm->msi64_start >> 32; | |
1248 | msg.address_lo = pbm->msi64_start & 0xffffffff; | |
1249 | } else { | |
1250 | msg.address_hi = 0; | |
1251 | msg.address_lo = pbm->msi32_start; | |
1252 | } | |
1253 | msg.data = msi_num; | |
1254 | write_msi_msg(*virt_irq_p, &msg); | |
1255 | ||
1256 | irq_install_pre_handler(*virt_irq_p, | |
1257 | pci_sun4v_msi_prehandler, | |
1258 | pbm, (void *) msiqid); | |
1259 | ||
1260 | return 0; | |
1261 | ||
1262 | out_err: | |
1263 | free_msi(pbm, msi_num); | |
1264 | sun4v_destroy_msi(*virt_irq_p); | |
1265 | *virt_irq_p = 0; | |
1266 | return err; | |
1267 | ||
1268 | } | |
1269 | ||
1270 | static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq, | |
1271 | struct pci_dev *pdev) | |
1272 | { | |
a2fb23af | 1273 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 DM |
1274 | unsigned long msiqid, err; |
1275 | unsigned int msi_num; | |
1276 | ||
a2fb23af | 1277 | msi_num = pdev->dev.archdata.msi_num; |
35a17eb6 DM |
1278 | err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid); |
1279 | if (err) { | |
1280 | printk(KERN_ERR "%s: getmsiq gives error %lu\n", | |
1281 | pbm->name, err); | |
1282 | return; | |
1283 | } | |
1284 | ||
1285 | pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID); | |
1286 | pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID); | |
1287 | ||
1288 | free_msi(pbm, msi_num); | |
1289 | ||
1290 | /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ | |
1291 | * allocation. | |
1292 | */ | |
1293 | sun4v_destroy_msi(virt_irq); | |
1294 | } | |
1295 | #else /* CONFIG_PCI_MSI */ | |
1296 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) | |
1297 | { | |
1298 | } | |
1299 | #endif /* !(CONFIG_PCI_MSI) */ | |
1300 | ||
e87dc350 | 1301 | static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle) |
bade5622 DM |
1302 | { |
1303 | struct pci_pbm_info *pbm; | |
e87dc350 DM |
1304 | struct property *prop; |
1305 | int len, i; | |
bade5622 | 1306 | |
3833789b DM |
1307 | if (devhandle & 0x40) |
1308 | pbm = &p->pbm_B; | |
1309 | else | |
1310 | pbm = &p->pbm_A; | |
bade5622 DM |
1311 | |
1312 | pbm->parent = p; | |
e87dc350 | 1313 | pbm->prom_node = dp; |
bade5622 DM |
1314 | pbm->pci_first_slot = 1; |
1315 | ||
3833789b | 1316 | pbm->devhandle = devhandle; |
bade5622 | 1317 | |
e87dc350 | 1318 | pbm->name = dp->full_name; |
bade5622 | 1319 | |
e87dc350 | 1320 | printk("%s: SUN4V PCI Bus Module\n", pbm->name); |
bade5622 | 1321 | |
e87dc350 DM |
1322 | prop = of_find_property(dp, "ranges", &len); |
1323 | pbm->pbm_ranges = prop->value; | |
bade5622 | 1324 | pbm->num_pbm_ranges = |
e87dc350 | 1325 | (len / sizeof(struct linux_prom_pci_ranges)); |
bade5622 | 1326 | |
3833789b DM |
1327 | /* Mask out the top 8 bits of the ranges, leaving the real |
1328 | * physical address. | |
1329 | */ | |
1330 | for (i = 0; i < pbm->num_pbm_ranges; i++) | |
1331 | pbm->pbm_ranges[i].parent_phys_hi &= 0x0fffffff; | |
1332 | ||
9fd8b647 | 1333 | pci_determine_mem_io_space(pbm); |
bade5622 | 1334 | |
10804828 | 1335 | pci_sun4v_get_bus_range(pbm); |
bade5622 | 1336 | pci_sun4v_iommu_init(pbm); |
35a17eb6 | 1337 | pci_sun4v_msi_init(pbm); |
bade5622 DM |
1338 | } |
1339 | ||
e87dc350 | 1340 | void sun4v_pci_init(struct device_node *dp, char *model_name) |
8f6a93a1 | 1341 | { |
bade5622 DM |
1342 | struct pci_controller_info *p; |
1343 | struct pci_iommu *iommu; | |
e87dc350 DM |
1344 | struct property *prop; |
1345 | struct linux_prom64_registers *regs; | |
7c8f486a DM |
1346 | u32 devhandle; |
1347 | int i; | |
3833789b | 1348 | |
e87dc350 DM |
1349 | prop = of_find_property(dp, "reg", NULL); |
1350 | regs = prop->value; | |
1351 | ||
1352 | devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
3833789b DM |
1353 | |
1354 | for (p = pci_controller_root; p; p = p->next) { | |
1355 | struct pci_pbm_info *pbm; | |
1356 | ||
1357 | if (p->pbm_A.prom_node && p->pbm_B.prom_node) | |
1358 | continue; | |
1359 | ||
1360 | pbm = (p->pbm_A.prom_node ? | |
1361 | &p->pbm_A : | |
1362 | &p->pbm_B); | |
1363 | ||
0b522497 | 1364 | if (pbm->devhandle == (devhandle ^ 0x40)) { |
e87dc350 | 1365 | pci_sun4v_pbm_init(p, dp, devhandle); |
0b522497 DM |
1366 | return; |
1367 | } | |
3833789b | 1368 | } |
bade5622 | 1369 | |
a283a525 | 1370 | for_each_possible_cpu(i) { |
7c8f486a DM |
1371 | unsigned long page = get_zeroed_page(GFP_ATOMIC); |
1372 | ||
1373 | if (!page) | |
1374 | goto fatal_memory_error; | |
1375 | ||
6a32fd4d | 1376 | per_cpu(pci_iommu_batch, i).pglist = (u64 *) page; |
bade5622 | 1377 | } |
7c8f486a | 1378 | |
982c2064 | 1379 | p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
7c8f486a DM |
1380 | if (!p) |
1381 | goto fatal_memory_error; | |
1382 | ||
982c2064 | 1383 | iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC); |
7c8f486a DM |
1384 | if (!iommu) |
1385 | goto fatal_memory_error; | |
1386 | ||
bade5622 DM |
1387 | p->pbm_A.iommu = iommu; |
1388 | ||
982c2064 | 1389 | iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC); |
7c8f486a DM |
1390 | if (!iommu) |
1391 | goto fatal_memory_error; | |
1392 | ||
bade5622 DM |
1393 | p->pbm_B.iommu = iommu; |
1394 | ||
1395 | p->next = pci_controller_root; | |
1396 | pci_controller_root = p; | |
1397 | ||
1398 | p->index = pci_num_controllers++; | |
1399 | p->pbms_same_domain = 0; | |
1400 | ||
1401 | p->scan_bus = pci_sun4v_scan_bus; | |
bade5622 DM |
1402 | p->base_address_update = pci_sun4v_base_address_update; |
1403 | p->resource_adjust = pci_sun4v_resource_adjust; | |
35a17eb6 DM |
1404 | #ifdef CONFIG_PCI_MSI |
1405 | p->setup_msi_irq = pci_sun4v_setup_msi_irq; | |
1406 | p->teardown_msi_irq = pci_sun4v_teardown_msi_irq; | |
1407 | #endif | |
bade5622 DM |
1408 | p->pci_ops = &pci_sun4v_ops; |
1409 | ||
1410 | /* Like PSYCHO and SCHIZO we have a 2GB aligned area | |
1411 | * for memory space. | |
1412 | */ | |
1413 | pci_memspace_mask = 0x7fffffffUL; | |
1414 | ||
e87dc350 | 1415 | pci_sun4v_pbm_init(p, dp, devhandle); |
7c8f486a DM |
1416 | return; |
1417 | ||
1418 | fatal_memory_error: | |
1419 | prom_printf("SUN4V_PCI: Fatal memory allocation error.\n"); | |
1420 | prom_halt(); | |
8f6a93a1 | 1421 | } |