Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
3 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
13 | #include <linux/smp_lock.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/cache.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/profile.h> | |
24 | #include <linux/bootmem.h> | |
25 | ||
26 | #include <asm/head.h> | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/tlbflush.h> | |
30 | #include <asm/mmu_context.h> | |
31 | #include <asm/cpudata.h> | |
32 | ||
33 | #include <asm/irq.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/timer.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/tlb.h> | |
56fb4df6 | 41 | #include <asm/sections.h> |
1da177e4 | 42 | |
1da177e4 LT |
43 | extern void calibrate_delay(void); |
44 | ||
45 | /* Please don't make this stuff initdata!!! --DaveM */ | |
46 | static unsigned char boot_cpu_id; | |
47 | ||
c12a8289 AM |
48 | cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE; |
49 | cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE; | |
1da177e4 LT |
50 | static cpumask_t smp_commenced_mask; |
51 | static cpumask_t cpu_callout_map; | |
52 | ||
53 | void smp_info(struct seq_file *m) | |
54 | { | |
55 | int i; | |
56 | ||
57 | seq_printf(m, "State:\n"); | |
58 | for (i = 0; i < NR_CPUS; i++) { | |
59 | if (cpu_online(i)) | |
60 | seq_printf(m, | |
61 | "CPU%d:\t\tonline\n", i); | |
62 | } | |
63 | } | |
64 | ||
65 | void smp_bogo(struct seq_file *m) | |
66 | { | |
67 | int i; | |
68 | ||
69 | for (i = 0; i < NR_CPUS; i++) | |
70 | if (cpu_online(i)) | |
71 | seq_printf(m, | |
72 | "Cpu%dBogo\t: %lu.%02lu\n" | |
73 | "Cpu%dClkTck\t: %016lx\n", | |
74 | i, cpu_data(i).udelay_val / (500000/HZ), | |
75 | (cpu_data(i).udelay_val / (5000/HZ)) % 100, | |
76 | i, cpu_data(i).clock_tick); | |
77 | } | |
78 | ||
79 | void __init smp_store_cpu_info(int id) | |
80 | { | |
81 | int cpu_node; | |
82 | ||
83 | /* multiplier and counter set by | |
84 | smp_setup_percpu_timer() */ | |
85 | cpu_data(id).udelay_val = loops_per_jiffy; | |
86 | ||
87 | cpu_find_by_mid(id, &cpu_node); | |
88 | cpu_data(id).clock_tick = prom_getintdefault(cpu_node, | |
89 | "clock-frequency", 0); | |
90 | ||
1da177e4 | 91 | cpu_data(id).idle_volume = 1; |
80dc0d6b DM |
92 | |
93 | cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size", | |
94 | 16 * 1024); | |
95 | cpu_data(id).dcache_line_size = | |
96 | prom_getintdefault(cpu_node, "dcache-line-size", 32); | |
97 | cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size", | |
98 | 16 * 1024); | |
99 | cpu_data(id).icache_line_size = | |
100 | prom_getintdefault(cpu_node, "icache-line-size", 32); | |
101 | cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size", | |
102 | 4 * 1024 * 1024); | |
103 | cpu_data(id).ecache_line_size = | |
104 | prom_getintdefault(cpu_node, "ecache-line-size", 64); | |
105 | printk("CPU[%d]: Caches " | |
106 | "D[sz(%d):line_sz(%d)] " | |
107 | "I[sz(%d):line_sz(%d)] " | |
108 | "E[sz(%d):line_sz(%d)]\n", | |
109 | id, | |
110 | cpu_data(id).dcache_size, cpu_data(id).dcache_line_size, | |
111 | cpu_data(id).icache_size, cpu_data(id).icache_line_size, | |
112 | cpu_data(id).ecache_size, cpu_data(id).ecache_line_size); | |
1da177e4 LT |
113 | } |
114 | ||
115 | static void smp_setup_percpu_timer(void); | |
116 | ||
117 | static volatile unsigned long callin_flag = 0; | |
118 | ||
1da177e4 LT |
119 | void __init smp_callin(void) |
120 | { | |
121 | int cpuid = hard_smp_processor_id(); | |
122 | ||
56fb4df6 | 123 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 124 | |
56fb4df6 | 125 | __flush_tlb_all(); |
1da177e4 LT |
126 | |
127 | smp_setup_percpu_timer(); | |
128 | ||
816242da DM |
129 | if (cheetah_pcache_forced_on) |
130 | cheetah_enable_pcache(); | |
131 | ||
1da177e4 LT |
132 | local_irq_enable(); |
133 | ||
134 | calibrate_delay(); | |
135 | smp_store_cpu_info(cpuid); | |
136 | callin_flag = 1; | |
137 | __asm__ __volatile__("membar #Sync\n\t" | |
138 | "flush %%g6" : : : "memory"); | |
139 | ||
140 | /* Clear this or we will die instantly when we | |
141 | * schedule back to this idler... | |
142 | */ | |
db7d9a4e | 143 | current_thread_info()->new_child = 0; |
1da177e4 LT |
144 | |
145 | /* Attach to the address space of init_task. */ | |
146 | atomic_inc(&init_mm.mm_count); | |
147 | current->active_mm = &init_mm; | |
148 | ||
149 | while (!cpu_isset(cpuid, smp_commenced_mask)) | |
4f07118f | 150 | rmb(); |
1da177e4 LT |
151 | |
152 | cpu_set(cpuid, cpu_online_map); | |
5bfb5d69 NP |
153 | |
154 | /* idle thread is expected to have preempt disabled */ | |
155 | preempt_disable(); | |
1da177e4 LT |
156 | } |
157 | ||
158 | void cpu_panic(void) | |
159 | { | |
160 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
161 | panic("SMP bolixed\n"); | |
162 | } | |
163 | ||
d369ddd2 | 164 | static unsigned long current_tick_offset __read_mostly; |
1da177e4 LT |
165 | |
166 | /* This tick register synchronization scheme is taken entirely from | |
167 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
168 | * | |
169 | * The only change I've made is to rework it so that the master | |
170 | * initiates the synchonization instead of the slave. -DaveM | |
171 | */ | |
172 | ||
173 | #define MASTER 0 | |
174 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
175 | ||
176 | #define NUM_ROUNDS 64 /* magic value */ | |
177 | #define NUM_ITERS 5 /* likewise */ | |
178 | ||
179 | static DEFINE_SPINLOCK(itc_sync_lock); | |
180 | static unsigned long go[SLAVE + 1]; | |
181 | ||
182 | #define DEBUG_TICK_SYNC 0 | |
183 | ||
184 | static inline long get_delta (long *rt, long *master) | |
185 | { | |
186 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
187 | unsigned long tcenter, t0, t1, tm; | |
188 | unsigned long i; | |
189 | ||
190 | for (i = 0; i < NUM_ITERS; i++) { | |
191 | t0 = tick_ops->get_tick(); | |
192 | go[MASTER] = 1; | |
4f07118f | 193 | membar_storeload(); |
1da177e4 | 194 | while (!(tm = go[SLAVE])) |
4f07118f | 195 | rmb(); |
1da177e4 | 196 | go[SLAVE] = 0; |
4f07118f | 197 | wmb(); |
1da177e4 LT |
198 | t1 = tick_ops->get_tick(); |
199 | ||
200 | if (t1 - t0 < best_t1 - best_t0) | |
201 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
202 | } | |
203 | ||
204 | *rt = best_t1 - best_t0; | |
205 | *master = best_tm - best_t0; | |
206 | ||
207 | /* average best_t0 and best_t1 without overflow: */ | |
208 | tcenter = (best_t0/2 + best_t1/2); | |
209 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
210 | tcenter++; | |
211 | return tcenter - best_tm; | |
212 | } | |
213 | ||
214 | void smp_synchronize_tick_client(void) | |
215 | { | |
216 | long i, delta, adj, adjust_latency = 0, done = 0; | |
217 | unsigned long flags, rt, master_time_stamp, bound; | |
218 | #if DEBUG_TICK_SYNC | |
219 | struct { | |
220 | long rt; /* roundtrip time */ | |
221 | long master; /* master's timestamp */ | |
222 | long diff; /* difference between midpoint and master's timestamp */ | |
223 | long lat; /* estimate of itc adjustment latency */ | |
224 | } t[NUM_ROUNDS]; | |
225 | #endif | |
226 | ||
227 | go[MASTER] = 1; | |
228 | ||
229 | while (go[MASTER]) | |
4f07118f | 230 | rmb(); |
1da177e4 LT |
231 | |
232 | local_irq_save(flags); | |
233 | { | |
234 | for (i = 0; i < NUM_ROUNDS; i++) { | |
235 | delta = get_delta(&rt, &master_time_stamp); | |
236 | if (delta == 0) { | |
237 | done = 1; /* let's lock on to this... */ | |
238 | bound = rt; | |
239 | } | |
240 | ||
241 | if (!done) { | |
242 | if (i > 0) { | |
243 | adjust_latency += -delta; | |
244 | adj = -delta + adjust_latency/4; | |
245 | } else | |
246 | adj = -delta; | |
247 | ||
248 | tick_ops->add_tick(adj, current_tick_offset); | |
249 | } | |
250 | #if DEBUG_TICK_SYNC | |
251 | t[i].rt = rt; | |
252 | t[i].master = master_time_stamp; | |
253 | t[i].diff = delta; | |
254 | t[i].lat = adjust_latency/4; | |
255 | #endif | |
256 | } | |
257 | } | |
258 | local_irq_restore(flags); | |
259 | ||
260 | #if DEBUG_TICK_SYNC | |
261 | for (i = 0; i < NUM_ROUNDS; i++) | |
262 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
263 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
264 | #endif | |
265 | ||
266 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles," | |
267 | "maxerr %lu cycles)\n", smp_processor_id(), delta, rt); | |
268 | } | |
269 | ||
270 | static void smp_start_sync_tick_client(int cpu); | |
271 | ||
272 | static void smp_synchronize_one_tick(int cpu) | |
273 | { | |
274 | unsigned long flags, i; | |
275 | ||
276 | go[MASTER] = 0; | |
277 | ||
278 | smp_start_sync_tick_client(cpu); | |
279 | ||
280 | /* wait for client to be ready */ | |
281 | while (!go[MASTER]) | |
4f07118f | 282 | rmb(); |
1da177e4 LT |
283 | |
284 | /* now let the client proceed into his loop */ | |
285 | go[MASTER] = 0; | |
4f07118f | 286 | membar_storeload(); |
1da177e4 LT |
287 | |
288 | spin_lock_irqsave(&itc_sync_lock, flags); | |
289 | { | |
290 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
291 | while (!go[MASTER]) | |
4f07118f | 292 | rmb(); |
1da177e4 | 293 | go[MASTER] = 0; |
4f07118f | 294 | wmb(); |
1da177e4 | 295 | go[SLAVE] = tick_ops->get_tick(); |
4f07118f | 296 | membar_storeload(); |
1da177e4 LT |
297 | } |
298 | } | |
299 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
300 | } | |
301 | ||
302 | extern unsigned long sparc64_cpu_startup; | |
303 | ||
304 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
305 | * 32-bits (I think) so to be safe we have it read the pointer | |
306 | * contained here so we work on >4GB machines. -DaveM | |
307 | */ | |
308 | static struct thread_info *cpu_new_thread = NULL; | |
309 | ||
310 | static int __devinit smp_boot_one_cpu(unsigned int cpu) | |
311 | { | |
312 | unsigned long entry = | |
313 | (unsigned long)(&sparc64_cpu_startup); | |
314 | unsigned long cookie = | |
315 | (unsigned long)(&cpu_new_thread); | |
316 | struct task_struct *p; | |
317 | int timeout, ret, cpu_node; | |
318 | ||
319 | p = fork_idle(cpu); | |
320 | callin_flag = 0; | |
f3169641 | 321 | cpu_new_thread = task_thread_info(p); |
1da177e4 LT |
322 | cpu_set(cpu, cpu_callout_map); |
323 | ||
324 | cpu_find_by_mid(cpu, &cpu_node); | |
325 | prom_startcpu(cpu_node, entry, cookie); | |
326 | ||
327 | for (timeout = 0; timeout < 5000000; timeout++) { | |
328 | if (callin_flag) | |
329 | break; | |
330 | udelay(100); | |
331 | } | |
332 | if (callin_flag) { | |
333 | ret = 0; | |
334 | } else { | |
335 | printk("Processor %d is stuck.\n", cpu); | |
336 | cpu_clear(cpu, cpu_callout_map); | |
337 | ret = -ENODEV; | |
338 | } | |
339 | cpu_new_thread = NULL; | |
340 | ||
341 | return ret; | |
342 | } | |
343 | ||
344 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
345 | { | |
346 | u64 result, target; | |
347 | int stuck, tmp; | |
348 | ||
349 | if (this_is_starfire) { | |
350 | /* map to real upaid */ | |
351 | cpu = (((cpu & 0x3c) << 1) | | |
352 | ((cpu & 0x40) >> 4) | | |
353 | (cpu & 0x3)); | |
354 | } | |
355 | ||
356 | target = (cpu << 14) | 0x70; | |
357 | again: | |
358 | /* Ok, this is the real Spitfire Errata #54. | |
359 | * One must read back from a UDB internal register | |
360 | * after writes to the UDB interrupt dispatch, but | |
361 | * before the membar Sync for that write. | |
362 | * So we use the high UDB control register (ASI 0x7f, | |
363 | * ADDR 0x20) for the dummy read. -DaveM | |
364 | */ | |
365 | tmp = 0x40; | |
366 | __asm__ __volatile__( | |
367 | "wrpr %1, %2, %%pstate\n\t" | |
368 | "stxa %4, [%0] %3\n\t" | |
369 | "stxa %5, [%0+%8] %3\n\t" | |
370 | "add %0, %8, %0\n\t" | |
371 | "stxa %6, [%0+%8] %3\n\t" | |
372 | "membar #Sync\n\t" | |
373 | "stxa %%g0, [%7] %3\n\t" | |
374 | "membar #Sync\n\t" | |
375 | "mov 0x20, %%g1\n\t" | |
376 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
377 | "membar #Sync" | |
378 | : "=r" (tmp) | |
379 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
380 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
381 | "r" (0x10), "0" (tmp) | |
382 | : "g1"); | |
383 | ||
384 | /* NOTE: PSTATE_IE is still clear. */ | |
385 | stuck = 100000; | |
386 | do { | |
387 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
388 | : "=r" (result) | |
389 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
390 | if (result == 0) { | |
391 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
392 | : : "r" (pstate)); | |
393 | return; | |
394 | } | |
395 | stuck -= 1; | |
396 | if (stuck == 0) | |
397 | break; | |
398 | } while (result & 0x1); | |
399 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
400 | : : "r" (pstate)); | |
401 | if (stuck == 0) { | |
402 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
403 | smp_processor_id(), result); | |
404 | } else { | |
405 | udelay(2); | |
406 | goto again; | |
407 | } | |
408 | } | |
409 | ||
410 | static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
411 | { | |
412 | u64 pstate; | |
413 | int i; | |
414 | ||
415 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
416 | for_each_cpu_mask(i, mask) | |
417 | spitfire_xcall_helper(data0, data1, data2, pstate, i); | |
418 | } | |
419 | ||
420 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
421 | * packet, but we have no use for that. However we do take advantage of | |
422 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
423 | */ | |
424 | static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
425 | { | |
426 | u64 pstate, ver; | |
92704a1c | 427 | int nack_busy_id, is_jbus; |
1da177e4 LT |
428 | |
429 | if (cpus_empty(mask)) | |
430 | return; | |
431 | ||
432 | /* Unfortunately, someone at Sun had the brilliant idea to make the | |
433 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
434 | * derivative processor. | |
435 | */ | |
436 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
437 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
438 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
439 | |
440 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
441 | ||
442 | retry: | |
443 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" | |
444 | : : "r" (pstate), "i" (PSTATE_IE)); | |
445 | ||
446 | /* Setup the dispatch data registers. */ | |
447 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
448 | "stxa %1, [%4] %6\n\t" | |
449 | "stxa %2, [%5] %6\n\t" | |
450 | "membar #Sync\n\t" | |
451 | : /* no outputs */ | |
452 | : "r" (data0), "r" (data1), "r" (data2), | |
453 | "r" (0x40), "r" (0x50), "r" (0x60), | |
454 | "i" (ASI_INTR_W)); | |
455 | ||
456 | nack_busy_id = 0; | |
457 | { | |
458 | int i; | |
459 | ||
460 | for_each_cpu_mask(i, mask) { | |
461 | u64 target = (i << 14) | 0x70; | |
462 | ||
92704a1c | 463 | if (!is_jbus) |
1da177e4 LT |
464 | target |= (nack_busy_id << 24); |
465 | __asm__ __volatile__( | |
466 | "stxa %%g0, [%0] %1\n\t" | |
467 | "membar #Sync\n\t" | |
468 | : /* no outputs */ | |
469 | : "r" (target), "i" (ASI_INTR_W)); | |
470 | nack_busy_id++; | |
471 | } | |
472 | } | |
473 | ||
474 | /* Now, poll for completion. */ | |
475 | { | |
476 | u64 dispatch_stat; | |
477 | long stuck; | |
478 | ||
479 | stuck = 100000 * nack_busy_id; | |
480 | do { | |
481 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
482 | : "=r" (dispatch_stat) | |
483 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
484 | if (dispatch_stat == 0UL) { | |
485 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
486 | : : "r" (pstate)); | |
487 | return; | |
488 | } | |
489 | if (!--stuck) | |
490 | break; | |
491 | } while (dispatch_stat & 0x5555555555555555UL); | |
492 | ||
493 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
494 | : : "r" (pstate)); | |
495 | ||
496 | if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) { | |
497 | /* Busy bits will not clear, continue instead | |
498 | * of freezing up on this cpu. | |
499 | */ | |
500 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
501 | smp_processor_id(), dispatch_stat); | |
502 | } else { | |
503 | int i, this_busy_nack = 0; | |
504 | ||
505 | /* Delay some random time with interrupts enabled | |
506 | * to prevent deadlock. | |
507 | */ | |
508 | udelay(2 * nack_busy_id); | |
509 | ||
510 | /* Clear out the mask bits for cpus which did not | |
511 | * NACK us. | |
512 | */ | |
513 | for_each_cpu_mask(i, mask) { | |
514 | u64 check_mask; | |
515 | ||
92704a1c | 516 | if (is_jbus) |
1da177e4 LT |
517 | check_mask = (0x2UL << (2*i)); |
518 | else | |
519 | check_mask = (0x2UL << | |
520 | this_busy_nack); | |
521 | if ((dispatch_stat & check_mask) == 0) | |
522 | cpu_clear(i, mask); | |
523 | this_busy_nack += 2; | |
524 | } | |
525 | ||
526 | goto retry; | |
527 | } | |
528 | } | |
529 | } | |
530 | ||
531 | /* Send cross call to all processors mentioned in MASK | |
532 | * except self. | |
533 | */ | |
534 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask) | |
535 | { | |
536 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
537 | int this_cpu = get_cpu(); | |
538 | ||
539 | cpus_and(mask, mask, cpu_online_map); | |
540 | cpu_clear(this_cpu, mask); | |
541 | ||
542 | if (tlb_type == spitfire) | |
543 | spitfire_xcall_deliver(data0, data1, data2, mask); | |
544 | else | |
545 | cheetah_xcall_deliver(data0, data1, data2, mask); | |
546 | /* NOTE: Caller runs local copy on master. */ | |
547 | ||
548 | put_cpu(); | |
549 | } | |
550 | ||
551 | extern unsigned long xcall_sync_tick; | |
552 | ||
553 | static void smp_start_sync_tick_client(int cpu) | |
554 | { | |
555 | cpumask_t mask = cpumask_of_cpu(cpu); | |
556 | ||
557 | smp_cross_call_masked(&xcall_sync_tick, | |
558 | 0, 0, 0, mask); | |
559 | } | |
560 | ||
561 | /* Send cross call to all processors except self. */ | |
562 | #define smp_cross_call(func, ctx, data1, data2) \ | |
563 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map) | |
564 | ||
565 | struct call_data_struct { | |
566 | void (*func) (void *info); | |
567 | void *info; | |
568 | atomic_t finished; | |
569 | int wait; | |
570 | }; | |
571 | ||
572 | static DEFINE_SPINLOCK(call_lock); | |
573 | static struct call_data_struct *call_data; | |
574 | ||
575 | extern unsigned long xcall_call_function; | |
576 | ||
577 | /* | |
578 | * You must not call this function with disabled interrupts or from a | |
579 | * hardware interrupt handler or from a bottom half handler. | |
580 | */ | |
bd40791e DM |
581 | static int smp_call_function_mask(void (*func)(void *info), void *info, |
582 | int nonatomic, int wait, cpumask_t mask) | |
1da177e4 LT |
583 | { |
584 | struct call_data_struct data; | |
bd40791e | 585 | int cpus = cpus_weight(mask) - 1; |
1da177e4 LT |
586 | long timeout; |
587 | ||
588 | if (!cpus) | |
589 | return 0; | |
590 | ||
591 | /* Can deadlock when called with interrupts disabled */ | |
592 | WARN_ON(irqs_disabled()); | |
593 | ||
594 | data.func = func; | |
595 | data.info = info; | |
596 | atomic_set(&data.finished, 0); | |
597 | data.wait = wait; | |
598 | ||
599 | spin_lock(&call_lock); | |
600 | ||
601 | call_data = &data; | |
602 | ||
bd40791e | 603 | smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask); |
1da177e4 LT |
604 | |
605 | /* | |
606 | * Wait for other cpus to complete function or at | |
607 | * least snap the call data. | |
608 | */ | |
609 | timeout = 1000000; | |
610 | while (atomic_read(&data.finished) != cpus) { | |
611 | if (--timeout <= 0) | |
612 | goto out_timeout; | |
613 | barrier(); | |
614 | udelay(1); | |
615 | } | |
616 | ||
617 | spin_unlock(&call_lock); | |
618 | ||
619 | return 0; | |
620 | ||
621 | out_timeout: | |
622 | spin_unlock(&call_lock); | |
623 | printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n", | |
624 | (long) num_online_cpus() - 1L, | |
625 | (long) atomic_read(&data.finished)); | |
626 | return 0; | |
627 | } | |
628 | ||
bd40791e DM |
629 | int smp_call_function(void (*func)(void *info), void *info, |
630 | int nonatomic, int wait) | |
631 | { | |
632 | return smp_call_function_mask(func, info, nonatomic, wait, | |
633 | cpu_online_map); | |
634 | } | |
635 | ||
1da177e4 LT |
636 | void smp_call_function_client(int irq, struct pt_regs *regs) |
637 | { | |
638 | void (*func) (void *info) = call_data->func; | |
639 | void *info = call_data->info; | |
640 | ||
641 | clear_softint(1 << irq); | |
642 | if (call_data->wait) { | |
643 | /* let initiator proceed only after completion */ | |
644 | func(info); | |
645 | atomic_inc(&call_data->finished); | |
646 | } else { | |
647 | /* let initiator proceed after getting data */ | |
648 | atomic_inc(&call_data->finished); | |
649 | func(info); | |
650 | } | |
651 | } | |
652 | ||
bd40791e DM |
653 | static void tsb_sync(void *info) |
654 | { | |
655 | struct mm_struct *mm = info; | |
656 | ||
657 | if (current->active_mm == mm) | |
658 | tsb_context_switch(mm); | |
659 | } | |
660 | ||
661 | void smp_tsb_sync(struct mm_struct *mm) | |
662 | { | |
663 | smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask); | |
664 | } | |
665 | ||
1da177e4 LT |
666 | extern unsigned long xcall_flush_tlb_mm; |
667 | extern unsigned long xcall_flush_tlb_pending; | |
668 | extern unsigned long xcall_flush_tlb_kernel_range; | |
1da177e4 LT |
669 | extern unsigned long xcall_report_regs; |
670 | extern unsigned long xcall_receive_signal; | |
671 | ||
672 | #ifdef DCACHE_ALIASING_POSSIBLE | |
673 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
674 | #endif | |
675 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
676 | ||
677 | #ifdef CONFIG_DEBUG_DCFLUSH | |
678 | extern atomic_t dcpage_flushes; | |
679 | extern atomic_t dcpage_flushes_xcall; | |
680 | #endif | |
681 | ||
682 | static __inline__ void __local_flush_dcache_page(struct page *page) | |
683 | { | |
684 | #ifdef DCACHE_ALIASING_POSSIBLE | |
685 | __flush_dcache_page(page_address(page), | |
686 | ((tlb_type == spitfire) && | |
687 | page_mapping(page) != NULL)); | |
688 | #else | |
689 | if (page_mapping(page) != NULL && | |
690 | tlb_type == spitfire) | |
691 | __flush_icache_page(__pa(page_address(page))); | |
692 | #endif | |
693 | } | |
694 | ||
695 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
696 | { | |
697 | cpumask_t mask = cpumask_of_cpu(cpu); | |
698 | int this_cpu = get_cpu(); | |
699 | ||
700 | #ifdef CONFIG_DEBUG_DCFLUSH | |
701 | atomic_inc(&dcpage_flushes); | |
702 | #endif | |
703 | if (cpu == this_cpu) { | |
704 | __local_flush_dcache_page(page); | |
705 | } else if (cpu_online(cpu)) { | |
706 | void *pg_addr = page_address(page); | |
707 | u64 data0; | |
708 | ||
709 | if (tlb_type == spitfire) { | |
710 | data0 = | |
711 | ((u64)&xcall_flush_dcache_page_spitfire); | |
712 | if (page_mapping(page) != NULL) | |
713 | data0 |= ((u64)1 << 32); | |
714 | spitfire_xcall_deliver(data0, | |
715 | __pa(pg_addr), | |
716 | (u64) pg_addr, | |
717 | mask); | |
718 | } else { | |
719 | #ifdef DCACHE_ALIASING_POSSIBLE | |
720 | data0 = | |
721 | ((u64)&xcall_flush_dcache_page_cheetah); | |
722 | cheetah_xcall_deliver(data0, | |
723 | __pa(pg_addr), | |
724 | 0, mask); | |
725 | #endif | |
726 | } | |
727 | #ifdef CONFIG_DEBUG_DCFLUSH | |
728 | atomic_inc(&dcpage_flushes_xcall); | |
729 | #endif | |
730 | } | |
731 | ||
732 | put_cpu(); | |
733 | } | |
734 | ||
735 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
736 | { | |
737 | void *pg_addr = page_address(page); | |
738 | cpumask_t mask = cpu_online_map; | |
739 | u64 data0; | |
740 | int this_cpu = get_cpu(); | |
741 | ||
742 | cpu_clear(this_cpu, mask); | |
743 | ||
744 | #ifdef CONFIG_DEBUG_DCFLUSH | |
745 | atomic_inc(&dcpage_flushes); | |
746 | #endif | |
747 | if (cpus_empty(mask)) | |
748 | goto flush_self; | |
749 | if (tlb_type == spitfire) { | |
750 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
751 | if (page_mapping(page) != NULL) | |
752 | data0 |= ((u64)1 << 32); | |
753 | spitfire_xcall_deliver(data0, | |
754 | __pa(pg_addr), | |
755 | (u64) pg_addr, | |
756 | mask); | |
757 | } else { | |
758 | #ifdef DCACHE_ALIASING_POSSIBLE | |
759 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
760 | cheetah_xcall_deliver(data0, | |
761 | __pa(pg_addr), | |
762 | 0, mask); | |
763 | #endif | |
764 | } | |
765 | #ifdef CONFIG_DEBUG_DCFLUSH | |
766 | atomic_inc(&dcpage_flushes_xcall); | |
767 | #endif | |
768 | flush_self: | |
769 | __local_flush_dcache_page(page); | |
770 | ||
771 | put_cpu(); | |
772 | } | |
773 | ||
774 | void smp_receive_signal(int cpu) | |
775 | { | |
776 | cpumask_t mask = cpumask_of_cpu(cpu); | |
777 | ||
778 | if (cpu_online(cpu)) { | |
779 | u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff); | |
780 | ||
781 | if (tlb_type == spitfire) | |
782 | spitfire_xcall_deliver(data0, 0, 0, mask); | |
783 | else | |
784 | cheetah_xcall_deliver(data0, 0, 0, mask); | |
785 | } | |
786 | } | |
787 | ||
788 | void smp_receive_signal_client(int irq, struct pt_regs *regs) | |
789 | { | |
790 | /* Just return, rtrap takes care of the rest. */ | |
791 | clear_softint(1 << irq); | |
792 | } | |
793 | ||
794 | void smp_report_regs(void) | |
795 | { | |
796 | smp_cross_call(&xcall_report_regs, 0, 0, 0); | |
797 | } | |
798 | ||
1da177e4 LT |
799 | /* We know that the window frames of the user have been flushed |
800 | * to the stack before we get here because all callers of us | |
801 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
802 | * which performs the flushw. | |
803 | * | |
804 | * The SMP TLB coherency scheme we use works as follows: | |
805 | * | |
806 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
807 | * space has (potentially) executed on, this is the heuristic | |
808 | * we use to avoid doing cross calls. | |
809 | * | |
810 | * Also, for flushing from kswapd and also for clones, we | |
811 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
812 | * | |
813 | * 2) TLB context numbers are shared globally across all processors | |
814 | * in the system, this allows us to play several games to avoid | |
815 | * cross calls. | |
816 | * | |
817 | * One invariant is that when a cpu switches to a process, and | |
818 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
819 | * current cpu's bit set, that tlb context is flushed locally. | |
820 | * | |
821 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
822 | * cross calls when we want to flush the currently running process's | |
823 | * tlb state. This is done by clearing all cpu bits except the current | |
824 | * processor's in current->active_mm->cpu_vm_mask and performing the | |
825 | * flush locally only. This will force any subsequent cpus which run | |
826 | * this task to flush the context from the local tlb if the process | |
827 | * migrates to another cpu (again). | |
828 | * | |
829 | * 3) For shared address spaces (threads) and swapping we bite the | |
830 | * bullet for most cases and perform the cross call (but only to | |
831 | * the cpus listed in cpu_vm_mask). | |
832 | * | |
833 | * The performance gain from "optimizing" away the cross call for threads is | |
834 | * questionable (in theory the big win for threads is the massive sharing of | |
835 | * address space state across processors). | |
836 | */ | |
62dbec78 DM |
837 | |
838 | /* This currently is only used by the hugetlb arch pre-fault | |
839 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
840 | * bits of the context register for an address space. | |
841 | */ | |
1da177e4 LT |
842 | void smp_flush_tlb_mm(struct mm_struct *mm) |
843 | { | |
62dbec78 DM |
844 | u32 ctx = CTX_HWBITS(mm->context); |
845 | int cpu = get_cpu(); | |
1da177e4 | 846 | |
62dbec78 DM |
847 | if (atomic_read(&mm->mm_users) == 1) { |
848 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); | |
849 | goto local_flush_and_out; | |
850 | } | |
1da177e4 | 851 | |
62dbec78 DM |
852 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
853 | ctx, 0, 0, | |
854 | mm->cpu_vm_mask); | |
1da177e4 | 855 | |
62dbec78 DM |
856 | local_flush_and_out: |
857 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 858 | |
62dbec78 | 859 | put_cpu(); |
1da177e4 LT |
860 | } |
861 | ||
862 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) | |
863 | { | |
864 | u32 ctx = CTX_HWBITS(mm->context); | |
865 | int cpu = get_cpu(); | |
866 | ||
dedeb002 | 867 | if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) |
1da177e4 | 868 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); |
dedeb002 HD |
869 | else |
870 | smp_cross_call_masked(&xcall_flush_tlb_pending, | |
871 | ctx, nr, (unsigned long) vaddrs, | |
872 | mm->cpu_vm_mask); | |
1da177e4 | 873 | |
1da177e4 LT |
874 | __flush_tlb_pending(ctx, nr, vaddrs); |
875 | ||
876 | put_cpu(); | |
877 | } | |
878 | ||
879 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
880 | { | |
881 | start &= PAGE_MASK; | |
882 | end = PAGE_ALIGN(end); | |
883 | if (start != end) { | |
884 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
885 | 0, start, end); | |
886 | ||
887 | __flush_tlb_kernel_range(start, end); | |
888 | } | |
889 | } | |
890 | ||
891 | /* CPU capture. */ | |
892 | /* #define CAPTURE_DEBUG */ | |
893 | extern unsigned long xcall_capture; | |
894 | ||
895 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
896 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
897 | static unsigned long penguins_are_doing_time; | |
898 | ||
899 | void smp_capture(void) | |
900 | { | |
901 | int result = atomic_add_ret(1, &smp_capture_depth); | |
902 | ||
903 | if (result == 1) { | |
904 | int ncpus = num_online_cpus(); | |
905 | ||
906 | #ifdef CAPTURE_DEBUG | |
907 | printk("CPU[%d]: Sending penguins to jail...", | |
908 | smp_processor_id()); | |
909 | #endif | |
910 | penguins_are_doing_time = 1; | |
4f07118f | 911 | membar_storestore_loadstore(); |
1da177e4 LT |
912 | atomic_inc(&smp_capture_registry); |
913 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
914 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 915 | rmb(); |
1da177e4 LT |
916 | #ifdef CAPTURE_DEBUG |
917 | printk("done\n"); | |
918 | #endif | |
919 | } | |
920 | } | |
921 | ||
922 | void smp_release(void) | |
923 | { | |
924 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
925 | #ifdef CAPTURE_DEBUG | |
926 | printk("CPU[%d]: Giving pardon to " | |
927 | "imprisoned penguins\n", | |
928 | smp_processor_id()); | |
929 | #endif | |
930 | penguins_are_doing_time = 0; | |
4f07118f | 931 | membar_storeload_storestore(); |
1da177e4 LT |
932 | atomic_dec(&smp_capture_registry); |
933 | } | |
934 | } | |
935 | ||
936 | /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they | |
937 | * can service tlb flush xcalls... | |
938 | */ | |
939 | extern void prom_world(int); | |
96c6e0d8 | 940 | |
1da177e4 LT |
941 | void smp_penguin_jailcell(int irq, struct pt_regs *regs) |
942 | { | |
1da177e4 LT |
943 | clear_softint(1 << irq); |
944 | ||
945 | preempt_disable(); | |
946 | ||
947 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
948 | prom_world(1); |
949 | atomic_inc(&smp_capture_registry); | |
4f07118f | 950 | membar_storeload_storestore(); |
1da177e4 | 951 | while (penguins_are_doing_time) |
4f07118f | 952 | rmb(); |
1da177e4 LT |
953 | atomic_dec(&smp_capture_registry); |
954 | prom_world(0); | |
955 | ||
956 | preempt_enable(); | |
957 | } | |
958 | ||
1da177e4 LT |
959 | #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier |
960 | #define prof_counter(__cpu) cpu_data(__cpu).counter | |
961 | ||
962 | void smp_percpu_timer_interrupt(struct pt_regs *regs) | |
963 | { | |
964 | unsigned long compare, tick, pstate; | |
965 | int cpu = smp_processor_id(); | |
966 | int user = user_mode(regs); | |
967 | ||
968 | /* | |
969 | * Check for level 14 softint. | |
970 | */ | |
971 | { | |
972 | unsigned long tick_mask = tick_ops->softint_mask; | |
973 | ||
974 | if (!(get_softint() & tick_mask)) { | |
975 | extern void handler_irq(int, struct pt_regs *); | |
976 | ||
977 | handler_irq(14, regs); | |
978 | return; | |
979 | } | |
980 | clear_softint(tick_mask); | |
981 | } | |
982 | ||
983 | do { | |
984 | profile_tick(CPU_PROFILING, regs); | |
985 | if (!--prof_counter(cpu)) { | |
986 | irq_enter(); | |
987 | ||
988 | if (cpu == boot_cpu_id) { | |
989 | kstat_this_cpu.irqs[0]++; | |
990 | timer_tick_interrupt(regs); | |
991 | } | |
992 | ||
993 | update_process_times(user); | |
994 | ||
995 | irq_exit(); | |
996 | ||
997 | prof_counter(cpu) = prof_multiplier(cpu); | |
998 | } | |
999 | ||
1000 | /* Guarantee that the following sequences execute | |
1001 | * uninterrupted. | |
1002 | */ | |
1003 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
1004 | "wrpr %0, %1, %%pstate" | |
1005 | : "=r" (pstate) | |
1006 | : "i" (PSTATE_IE)); | |
1007 | ||
1008 | compare = tick_ops->add_compare(current_tick_offset); | |
1009 | tick = tick_ops->get_tick(); | |
1010 | ||
1011 | /* Restore PSTATE_IE. */ | |
1012 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
1013 | : /* no outputs */ | |
1014 | : "r" (pstate)); | |
1015 | } while (time_after_eq(tick, compare)); | |
1016 | } | |
1017 | ||
1018 | static void __init smp_setup_percpu_timer(void) | |
1019 | { | |
1020 | int cpu = smp_processor_id(); | |
1021 | unsigned long pstate; | |
1022 | ||
1023 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
1024 | ||
1025 | /* Guarantee that the following sequences execute | |
1026 | * uninterrupted. | |
1027 | */ | |
1028 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
1029 | "wrpr %0, %1, %%pstate" | |
1030 | : "=r" (pstate) | |
1031 | : "i" (PSTATE_IE)); | |
1032 | ||
1033 | tick_ops->init_tick(current_tick_offset); | |
1034 | ||
1035 | /* Restore PSTATE_IE. */ | |
1036 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
1037 | : /* no outputs */ | |
1038 | : "r" (pstate)); | |
1039 | } | |
1040 | ||
1041 | void __init smp_tick_init(void) | |
1042 | { | |
1043 | boot_cpu_id = hard_smp_processor_id(); | |
1044 | current_tick_offset = timer_tick_offset; | |
1045 | ||
1046 | cpu_set(boot_cpu_id, cpu_online_map); | |
1047 | prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1; | |
1048 | } | |
1049 | ||
1050 | /* /proc/profile writes can call this, don't __init it please. */ | |
1051 | static DEFINE_SPINLOCK(prof_setup_lock); | |
1052 | ||
1053 | int setup_profiling_timer(unsigned int multiplier) | |
1054 | { | |
1055 | unsigned long flags; | |
1056 | int i; | |
1057 | ||
1058 | if ((!multiplier) || (timer_tick_offset / multiplier) < 1000) | |
1059 | return -EINVAL; | |
1060 | ||
1061 | spin_lock_irqsave(&prof_setup_lock, flags); | |
1062 | for (i = 0; i < NR_CPUS; i++) | |
1063 | prof_multiplier(i) = multiplier; | |
1064 | current_tick_offset = (timer_tick_offset / multiplier); | |
1065 | spin_unlock_irqrestore(&prof_setup_lock, flags); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
7abea921 | 1070 | /* Constrain the number of cpus to max_cpus. */ |
1da177e4 LT |
1071 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1072 | { | |
1da177e4 | 1073 | if (num_possible_cpus() > max_cpus) { |
7abea921 DM |
1074 | int instance, mid; |
1075 | ||
1da177e4 LT |
1076 | instance = 0; |
1077 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1078 | if (mid != boot_cpu_id) { | |
1079 | cpu_clear(mid, phys_cpu_present_map); | |
1080 | if (num_possible_cpus() <= max_cpus) | |
1081 | break; | |
1082 | } | |
1083 | instance++; | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | smp_store_cpu_info(boot_cpu_id); | |
1088 | } | |
1089 | ||
7abea921 DM |
1090 | /* Set this up early so that things like the scheduler can init |
1091 | * properly. We use the same cpu mask for both the present and | |
1092 | * possible cpu map. | |
1093 | */ | |
1094 | void __init smp_setup_cpu_possible_map(void) | |
1095 | { | |
1096 | int instance, mid; | |
1097 | ||
1098 | instance = 0; | |
1099 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1100 | if (mid < NR_CPUS) | |
1101 | cpu_set(mid, phys_cpu_present_map); | |
1102 | instance++; | |
1103 | } | |
1104 | } | |
1105 | ||
1da177e4 LT |
1106 | void __devinit smp_prepare_boot_cpu(void) |
1107 | { | |
56fb4df6 DM |
1108 | int cpu = hard_smp_processor_id(); |
1109 | ||
1110 | if (cpu >= NR_CPUS) { | |
1da177e4 LT |
1111 | prom_printf("Serious problem, boot cpu id >= NR_CPUS\n"); |
1112 | prom_halt(); | |
1113 | } | |
1114 | ||
56fb4df6 DM |
1115 | current_thread_info()->cpu = cpu; |
1116 | __local_per_cpu_offset = __per_cpu_offset(cpu); | |
1da177e4 LT |
1117 | |
1118 | cpu_set(smp_processor_id(), cpu_online_map); | |
1119 | cpu_set(smp_processor_id(), phys_cpu_present_map); | |
1120 | } | |
1121 | ||
1122 | int __devinit __cpu_up(unsigned int cpu) | |
1123 | { | |
1124 | int ret = smp_boot_one_cpu(cpu); | |
1125 | ||
1126 | if (!ret) { | |
1127 | cpu_set(cpu, smp_commenced_mask); | |
1128 | while (!cpu_isset(cpu, cpu_online_map)) | |
1129 | mb(); | |
1130 | if (!cpu_isset(cpu, cpu_online_map)) { | |
1131 | ret = -ENODEV; | |
1132 | } else { | |
1133 | smp_synchronize_one_tick(cpu); | |
1134 | } | |
1135 | } | |
1136 | return ret; | |
1137 | } | |
1138 | ||
1139 | void __init smp_cpus_done(unsigned int max_cpus) | |
1140 | { | |
1141 | unsigned long bogosum = 0; | |
1142 | int i; | |
1143 | ||
1144 | for (i = 0; i < NR_CPUS; i++) { | |
1145 | if (cpu_online(i)) | |
1146 | bogosum += cpu_data(i).udelay_val; | |
1147 | } | |
1148 | printk("Total of %ld processors activated " | |
1149 | "(%lu.%02lu BogoMIPS).\n", | |
1150 | (long) num_online_cpus(), | |
1151 | bogosum/(500000/HZ), | |
1152 | (bogosum/(5000/HZ))%100); | |
1153 | } | |
1154 | ||
1da177e4 LT |
1155 | void smp_send_reschedule(int cpu) |
1156 | { | |
64c7c8f8 | 1157 | smp_receive_signal(cpu); |
1da177e4 LT |
1158 | } |
1159 | ||
1160 | /* This is a nop because we capture all other cpus | |
1161 | * anyways when making the PROM active. | |
1162 | */ | |
1163 | void smp_send_stop(void) | |
1164 | { | |
1165 | } | |
1166 | ||
d369ddd2 DM |
1167 | unsigned long __per_cpu_base __read_mostly; |
1168 | unsigned long __per_cpu_shift __read_mostly; | |
1da177e4 LT |
1169 | |
1170 | EXPORT_SYMBOL(__per_cpu_base); | |
1171 | EXPORT_SYMBOL(__per_cpu_shift); | |
1172 | ||
1173 | void __init setup_per_cpu_areas(void) | |
1174 | { | |
1175 | unsigned long goal, size, i; | |
1176 | char *ptr; | |
1da177e4 LT |
1177 | |
1178 | /* Copy section for each CPU (we discard the original) */ | |
56fb4df6 | 1179 | goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES); |
1da177e4 LT |
1180 | #ifdef CONFIG_MODULES |
1181 | if (goal < PERCPU_ENOUGH_ROOM) | |
1182 | goal = PERCPU_ENOUGH_ROOM; | |
1183 | #endif | |
1184 | __per_cpu_shift = 0; | |
1185 | for (size = 1UL; size < goal; size <<= 1UL) | |
1186 | __per_cpu_shift++; | |
1187 | ||
56fb4df6 | 1188 | ptr = alloc_bootmem(size * NR_CPUS); |
1da177e4 LT |
1189 | |
1190 | __per_cpu_base = ptr - __per_cpu_start; | |
1191 | ||
1da177e4 LT |
1192 | for (i = 0; i < NR_CPUS; i++, ptr += size) |
1193 | memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); | |
1da177e4 | 1194 | } |