Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
3 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/seq_file.h> | |
20 | #include <linux/cache.h> | |
21 | #include <linux/jiffies.h> | |
22 | #include <linux/profile.h> | |
23 | #include <linux/bootmem.h> | |
24 | ||
25 | #include <asm/head.h> | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/atomic.h> | |
28 | #include <asm/tlbflush.h> | |
29 | #include <asm/mmu_context.h> | |
30 | #include <asm/cpudata.h> | |
31 | ||
32 | #include <asm/irq.h> | |
6d24c8dc | 33 | #include <asm/irq_regs.h> |
1da177e4 LT |
34 | #include <asm/page.h> |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/timer.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/tlb.h> | |
56fb4df6 | 41 | #include <asm/sections.h> |
07f8e5f3 | 42 | #include <asm/prom.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | extern void calibrate_delay(void); |
45 | ||
46 | /* Please don't make this stuff initdata!!! --DaveM */ | |
777a4475 | 47 | unsigned char boot_cpu_id; |
1da177e4 | 48 | |
c12a8289 AM |
49 | cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE; |
50 | cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE; | |
8935dced DM |
51 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly = |
52 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
1da177e4 LT |
53 | static cpumask_t smp_commenced_mask; |
54 | static cpumask_t cpu_callout_map; | |
55 | ||
56 | void smp_info(struct seq_file *m) | |
57 | { | |
58 | int i; | |
59 | ||
60 | seq_printf(m, "State:\n"); | |
394e3902 AM |
61 | for_each_online_cpu(i) |
62 | seq_printf(m, "CPU%d:\t\tonline\n", i); | |
1da177e4 LT |
63 | } |
64 | ||
65 | void smp_bogo(struct seq_file *m) | |
66 | { | |
67 | int i; | |
68 | ||
394e3902 AM |
69 | for_each_online_cpu(i) |
70 | seq_printf(m, | |
71 | "Cpu%dBogo\t: %lu.%02lu\n" | |
72 | "Cpu%dClkTck\t: %016lx\n", | |
73 | i, cpu_data(i).udelay_val / (500000/HZ), | |
74 | (cpu_data(i).udelay_val / (5000/HZ)) % 100, | |
75 | i, cpu_data(i).clock_tick); | |
1da177e4 LT |
76 | } |
77 | ||
78 | void __init smp_store_cpu_info(int id) | |
79 | { | |
07f8e5f3 DM |
80 | struct device_node *dp; |
81 | int def; | |
1da177e4 | 82 | |
1da177e4 LT |
83 | cpu_data(id).udelay_val = loops_per_jiffy; |
84 | ||
07f8e5f3 DM |
85 | cpu_find_by_mid(id, &dp); |
86 | cpu_data(id).clock_tick = | |
87 | of_getintprop_default(dp, "clock-frequency", 0); | |
1da177e4 | 88 | |
f03b8a54 | 89 | def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024)); |
07f8e5f3 DM |
90 | cpu_data(id).dcache_size = |
91 | of_getintprop_default(dp, "dcache-size", def); | |
f03b8a54 DM |
92 | |
93 | def = 32; | |
80dc0d6b | 94 | cpu_data(id).dcache_line_size = |
07f8e5f3 | 95 | of_getintprop_default(dp, "dcache-line-size", def); |
f03b8a54 DM |
96 | |
97 | def = 16 * 1024; | |
07f8e5f3 DM |
98 | cpu_data(id).icache_size = |
99 | of_getintprop_default(dp, "icache-size", def); | |
f03b8a54 DM |
100 | |
101 | def = 32; | |
80dc0d6b | 102 | cpu_data(id).icache_line_size = |
07f8e5f3 | 103 | of_getintprop_default(dp, "icache-line-size", def); |
f03b8a54 DM |
104 | |
105 | def = ((tlb_type == hypervisor) ? | |
106 | (3 * 1024 * 1024) : | |
107 | (4 * 1024 * 1024)); | |
07f8e5f3 DM |
108 | cpu_data(id).ecache_size = |
109 | of_getintprop_default(dp, "ecache-size", def); | |
f03b8a54 DM |
110 | |
111 | def = 64; | |
80dc0d6b | 112 | cpu_data(id).ecache_line_size = |
07f8e5f3 | 113 | of_getintprop_default(dp, "ecache-line-size", def); |
f03b8a54 | 114 | |
80dc0d6b DM |
115 | printk("CPU[%d]: Caches " |
116 | "D[sz(%d):line_sz(%d)] " | |
117 | "I[sz(%d):line_sz(%d)] " | |
118 | "E[sz(%d):line_sz(%d)]\n", | |
119 | id, | |
120 | cpu_data(id).dcache_size, cpu_data(id).dcache_line_size, | |
121 | cpu_data(id).icache_size, cpu_data(id).icache_line_size, | |
122 | cpu_data(id).ecache_size, cpu_data(id).ecache_line_size); | |
1da177e4 LT |
123 | } |
124 | ||
112f4871 | 125 | extern void setup_sparc64_timer(void); |
1da177e4 LT |
126 | |
127 | static volatile unsigned long callin_flag = 0; | |
128 | ||
1da177e4 LT |
129 | void __init smp_callin(void) |
130 | { | |
131 | int cpuid = hard_smp_processor_id(); | |
132 | ||
56fb4df6 | 133 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 134 | |
4a07e646 | 135 | if (tlb_type == hypervisor) |
490384e7 | 136 | sun4v_ktsb_register(); |
481295f9 | 137 | |
56fb4df6 | 138 | __flush_tlb_all(); |
1da177e4 | 139 | |
112f4871 | 140 | setup_sparc64_timer(); |
1da177e4 | 141 | |
816242da DM |
142 | if (cheetah_pcache_forced_on) |
143 | cheetah_enable_pcache(); | |
144 | ||
1da177e4 LT |
145 | local_irq_enable(); |
146 | ||
147 | calibrate_delay(); | |
148 | smp_store_cpu_info(cpuid); | |
149 | callin_flag = 1; | |
150 | __asm__ __volatile__("membar #Sync\n\t" | |
151 | "flush %%g6" : : : "memory"); | |
152 | ||
153 | /* Clear this or we will die instantly when we | |
154 | * schedule back to this idler... | |
155 | */ | |
db7d9a4e | 156 | current_thread_info()->new_child = 0; |
1da177e4 LT |
157 | |
158 | /* Attach to the address space of init_task. */ | |
159 | atomic_inc(&init_mm.mm_count); | |
160 | current->active_mm = &init_mm; | |
161 | ||
162 | while (!cpu_isset(cpuid, smp_commenced_mask)) | |
4f07118f | 163 | rmb(); |
1da177e4 LT |
164 | |
165 | cpu_set(cpuid, cpu_online_map); | |
5bfb5d69 NP |
166 | |
167 | /* idle thread is expected to have preempt disabled */ | |
168 | preempt_disable(); | |
1da177e4 LT |
169 | } |
170 | ||
171 | void cpu_panic(void) | |
172 | { | |
173 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
174 | panic("SMP bolixed\n"); | |
175 | } | |
176 | ||
1da177e4 LT |
177 | /* This tick register synchronization scheme is taken entirely from |
178 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
179 | * | |
180 | * The only change I've made is to rework it so that the master | |
181 | * initiates the synchonization instead of the slave. -DaveM | |
182 | */ | |
183 | ||
184 | #define MASTER 0 | |
185 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
186 | ||
187 | #define NUM_ROUNDS 64 /* magic value */ | |
188 | #define NUM_ITERS 5 /* likewise */ | |
189 | ||
190 | static DEFINE_SPINLOCK(itc_sync_lock); | |
191 | static unsigned long go[SLAVE + 1]; | |
192 | ||
193 | #define DEBUG_TICK_SYNC 0 | |
194 | ||
195 | static inline long get_delta (long *rt, long *master) | |
196 | { | |
197 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
198 | unsigned long tcenter, t0, t1, tm; | |
199 | unsigned long i; | |
200 | ||
201 | for (i = 0; i < NUM_ITERS; i++) { | |
202 | t0 = tick_ops->get_tick(); | |
203 | go[MASTER] = 1; | |
4f07118f | 204 | membar_storeload(); |
1da177e4 | 205 | while (!(tm = go[SLAVE])) |
4f07118f | 206 | rmb(); |
1da177e4 | 207 | go[SLAVE] = 0; |
4f07118f | 208 | wmb(); |
1da177e4 LT |
209 | t1 = tick_ops->get_tick(); |
210 | ||
211 | if (t1 - t0 < best_t1 - best_t0) | |
212 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
213 | } | |
214 | ||
215 | *rt = best_t1 - best_t0; | |
216 | *master = best_tm - best_t0; | |
217 | ||
218 | /* average best_t0 and best_t1 without overflow: */ | |
219 | tcenter = (best_t0/2 + best_t1/2); | |
220 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
221 | tcenter++; | |
222 | return tcenter - best_tm; | |
223 | } | |
224 | ||
225 | void smp_synchronize_tick_client(void) | |
226 | { | |
227 | long i, delta, adj, adjust_latency = 0, done = 0; | |
228 | unsigned long flags, rt, master_time_stamp, bound; | |
229 | #if DEBUG_TICK_SYNC | |
230 | struct { | |
231 | long rt; /* roundtrip time */ | |
232 | long master; /* master's timestamp */ | |
233 | long diff; /* difference between midpoint and master's timestamp */ | |
234 | long lat; /* estimate of itc adjustment latency */ | |
235 | } t[NUM_ROUNDS]; | |
236 | #endif | |
237 | ||
238 | go[MASTER] = 1; | |
239 | ||
240 | while (go[MASTER]) | |
4f07118f | 241 | rmb(); |
1da177e4 LT |
242 | |
243 | local_irq_save(flags); | |
244 | { | |
245 | for (i = 0; i < NUM_ROUNDS; i++) { | |
246 | delta = get_delta(&rt, &master_time_stamp); | |
247 | if (delta == 0) { | |
248 | done = 1; /* let's lock on to this... */ | |
249 | bound = rt; | |
250 | } | |
251 | ||
252 | if (!done) { | |
253 | if (i > 0) { | |
254 | adjust_latency += -delta; | |
255 | adj = -delta + adjust_latency/4; | |
256 | } else | |
257 | adj = -delta; | |
258 | ||
112f4871 | 259 | tick_ops->add_tick(adj); |
1da177e4 LT |
260 | } |
261 | #if DEBUG_TICK_SYNC | |
262 | t[i].rt = rt; | |
263 | t[i].master = master_time_stamp; | |
264 | t[i].diff = delta; | |
265 | t[i].lat = adjust_latency/4; | |
266 | #endif | |
267 | } | |
268 | } | |
269 | local_irq_restore(flags); | |
270 | ||
271 | #if DEBUG_TICK_SYNC | |
272 | for (i = 0; i < NUM_ROUNDS; i++) | |
273 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
274 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
275 | #endif | |
276 | ||
277 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles," | |
278 | "maxerr %lu cycles)\n", smp_processor_id(), delta, rt); | |
279 | } | |
280 | ||
281 | static void smp_start_sync_tick_client(int cpu); | |
282 | ||
283 | static void smp_synchronize_one_tick(int cpu) | |
284 | { | |
285 | unsigned long flags, i; | |
286 | ||
287 | go[MASTER] = 0; | |
288 | ||
289 | smp_start_sync_tick_client(cpu); | |
290 | ||
291 | /* wait for client to be ready */ | |
292 | while (!go[MASTER]) | |
4f07118f | 293 | rmb(); |
1da177e4 LT |
294 | |
295 | /* now let the client proceed into his loop */ | |
296 | go[MASTER] = 0; | |
4f07118f | 297 | membar_storeload(); |
1da177e4 LT |
298 | |
299 | spin_lock_irqsave(&itc_sync_lock, flags); | |
300 | { | |
301 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
302 | while (!go[MASTER]) | |
4f07118f | 303 | rmb(); |
1da177e4 | 304 | go[MASTER] = 0; |
4f07118f | 305 | wmb(); |
1da177e4 | 306 | go[SLAVE] = tick_ops->get_tick(); |
4f07118f | 307 | membar_storeload(); |
1da177e4 LT |
308 | } |
309 | } | |
310 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
311 | } | |
312 | ||
72aff53f DM |
313 | extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load); |
314 | ||
1da177e4 LT |
315 | extern unsigned long sparc64_cpu_startup; |
316 | ||
317 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
318 | * 32-bits (I think) so to be safe we have it read the pointer | |
319 | * contained here so we work on >4GB machines. -DaveM | |
320 | */ | |
321 | static struct thread_info *cpu_new_thread = NULL; | |
322 | ||
323 | static int __devinit smp_boot_one_cpu(unsigned int cpu) | |
324 | { | |
325 | unsigned long entry = | |
326 | (unsigned long)(&sparc64_cpu_startup); | |
327 | unsigned long cookie = | |
328 | (unsigned long)(&cpu_new_thread); | |
329 | struct task_struct *p; | |
7890f794 | 330 | int timeout, ret; |
1da177e4 LT |
331 | |
332 | p = fork_idle(cpu); | |
333 | callin_flag = 0; | |
f3169641 | 334 | cpu_new_thread = task_thread_info(p); |
1da177e4 LT |
335 | cpu_set(cpu, cpu_callout_map); |
336 | ||
7890f794 | 337 | if (tlb_type == hypervisor) { |
72aff53f DM |
338 | /* Alloc the mondo queues, cpu will load them. */ |
339 | sun4v_init_mondo_queues(0, cpu, 1, 0); | |
340 | ||
7890f794 DM |
341 | prom_startcpu_cpuid(cpu, entry, cookie); |
342 | } else { | |
07f8e5f3 | 343 | struct device_node *dp; |
7890f794 | 344 | |
07f8e5f3 DM |
345 | cpu_find_by_mid(cpu, &dp); |
346 | prom_startcpu(dp->node, entry, cookie); | |
7890f794 | 347 | } |
1da177e4 LT |
348 | |
349 | for (timeout = 0; timeout < 5000000; timeout++) { | |
350 | if (callin_flag) | |
351 | break; | |
352 | udelay(100); | |
353 | } | |
72aff53f | 354 | |
1da177e4 LT |
355 | if (callin_flag) { |
356 | ret = 0; | |
357 | } else { | |
358 | printk("Processor %d is stuck.\n", cpu); | |
359 | cpu_clear(cpu, cpu_callout_map); | |
360 | ret = -ENODEV; | |
361 | } | |
362 | cpu_new_thread = NULL; | |
363 | ||
364 | return ret; | |
365 | } | |
366 | ||
367 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
368 | { | |
369 | u64 result, target; | |
370 | int stuck, tmp; | |
371 | ||
372 | if (this_is_starfire) { | |
373 | /* map to real upaid */ | |
374 | cpu = (((cpu & 0x3c) << 1) | | |
375 | ((cpu & 0x40) >> 4) | | |
376 | (cpu & 0x3)); | |
377 | } | |
378 | ||
379 | target = (cpu << 14) | 0x70; | |
380 | again: | |
381 | /* Ok, this is the real Spitfire Errata #54. | |
382 | * One must read back from a UDB internal register | |
383 | * after writes to the UDB interrupt dispatch, but | |
384 | * before the membar Sync for that write. | |
385 | * So we use the high UDB control register (ASI 0x7f, | |
386 | * ADDR 0x20) for the dummy read. -DaveM | |
387 | */ | |
388 | tmp = 0x40; | |
389 | __asm__ __volatile__( | |
390 | "wrpr %1, %2, %%pstate\n\t" | |
391 | "stxa %4, [%0] %3\n\t" | |
392 | "stxa %5, [%0+%8] %3\n\t" | |
393 | "add %0, %8, %0\n\t" | |
394 | "stxa %6, [%0+%8] %3\n\t" | |
395 | "membar #Sync\n\t" | |
396 | "stxa %%g0, [%7] %3\n\t" | |
397 | "membar #Sync\n\t" | |
398 | "mov 0x20, %%g1\n\t" | |
399 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
400 | "membar #Sync" | |
401 | : "=r" (tmp) | |
402 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
403 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
404 | "r" (0x10), "0" (tmp) | |
405 | : "g1"); | |
406 | ||
407 | /* NOTE: PSTATE_IE is still clear. */ | |
408 | stuck = 100000; | |
409 | do { | |
410 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
411 | : "=r" (result) | |
412 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
413 | if (result == 0) { | |
414 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
415 | : : "r" (pstate)); | |
416 | return; | |
417 | } | |
418 | stuck -= 1; | |
419 | if (stuck == 0) | |
420 | break; | |
421 | } while (result & 0x1); | |
422 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
423 | : : "r" (pstate)); | |
424 | if (stuck == 0) { | |
425 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
426 | smp_processor_id(), result); | |
427 | } else { | |
428 | udelay(2); | |
429 | goto again; | |
430 | } | |
431 | } | |
432 | ||
433 | static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
434 | { | |
435 | u64 pstate; | |
436 | int i; | |
437 | ||
438 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
439 | for_each_cpu_mask(i, mask) | |
440 | spitfire_xcall_helper(data0, data1, data2, pstate, i); | |
441 | } | |
442 | ||
443 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
444 | * packet, but we have no use for that. However we do take advantage of | |
445 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
446 | */ | |
447 | static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
448 | { | |
449 | u64 pstate, ver; | |
92704a1c | 450 | int nack_busy_id, is_jbus; |
1da177e4 LT |
451 | |
452 | if (cpus_empty(mask)) | |
453 | return; | |
454 | ||
455 | /* Unfortunately, someone at Sun had the brilliant idea to make the | |
456 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
457 | * derivative processor. | |
458 | */ | |
459 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
460 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
461 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
462 | |
463 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
464 | ||
465 | retry: | |
466 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" | |
467 | : : "r" (pstate), "i" (PSTATE_IE)); | |
468 | ||
469 | /* Setup the dispatch data registers. */ | |
470 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
471 | "stxa %1, [%4] %6\n\t" | |
472 | "stxa %2, [%5] %6\n\t" | |
473 | "membar #Sync\n\t" | |
474 | : /* no outputs */ | |
475 | : "r" (data0), "r" (data1), "r" (data2), | |
476 | "r" (0x40), "r" (0x50), "r" (0x60), | |
477 | "i" (ASI_INTR_W)); | |
478 | ||
479 | nack_busy_id = 0; | |
480 | { | |
481 | int i; | |
482 | ||
483 | for_each_cpu_mask(i, mask) { | |
484 | u64 target = (i << 14) | 0x70; | |
485 | ||
92704a1c | 486 | if (!is_jbus) |
1da177e4 LT |
487 | target |= (nack_busy_id << 24); |
488 | __asm__ __volatile__( | |
489 | "stxa %%g0, [%0] %1\n\t" | |
490 | "membar #Sync\n\t" | |
491 | : /* no outputs */ | |
492 | : "r" (target), "i" (ASI_INTR_W)); | |
493 | nack_busy_id++; | |
494 | } | |
495 | } | |
496 | ||
497 | /* Now, poll for completion. */ | |
498 | { | |
499 | u64 dispatch_stat; | |
500 | long stuck; | |
501 | ||
502 | stuck = 100000 * nack_busy_id; | |
503 | do { | |
504 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
505 | : "=r" (dispatch_stat) | |
506 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
507 | if (dispatch_stat == 0UL) { | |
508 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
509 | : : "r" (pstate)); | |
510 | return; | |
511 | } | |
512 | if (!--stuck) | |
513 | break; | |
514 | } while (dispatch_stat & 0x5555555555555555UL); | |
515 | ||
516 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
517 | : : "r" (pstate)); | |
518 | ||
519 | if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) { | |
520 | /* Busy bits will not clear, continue instead | |
521 | * of freezing up on this cpu. | |
522 | */ | |
523 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
524 | smp_processor_id(), dispatch_stat); | |
525 | } else { | |
526 | int i, this_busy_nack = 0; | |
527 | ||
528 | /* Delay some random time with interrupts enabled | |
529 | * to prevent deadlock. | |
530 | */ | |
531 | udelay(2 * nack_busy_id); | |
532 | ||
533 | /* Clear out the mask bits for cpus which did not | |
534 | * NACK us. | |
535 | */ | |
536 | for_each_cpu_mask(i, mask) { | |
537 | u64 check_mask; | |
538 | ||
92704a1c | 539 | if (is_jbus) |
1da177e4 LT |
540 | check_mask = (0x2UL << (2*i)); |
541 | else | |
542 | check_mask = (0x2UL << | |
543 | this_busy_nack); | |
544 | if ((dispatch_stat & check_mask) == 0) | |
545 | cpu_clear(i, mask); | |
546 | this_busy_nack += 2; | |
547 | } | |
548 | ||
549 | goto retry; | |
550 | } | |
551 | } | |
552 | } | |
553 | ||
1d2f1f90 | 554 | /* Multi-cpu list version. */ |
a43fe0e7 DM |
555 | static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) |
556 | { | |
b830ab66 DM |
557 | struct trap_per_cpu *tb; |
558 | u16 *cpu_list; | |
559 | u64 *mondo; | |
560 | cpumask_t error_mask; | |
561 | unsigned long flags, status; | |
3cab0c3e | 562 | int cnt, retries, this_cpu, prev_sent, i; |
b830ab66 DM |
563 | |
564 | /* We have to do this whole thing with interrupts fully disabled. | |
565 | * Otherwise if we send an xcall from interrupt context it will | |
566 | * corrupt both our mondo block and cpu list state. | |
567 | * | |
568 | * One consequence of this is that we cannot use timeout mechanisms | |
569 | * that depend upon interrupts being delivered locally. So, for | |
570 | * example, we cannot sample jiffies and expect it to advance. | |
571 | * | |
572 | * Fortunately, udelay() uses %stick/%tick so we can use that. | |
573 | */ | |
574 | local_irq_save(flags); | |
575 | ||
576 | this_cpu = smp_processor_id(); | |
577 | tb = &trap_block[this_cpu]; | |
1d2f1f90 | 578 | |
b830ab66 | 579 | mondo = __va(tb->cpu_mondo_block_pa); |
1d2f1f90 DM |
580 | mondo[0] = data0; |
581 | mondo[1] = data1; | |
582 | mondo[2] = data2; | |
583 | wmb(); | |
584 | ||
b830ab66 DM |
585 | cpu_list = __va(tb->cpu_list_pa); |
586 | ||
587 | /* Setup the initial cpu list. */ | |
588 | cnt = 0; | |
589 | for_each_cpu_mask(i, mask) | |
590 | cpu_list[cnt++] = i; | |
591 | ||
592 | cpus_clear(error_mask); | |
1d2f1f90 | 593 | retries = 0; |
3cab0c3e | 594 | prev_sent = 0; |
1d2f1f90 | 595 | do { |
3cab0c3e | 596 | int forward_progress, n_sent; |
1d2f1f90 | 597 | |
b830ab66 DM |
598 | status = sun4v_cpu_mondo_send(cnt, |
599 | tb->cpu_list_pa, | |
600 | tb->cpu_mondo_block_pa); | |
601 | ||
602 | /* HV_EOK means all cpus received the xcall, we're done. */ | |
603 | if (likely(status == HV_EOK)) | |
1d2f1f90 | 604 | break; |
b830ab66 | 605 | |
3cab0c3e DM |
606 | /* First, see if we made any forward progress. |
607 | * | |
608 | * The hypervisor indicates successful sends by setting | |
609 | * cpu list entries to the value 0xffff. | |
b830ab66 | 610 | */ |
3cab0c3e | 611 | n_sent = 0; |
b830ab66 | 612 | for (i = 0; i < cnt; i++) { |
3cab0c3e DM |
613 | if (likely(cpu_list[i] == 0xffff)) |
614 | n_sent++; | |
1d2f1f90 DM |
615 | } |
616 | ||
3cab0c3e DM |
617 | forward_progress = 0; |
618 | if (n_sent > prev_sent) | |
619 | forward_progress = 1; | |
620 | ||
621 | prev_sent = n_sent; | |
622 | ||
b830ab66 DM |
623 | /* If we get a HV_ECPUERROR, then one or more of the cpus |
624 | * in the list are in error state. Use the cpu_state() | |
625 | * hypervisor call to find out which cpus are in error state. | |
626 | */ | |
627 | if (unlikely(status == HV_ECPUERROR)) { | |
628 | for (i = 0; i < cnt; i++) { | |
629 | long err; | |
630 | u16 cpu; | |
631 | ||
632 | cpu = cpu_list[i]; | |
633 | if (cpu == 0xffff) | |
634 | continue; | |
635 | ||
636 | err = sun4v_cpu_state(cpu); | |
637 | if (err >= 0 && | |
638 | err == HV_CPU_STATE_ERROR) { | |
3cab0c3e | 639 | cpu_list[i] = 0xffff; |
b830ab66 DM |
640 | cpu_set(cpu, error_mask); |
641 | } | |
642 | } | |
643 | } else if (unlikely(status != HV_EWOULDBLOCK)) | |
644 | goto fatal_mondo_error; | |
645 | ||
3cab0c3e DM |
646 | /* Don't bother rewriting the CPU list, just leave the |
647 | * 0xffff and non-0xffff entries in there and the | |
648 | * hypervisor will do the right thing. | |
649 | * | |
650 | * Only advance timeout state if we didn't make any | |
651 | * forward progress. | |
652 | */ | |
b830ab66 DM |
653 | if (unlikely(!forward_progress)) { |
654 | if (unlikely(++retries > 10000)) | |
655 | goto fatal_mondo_timeout; | |
656 | ||
657 | /* Delay a little bit to let other cpus catch up | |
658 | * on their cpu mondo queue work. | |
659 | */ | |
660 | udelay(2 * cnt); | |
661 | } | |
1d2f1f90 DM |
662 | } while (1); |
663 | ||
b830ab66 DM |
664 | local_irq_restore(flags); |
665 | ||
666 | if (unlikely(!cpus_empty(error_mask))) | |
667 | goto fatal_mondo_cpu_error; | |
668 | ||
669 | return; | |
670 | ||
671 | fatal_mondo_cpu_error: | |
672 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus " | |
673 | "were in error state\n", | |
674 | this_cpu); | |
675 | printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu); | |
676 | for_each_cpu_mask(i, error_mask) | |
677 | printk("%d ", i); | |
678 | printk("]\n"); | |
679 | return; | |
680 | ||
681 | fatal_mondo_timeout: | |
682 | local_irq_restore(flags); | |
683 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward " | |
684 | " progress after %d retries.\n", | |
685 | this_cpu, retries); | |
686 | goto dump_cpu_list_and_out; | |
687 | ||
688 | fatal_mondo_error: | |
689 | local_irq_restore(flags); | |
690 | printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n", | |
691 | this_cpu, status); | |
692 | printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) " | |
693 | "mondo_block_pa(%lx)\n", | |
694 | this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa); | |
695 | ||
696 | dump_cpu_list_and_out: | |
697 | printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu); | |
698 | for (i = 0; i < cnt; i++) | |
699 | printk("%u ", cpu_list[i]); | |
700 | printk("]\n"); | |
1d2f1f90 | 701 | } |
a43fe0e7 | 702 | |
1da177e4 LT |
703 | /* Send cross call to all processors mentioned in MASK |
704 | * except self. | |
705 | */ | |
706 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask) | |
707 | { | |
708 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
709 | int this_cpu = get_cpu(); | |
710 | ||
711 | cpus_and(mask, mask, cpu_online_map); | |
712 | cpu_clear(this_cpu, mask); | |
713 | ||
714 | if (tlb_type == spitfire) | |
715 | spitfire_xcall_deliver(data0, data1, data2, mask); | |
a43fe0e7 | 716 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
1da177e4 | 717 | cheetah_xcall_deliver(data0, data1, data2, mask); |
a43fe0e7 DM |
718 | else |
719 | hypervisor_xcall_deliver(data0, data1, data2, mask); | |
1da177e4 LT |
720 | /* NOTE: Caller runs local copy on master. */ |
721 | ||
722 | put_cpu(); | |
723 | } | |
724 | ||
725 | extern unsigned long xcall_sync_tick; | |
726 | ||
727 | static void smp_start_sync_tick_client(int cpu) | |
728 | { | |
729 | cpumask_t mask = cpumask_of_cpu(cpu); | |
730 | ||
731 | smp_cross_call_masked(&xcall_sync_tick, | |
732 | 0, 0, 0, mask); | |
733 | } | |
734 | ||
735 | /* Send cross call to all processors except self. */ | |
736 | #define smp_cross_call(func, ctx, data1, data2) \ | |
737 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map) | |
738 | ||
739 | struct call_data_struct { | |
740 | void (*func) (void *info); | |
741 | void *info; | |
742 | atomic_t finished; | |
743 | int wait; | |
744 | }; | |
745 | ||
aa1d1a0a | 746 | static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock); |
1da177e4 LT |
747 | static struct call_data_struct *call_data; |
748 | ||
749 | extern unsigned long xcall_call_function; | |
750 | ||
aa1d1a0a DM |
751 | /** |
752 | * smp_call_function(): Run a function on all other CPUs. | |
753 | * @func: The function to run. This must be fast and non-blocking. | |
754 | * @info: An arbitrary pointer to pass to the function. | |
755 | * @nonatomic: currently unused. | |
756 | * @wait: If true, wait (atomically) until function has completed on other CPUs. | |
757 | * | |
758 | * Returns 0 on success, else a negative status code. Does not return until | |
759 | * remote CPUs are nearly ready to execute <<func>> or are or have executed. | |
760 | * | |
1da177e4 LT |
761 | * You must not call this function with disabled interrupts or from a |
762 | * hardware interrupt handler or from a bottom half handler. | |
763 | */ | |
bd40791e DM |
764 | static int smp_call_function_mask(void (*func)(void *info), void *info, |
765 | int nonatomic, int wait, cpumask_t mask) | |
1da177e4 LT |
766 | { |
767 | struct call_data_struct data; | |
ee29074d | 768 | int cpus; |
1da177e4 | 769 | |
1da177e4 LT |
770 | /* Can deadlock when called with interrupts disabled */ |
771 | WARN_ON(irqs_disabled()); | |
772 | ||
773 | data.func = func; | |
774 | data.info = info; | |
775 | atomic_set(&data.finished, 0); | |
776 | data.wait = wait; | |
777 | ||
778 | spin_lock(&call_lock); | |
779 | ||
ee29074d DM |
780 | cpu_clear(smp_processor_id(), mask); |
781 | cpus = cpus_weight(mask); | |
782 | if (!cpus) | |
783 | goto out_unlock; | |
784 | ||
1da177e4 | 785 | call_data = &data; |
aa1d1a0a | 786 | mb(); |
1da177e4 | 787 | |
bd40791e | 788 | smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask); |
1da177e4 | 789 | |
aa1d1a0a DM |
790 | /* Wait for response */ |
791 | while (atomic_read(&data.finished) != cpus) | |
792 | cpu_relax(); | |
1da177e4 | 793 | |
ee29074d | 794 | out_unlock: |
1da177e4 LT |
795 | spin_unlock(&call_lock); |
796 | ||
797 | return 0; | |
1da177e4 LT |
798 | } |
799 | ||
bd40791e DM |
800 | int smp_call_function(void (*func)(void *info), void *info, |
801 | int nonatomic, int wait) | |
802 | { | |
803 | return smp_call_function_mask(func, info, nonatomic, wait, | |
804 | cpu_online_map); | |
805 | } | |
806 | ||
1da177e4 LT |
807 | void smp_call_function_client(int irq, struct pt_regs *regs) |
808 | { | |
809 | void (*func) (void *info) = call_data->func; | |
810 | void *info = call_data->info; | |
811 | ||
812 | clear_softint(1 << irq); | |
813 | if (call_data->wait) { | |
814 | /* let initiator proceed only after completion */ | |
815 | func(info); | |
816 | atomic_inc(&call_data->finished); | |
817 | } else { | |
818 | /* let initiator proceed after getting data */ | |
819 | atomic_inc(&call_data->finished); | |
820 | func(info); | |
821 | } | |
822 | } | |
823 | ||
bd40791e DM |
824 | static void tsb_sync(void *info) |
825 | { | |
6f25f398 | 826 | struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()]; |
bd40791e DM |
827 | struct mm_struct *mm = info; |
828 | ||
6f25f398 DM |
829 | /* It is not valid to test "currrent->active_mm == mm" here. |
830 | * | |
831 | * The value of "current" is not changed atomically with | |
832 | * switch_mm(). But that's OK, we just need to check the | |
833 | * current cpu's trap block PGD physical address. | |
834 | */ | |
835 | if (tp->pgd_paddr == __pa(mm->pgd)) | |
bd40791e DM |
836 | tsb_context_switch(mm); |
837 | } | |
838 | ||
839 | void smp_tsb_sync(struct mm_struct *mm) | |
840 | { | |
841 | smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask); | |
842 | } | |
843 | ||
1da177e4 LT |
844 | extern unsigned long xcall_flush_tlb_mm; |
845 | extern unsigned long xcall_flush_tlb_pending; | |
846 | extern unsigned long xcall_flush_tlb_kernel_range; | |
1da177e4 LT |
847 | extern unsigned long xcall_report_regs; |
848 | extern unsigned long xcall_receive_signal; | |
ee29074d | 849 | extern unsigned long xcall_new_mmu_context_version; |
1da177e4 LT |
850 | |
851 | #ifdef DCACHE_ALIASING_POSSIBLE | |
852 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
853 | #endif | |
854 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
855 | ||
856 | #ifdef CONFIG_DEBUG_DCFLUSH | |
857 | extern atomic_t dcpage_flushes; | |
858 | extern atomic_t dcpage_flushes_xcall; | |
859 | #endif | |
860 | ||
861 | static __inline__ void __local_flush_dcache_page(struct page *page) | |
862 | { | |
863 | #ifdef DCACHE_ALIASING_POSSIBLE | |
864 | __flush_dcache_page(page_address(page), | |
865 | ((tlb_type == spitfire) && | |
866 | page_mapping(page) != NULL)); | |
867 | #else | |
868 | if (page_mapping(page) != NULL && | |
869 | tlb_type == spitfire) | |
870 | __flush_icache_page(__pa(page_address(page))); | |
871 | #endif | |
872 | } | |
873 | ||
874 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
875 | { | |
876 | cpumask_t mask = cpumask_of_cpu(cpu); | |
a43fe0e7 DM |
877 | int this_cpu; |
878 | ||
879 | if (tlb_type == hypervisor) | |
880 | return; | |
1da177e4 LT |
881 | |
882 | #ifdef CONFIG_DEBUG_DCFLUSH | |
883 | atomic_inc(&dcpage_flushes); | |
884 | #endif | |
a43fe0e7 DM |
885 | |
886 | this_cpu = get_cpu(); | |
887 | ||
1da177e4 LT |
888 | if (cpu == this_cpu) { |
889 | __local_flush_dcache_page(page); | |
890 | } else if (cpu_online(cpu)) { | |
891 | void *pg_addr = page_address(page); | |
892 | u64 data0; | |
893 | ||
894 | if (tlb_type == spitfire) { | |
895 | data0 = | |
896 | ((u64)&xcall_flush_dcache_page_spitfire); | |
897 | if (page_mapping(page) != NULL) | |
898 | data0 |= ((u64)1 << 32); | |
899 | spitfire_xcall_deliver(data0, | |
900 | __pa(pg_addr), | |
901 | (u64) pg_addr, | |
902 | mask); | |
a43fe0e7 | 903 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
904 | #ifdef DCACHE_ALIASING_POSSIBLE |
905 | data0 = | |
906 | ((u64)&xcall_flush_dcache_page_cheetah); | |
907 | cheetah_xcall_deliver(data0, | |
908 | __pa(pg_addr), | |
909 | 0, mask); | |
910 | #endif | |
911 | } | |
912 | #ifdef CONFIG_DEBUG_DCFLUSH | |
913 | atomic_inc(&dcpage_flushes_xcall); | |
914 | #endif | |
915 | } | |
916 | ||
917 | put_cpu(); | |
918 | } | |
919 | ||
920 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
921 | { | |
922 | void *pg_addr = page_address(page); | |
923 | cpumask_t mask = cpu_online_map; | |
924 | u64 data0; | |
a43fe0e7 DM |
925 | int this_cpu; |
926 | ||
927 | if (tlb_type == hypervisor) | |
928 | return; | |
929 | ||
930 | this_cpu = get_cpu(); | |
1da177e4 LT |
931 | |
932 | cpu_clear(this_cpu, mask); | |
933 | ||
934 | #ifdef CONFIG_DEBUG_DCFLUSH | |
935 | atomic_inc(&dcpage_flushes); | |
936 | #endif | |
937 | if (cpus_empty(mask)) | |
938 | goto flush_self; | |
939 | if (tlb_type == spitfire) { | |
940 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
941 | if (page_mapping(page) != NULL) | |
942 | data0 |= ((u64)1 << 32); | |
943 | spitfire_xcall_deliver(data0, | |
944 | __pa(pg_addr), | |
945 | (u64) pg_addr, | |
946 | mask); | |
a43fe0e7 | 947 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
948 | #ifdef DCACHE_ALIASING_POSSIBLE |
949 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
950 | cheetah_xcall_deliver(data0, | |
951 | __pa(pg_addr), | |
952 | 0, mask); | |
953 | #endif | |
954 | } | |
955 | #ifdef CONFIG_DEBUG_DCFLUSH | |
956 | atomic_inc(&dcpage_flushes_xcall); | |
957 | #endif | |
958 | flush_self: | |
959 | __local_flush_dcache_page(page); | |
960 | ||
961 | put_cpu(); | |
962 | } | |
963 | ||
a0663a79 DM |
964 | static void __smp_receive_signal_mask(cpumask_t mask) |
965 | { | |
966 | smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask); | |
967 | } | |
968 | ||
1da177e4 LT |
969 | void smp_receive_signal(int cpu) |
970 | { | |
971 | cpumask_t mask = cpumask_of_cpu(cpu); | |
972 | ||
a0663a79 DM |
973 | if (cpu_online(cpu)) |
974 | __smp_receive_signal_mask(mask); | |
1da177e4 LT |
975 | } |
976 | ||
977 | void smp_receive_signal_client(int irq, struct pt_regs *regs) | |
ee29074d DM |
978 | { |
979 | clear_softint(1 << irq); | |
980 | } | |
981 | ||
982 | void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs) | |
1da177e4 | 983 | { |
a0663a79 | 984 | struct mm_struct *mm; |
ee29074d | 985 | unsigned long flags; |
a0663a79 | 986 | |
1da177e4 | 987 | clear_softint(1 << irq); |
a0663a79 DM |
988 | |
989 | /* See if we need to allocate a new TLB context because | |
990 | * the version of the one we are using is now out of date. | |
991 | */ | |
992 | mm = current->active_mm; | |
ee29074d DM |
993 | if (unlikely(!mm || (mm == &init_mm))) |
994 | return; | |
a0663a79 | 995 | |
ee29074d | 996 | spin_lock_irqsave(&mm->context.lock, flags); |
aac0aadf | 997 | |
ee29074d DM |
998 | if (unlikely(!CTX_VALID(mm->context))) |
999 | get_new_mmu_context(mm); | |
aac0aadf | 1000 | |
ee29074d | 1001 | spin_unlock_irqrestore(&mm->context.lock, flags); |
aac0aadf | 1002 | |
ee29074d DM |
1003 | load_secondary_context(mm); |
1004 | __flush_tlb_mm(CTX_HWBITS(mm->context), | |
1005 | SECONDARY_CONTEXT); | |
a0663a79 DM |
1006 | } |
1007 | ||
1008 | void smp_new_mmu_context_version(void) | |
1009 | { | |
ee29074d | 1010 | smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0); |
1da177e4 LT |
1011 | } |
1012 | ||
1013 | void smp_report_regs(void) | |
1014 | { | |
1015 | smp_cross_call(&xcall_report_regs, 0, 0, 0); | |
1016 | } | |
1017 | ||
1da177e4 LT |
1018 | /* We know that the window frames of the user have been flushed |
1019 | * to the stack before we get here because all callers of us | |
1020 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
1021 | * which performs the flushw. | |
1022 | * | |
1023 | * The SMP TLB coherency scheme we use works as follows: | |
1024 | * | |
1025 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
1026 | * space has (potentially) executed on, this is the heuristic | |
1027 | * we use to avoid doing cross calls. | |
1028 | * | |
1029 | * Also, for flushing from kswapd and also for clones, we | |
1030 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
1031 | * | |
1032 | * 2) TLB context numbers are shared globally across all processors | |
1033 | * in the system, this allows us to play several games to avoid | |
1034 | * cross calls. | |
1035 | * | |
1036 | * One invariant is that when a cpu switches to a process, and | |
1037 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
1038 | * current cpu's bit set, that tlb context is flushed locally. | |
1039 | * | |
1040 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
1041 | * cross calls when we want to flush the currently running process's | |
1042 | * tlb state. This is done by clearing all cpu bits except the current | |
1043 | * processor's in current->active_mm->cpu_vm_mask and performing the | |
1044 | * flush locally only. This will force any subsequent cpus which run | |
1045 | * this task to flush the context from the local tlb if the process | |
1046 | * migrates to another cpu (again). | |
1047 | * | |
1048 | * 3) For shared address spaces (threads) and swapping we bite the | |
1049 | * bullet for most cases and perform the cross call (but only to | |
1050 | * the cpus listed in cpu_vm_mask). | |
1051 | * | |
1052 | * The performance gain from "optimizing" away the cross call for threads is | |
1053 | * questionable (in theory the big win for threads is the massive sharing of | |
1054 | * address space state across processors). | |
1055 | */ | |
62dbec78 DM |
1056 | |
1057 | /* This currently is only used by the hugetlb arch pre-fault | |
1058 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
1059 | * bits of the context register for an address space. | |
1060 | */ | |
1da177e4 LT |
1061 | void smp_flush_tlb_mm(struct mm_struct *mm) |
1062 | { | |
62dbec78 DM |
1063 | u32 ctx = CTX_HWBITS(mm->context); |
1064 | int cpu = get_cpu(); | |
1da177e4 | 1065 | |
62dbec78 DM |
1066 | if (atomic_read(&mm->mm_users) == 1) { |
1067 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); | |
1068 | goto local_flush_and_out; | |
1069 | } | |
1da177e4 | 1070 | |
62dbec78 DM |
1071 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
1072 | ctx, 0, 0, | |
1073 | mm->cpu_vm_mask); | |
1da177e4 | 1074 | |
62dbec78 DM |
1075 | local_flush_and_out: |
1076 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 1077 | |
62dbec78 | 1078 | put_cpu(); |
1da177e4 LT |
1079 | } |
1080 | ||
1081 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) | |
1082 | { | |
1083 | u32 ctx = CTX_HWBITS(mm->context); | |
1084 | int cpu = get_cpu(); | |
1085 | ||
dedeb002 | 1086 | if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) |
1da177e4 | 1087 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); |
dedeb002 HD |
1088 | else |
1089 | smp_cross_call_masked(&xcall_flush_tlb_pending, | |
1090 | ctx, nr, (unsigned long) vaddrs, | |
1091 | mm->cpu_vm_mask); | |
1da177e4 | 1092 | |
1da177e4 LT |
1093 | __flush_tlb_pending(ctx, nr, vaddrs); |
1094 | ||
1095 | put_cpu(); | |
1096 | } | |
1097 | ||
1098 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
1099 | { | |
1100 | start &= PAGE_MASK; | |
1101 | end = PAGE_ALIGN(end); | |
1102 | if (start != end) { | |
1103 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1104 | 0, start, end); | |
1105 | ||
1106 | __flush_tlb_kernel_range(start, end); | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | /* CPU capture. */ | |
1111 | /* #define CAPTURE_DEBUG */ | |
1112 | extern unsigned long xcall_capture; | |
1113 | ||
1114 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1115 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1116 | static unsigned long penguins_are_doing_time; | |
1117 | ||
1118 | void smp_capture(void) | |
1119 | { | |
1120 | int result = atomic_add_ret(1, &smp_capture_depth); | |
1121 | ||
1122 | if (result == 1) { | |
1123 | int ncpus = num_online_cpus(); | |
1124 | ||
1125 | #ifdef CAPTURE_DEBUG | |
1126 | printk("CPU[%d]: Sending penguins to jail...", | |
1127 | smp_processor_id()); | |
1128 | #endif | |
1129 | penguins_are_doing_time = 1; | |
4f07118f | 1130 | membar_storestore_loadstore(); |
1da177e4 LT |
1131 | atomic_inc(&smp_capture_registry); |
1132 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1133 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1134 | rmb(); |
1da177e4 LT |
1135 | #ifdef CAPTURE_DEBUG |
1136 | printk("done\n"); | |
1137 | #endif | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | void smp_release(void) | |
1142 | { | |
1143 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1144 | #ifdef CAPTURE_DEBUG | |
1145 | printk("CPU[%d]: Giving pardon to " | |
1146 | "imprisoned penguins\n", | |
1147 | smp_processor_id()); | |
1148 | #endif | |
1149 | penguins_are_doing_time = 0; | |
4f07118f | 1150 | membar_storeload_storestore(); |
1da177e4 LT |
1151 | atomic_dec(&smp_capture_registry); |
1152 | } | |
1153 | } | |
1154 | ||
1155 | /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they | |
1156 | * can service tlb flush xcalls... | |
1157 | */ | |
1158 | extern void prom_world(int); | |
96c6e0d8 | 1159 | |
1da177e4 LT |
1160 | void smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1161 | { | |
1da177e4 LT |
1162 | clear_softint(1 << irq); |
1163 | ||
1164 | preempt_disable(); | |
1165 | ||
1166 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1167 | prom_world(1); |
1168 | atomic_inc(&smp_capture_registry); | |
4f07118f | 1169 | membar_storeload_storestore(); |
1da177e4 | 1170 | while (penguins_are_doing_time) |
4f07118f | 1171 | rmb(); |
1da177e4 LT |
1172 | atomic_dec(&smp_capture_registry); |
1173 | prom_world(0); | |
1174 | ||
1175 | preempt_enable(); | |
1176 | } | |
1177 | ||
1da177e4 LT |
1178 | void __init smp_tick_init(void) |
1179 | { | |
1180 | boot_cpu_id = hard_smp_processor_id(); | |
1da177e4 LT |
1181 | } |
1182 | ||
1183 | /* /proc/profile writes can call this, don't __init it please. */ | |
1da177e4 LT |
1184 | int setup_profiling_timer(unsigned int multiplier) |
1185 | { | |
777a4475 | 1186 | return -EINVAL; |
1da177e4 LT |
1187 | } |
1188 | ||
9145bcf6 DM |
1189 | static void __init smp_tune_scheduling(void) |
1190 | { | |
07f8e5f3 DM |
1191 | struct device_node *dp; |
1192 | int instance; | |
9145bcf6 DM |
1193 | unsigned int def, smallest = ~0U; |
1194 | ||
1195 | def = ((tlb_type == hypervisor) ? | |
1196 | (3 * 1024 * 1024) : | |
1197 | (4 * 1024 * 1024)); | |
1198 | ||
1199 | instance = 0; | |
07f8e5f3 | 1200 | while (!cpu_find_by_instance(instance, &dp, NULL)) { |
9145bcf6 DM |
1201 | unsigned int val; |
1202 | ||
07f8e5f3 | 1203 | val = of_getintprop_default(dp, "ecache-size", def); |
9145bcf6 DM |
1204 | if (val < smallest) |
1205 | smallest = val; | |
1206 | ||
1207 | instance++; | |
1208 | } | |
1209 | ||
1210 | /* Any value less than 256K is nonsense. */ | |
1211 | if (smallest < (256U * 1024U)) | |
1212 | smallest = 256 * 1024; | |
1213 | ||
1214 | max_cache_size = smallest; | |
1215 | ||
1216 | if (smallest < 1U * 1024U * 1024U) | |
1217 | printk(KERN_INFO "Using max_cache_size of %uKB\n", | |
1218 | smallest / 1024U); | |
1219 | else | |
1220 | printk(KERN_INFO "Using max_cache_size of %uMB\n", | |
1221 | smallest / 1024U / 1024U); | |
1222 | } | |
1223 | ||
7abea921 | 1224 | /* Constrain the number of cpus to max_cpus. */ |
1da177e4 LT |
1225 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1226 | { | |
8935dced DM |
1227 | int i; |
1228 | ||
1da177e4 | 1229 | if (num_possible_cpus() > max_cpus) { |
7abea921 DM |
1230 | int instance, mid; |
1231 | ||
1da177e4 LT |
1232 | instance = 0; |
1233 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1234 | if (mid != boot_cpu_id) { | |
1235 | cpu_clear(mid, phys_cpu_present_map); | |
7d3aee9a | 1236 | cpu_clear(mid, cpu_present_map); |
1da177e4 LT |
1237 | if (num_possible_cpus() <= max_cpus) |
1238 | break; | |
1239 | } | |
1240 | instance++; | |
1241 | } | |
1242 | } | |
1243 | ||
a283a525 | 1244 | for_each_possible_cpu(i) { |
8935dced DM |
1245 | if (tlb_type == hypervisor) { |
1246 | int j; | |
1247 | ||
1248 | /* XXX get this mapping from machine description */ | |
a283a525 | 1249 | for_each_possible_cpu(j) { |
8935dced DM |
1250 | if ((j >> 2) == (i >> 2)) |
1251 | cpu_set(j, cpu_sibling_map[i]); | |
1252 | } | |
1253 | } else { | |
1254 | cpu_set(i, cpu_sibling_map[i]); | |
1255 | } | |
1256 | } | |
1257 | ||
1da177e4 | 1258 | smp_store_cpu_info(boot_cpu_id); |
9145bcf6 | 1259 | smp_tune_scheduling(); |
1da177e4 LT |
1260 | } |
1261 | ||
7abea921 DM |
1262 | /* Set this up early so that things like the scheduler can init |
1263 | * properly. We use the same cpu mask for both the present and | |
1264 | * possible cpu map. | |
1265 | */ | |
1266 | void __init smp_setup_cpu_possible_map(void) | |
1267 | { | |
1268 | int instance, mid; | |
1269 | ||
1270 | instance = 0; | |
1271 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
7d3aee9a | 1272 | if (mid < NR_CPUS) { |
7abea921 | 1273 | cpu_set(mid, phys_cpu_present_map); |
7d3aee9a DM |
1274 | cpu_set(mid, cpu_present_map); |
1275 | } | |
7abea921 DM |
1276 | instance++; |
1277 | } | |
1278 | } | |
1279 | ||
1da177e4 LT |
1280 | void __devinit smp_prepare_boot_cpu(void) |
1281 | { | |
1da177e4 LT |
1282 | } |
1283 | ||
b282b6f8 | 1284 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
1285 | { |
1286 | int ret = smp_boot_one_cpu(cpu); | |
1287 | ||
1288 | if (!ret) { | |
1289 | cpu_set(cpu, smp_commenced_mask); | |
1290 | while (!cpu_isset(cpu, cpu_online_map)) | |
1291 | mb(); | |
1292 | if (!cpu_isset(cpu, cpu_online_map)) { | |
1293 | ret = -ENODEV; | |
1294 | } else { | |
02fead75 DM |
1295 | /* On SUN4V, writes to %tick and %stick are |
1296 | * not allowed. | |
1297 | */ | |
1298 | if (tlb_type != hypervisor) | |
1299 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1300 | } |
1301 | } | |
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | void __init smp_cpus_done(unsigned int max_cpus) | |
1306 | { | |
1307 | unsigned long bogosum = 0; | |
1308 | int i; | |
1309 | ||
394e3902 AM |
1310 | for_each_online_cpu(i) |
1311 | bogosum += cpu_data(i).udelay_val; | |
1da177e4 LT |
1312 | printk("Total of %ld processors activated " |
1313 | "(%lu.%02lu BogoMIPS).\n", | |
1314 | (long) num_online_cpus(), | |
1315 | bogosum/(500000/HZ), | |
1316 | (bogosum/(5000/HZ))%100); | |
1317 | } | |
1318 | ||
1da177e4 LT |
1319 | void smp_send_reschedule(int cpu) |
1320 | { | |
64c7c8f8 | 1321 | smp_receive_signal(cpu); |
1da177e4 LT |
1322 | } |
1323 | ||
1324 | /* This is a nop because we capture all other cpus | |
1325 | * anyways when making the PROM active. | |
1326 | */ | |
1327 | void smp_send_stop(void) | |
1328 | { | |
1329 | } | |
1330 | ||
d369ddd2 DM |
1331 | unsigned long __per_cpu_base __read_mostly; |
1332 | unsigned long __per_cpu_shift __read_mostly; | |
1da177e4 LT |
1333 | |
1334 | EXPORT_SYMBOL(__per_cpu_base); | |
1335 | EXPORT_SYMBOL(__per_cpu_shift); | |
1336 | ||
1337 | void __init setup_per_cpu_areas(void) | |
1338 | { | |
1339 | unsigned long goal, size, i; | |
1340 | char *ptr; | |
1da177e4 LT |
1341 | |
1342 | /* Copy section for each CPU (we discard the original) */ | |
5a089006 DM |
1343 | goal = PERCPU_ENOUGH_ROOM; |
1344 | ||
b6e3590f JF |
1345 | __per_cpu_shift = PAGE_SHIFT; |
1346 | for (size = PAGE_SIZE; size < goal; size <<= 1UL) | |
1da177e4 LT |
1347 | __per_cpu_shift++; |
1348 | ||
b6e3590f | 1349 | ptr = alloc_bootmem_pages(size * NR_CPUS); |
1da177e4 LT |
1350 | |
1351 | __per_cpu_base = ptr - __per_cpu_start; | |
1352 | ||
1da177e4 LT |
1353 | for (i = 0; i < NR_CPUS; i++, ptr += size) |
1354 | memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); | |
951bc82c DM |
1355 | |
1356 | /* Setup %g5 for the boot cpu. */ | |
1357 | __local_per_cpu_offset = __per_cpu_offset(smp_processor_id()); | |
1da177e4 | 1358 | } |