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[SPARC64]: Disable smp_report_regs() for now.
[deliverable/linux.git] / arch / sparc64 / kernel / trampoline.S
CommitLineData
1da177e4
LT		 1/* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
2 * trampoline.S: Jump start slave processors on sparc64.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#include <asm/head.h>
8#include <asm/asi.h>
9#include <asm/lsu.h>
10#include <asm/dcr.h>
11#include <asm/dcu.h>
12#include <asm/pstate.h>
13#include <asm/page.h>
14#include <asm/pgtable.h>
15#include <asm/spitfire.h>
16#include <asm/processor.h>
17#include <asm/thread_info.h>
18#include <asm/mmu.h>
d82ace7d 19#include <asm/hypervisor.h>
3af6e01e 20#include <asm/cpudata.h>
1da177e4
LT		 21
22 .data
23 .align 8
24call_method:
25 .asciz "call-method"
26 .align 8
27itlb_load:
28 .asciz "SUNW,itlb-load"
29 .align 8
30dtlb_load:
31 .asciz "SUNW,dtlb-load"
32
33 .text
34 .align 8
35 .globl sparc64_cpu_startup, sparc64_cpu_startup_end
36sparc64_cpu_startup:
37 flushw
38
d82ace7d
DM		 39 BRANCH_IF_SUN4V(g1, niagara_startup)
40 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
41 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
1da177e4
LT		 42
43 ba,pt %xcc, spitfire_startup
44 nop
45
46cheetah_plus_startup:
47 /* Preserve OBP chosen DCU and DCR register settings. */
48 ba,pt %xcc, cheetah_generic_startup
49 nop
50
51cheetah_startup:
52 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
53 wr %g1, %asr18
54
55 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
56 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
57 sllx %g5, 32, %g5
58 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
59 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
60 membar #Sync
61
62cheetah_generic_startup:
63 mov TSB_EXTENSION_P, %g3
64 stxa %g0, [%g3] ASI_DMMU
65 stxa %g0, [%g3] ASI_IMMU
66 membar #Sync
67
68 mov TSB_EXTENSION_S, %g3
69 stxa %g0, [%g3] ASI_DMMU
70 membar #Sync
71
72 mov TSB_EXTENSION_N, %g3
73 stxa %g0, [%g3] ASI_DMMU
74 stxa %g0, [%g3] ASI_IMMU
75 membar #Sync
d82ace7d 76 /* fallthru */
1da177e4 77
d82ace7d 78niagara_startup:
1da177e4
LT		 79 /* Disable STICK_INT interrupts. */
80 sethi %hi(0x80000000), %g5
81 sllx %g5, 32, %g5
82 wr %g5, %asr25
83
84 ba,pt %xcc, startup_continue
85 nop
86
87spitfire_startup:
88 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
89 stxa %g1, [%g0] ASI_LSU_CONTROL
90 membar #Sync
91
92startup_continue:
93 wrpr %g0, 15, %pil
94
95 sethi %hi(0x80000000), %g2
96 sllx %g2, 32, %g2
97 wr %g2, 0, %tick_cmpr
98
d82ace7d
DM		 99 BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
100
1da177e4
LT		 101 /* Call OBP by hand to lock KERNBASE into i/d tlbs.
102 * We lock 2 consequetive entries if we are 'bigkernel'.
103 */
104 mov %o0, %l0
105
106 sethi %hi(prom_entry_lock), %g2
1071: ldstub [%g2 + %lo(prom_entry_lock)], %g1
b445e26c 108 membar #StoreLoad | #StoreStore
1da177e4 109 brnz,pn %g1, 1b
b445e26c 110 nop
1da177e4
LT		 111
112 sethi %hi(p1275buf), %g2
113 or %g2, %lo(p1275buf), %g2
114 ldx [%g2 + 0x10], %l2
115 mov %sp, %l1
116 add %l2, -(192 + 128), %sp
117 flushw
118
119 sethi %hi(call_method), %g2
120 or %g2, %lo(call_method), %g2
121 stx %g2, [%sp + 2047 + 128 + 0x00]
122 mov 5, %g2
123 stx %g2, [%sp + 2047 + 128 + 0x08]
124 mov 1, %g2
125 stx %g2, [%sp + 2047 + 128 + 0x10]
126 sethi %hi(itlb_load), %g2
127 or %g2, %lo(itlb_load), %g2
128 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 129 sethi %hi(prom_mmu_ihandle_cache), %g2
130 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 131 stx %g2, [%sp + 2047 + 128 + 0x20]
132 sethi %hi(KERNBASE), %g2
133 stx %g2, [%sp + 2047 + 128 + 0x28]
134 sethi %hi(kern_locked_tte_data), %g2
135 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
136 stx %g2, [%sp + 2047 + 128 + 0x30]
137
138 mov 15, %g2
139 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
140
141 mov 63, %g2
1421:
143 stx %g2, [%sp + 2047 + 128 + 0x38]
144 sethi %hi(p1275buf), %g2
145 or %g2, %lo(p1275buf), %g2
146 ldx [%g2 + 0x08], %o1
147 call %o1
148 add %sp, (2047 + 128), %o0
149
150 sethi %hi(bigkernel), %g2
151 lduw [%g2 + %lo(bigkernel)], %g2
d82ace7d 152 brz,pt %g2, do_dtlb
1da177e4
LT		 153 nop
154
155 sethi %hi(call_method), %g2
156 or %g2, %lo(call_method), %g2
157 stx %g2, [%sp + 2047 + 128 + 0x00]
158 mov 5, %g2
159 stx %g2, [%sp + 2047 + 128 + 0x08]
160 mov 1, %g2
161 stx %g2, [%sp + 2047 + 128 + 0x10]
162 sethi %hi(itlb_load), %g2
163 or %g2, %lo(itlb_load), %g2
164 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 165 sethi %hi(prom_mmu_ihandle_cache), %g2
166 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 167 stx %g2, [%sp + 2047 + 128 + 0x20]
168 sethi %hi(KERNBASE + 0x400000), %g2
169 stx %g2, [%sp + 2047 + 128 + 0x28]
170 sethi %hi(kern_locked_tte_data), %g2
171 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
172 sethi %hi(0x400000), %g1
173 add %g2, %g1, %g2
174 stx %g2, [%sp + 2047 + 128 + 0x30]
175
176 mov 14, %g2
177 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
178
179 mov 62, %g2
1801:
181 stx %g2, [%sp + 2047 + 128 + 0x38]
182 sethi %hi(p1275buf), %g2
183 or %g2, %lo(p1275buf), %g2
184 ldx [%g2 + 0x08], %o1
185 call %o1
186 add %sp, (2047 + 128), %o0
187
188do_dtlb:
189 sethi %hi(call_method), %g2
190 or %g2, %lo(call_method), %g2
191 stx %g2, [%sp + 2047 + 128 + 0x00]
192 mov 5, %g2
193 stx %g2, [%sp + 2047 + 128 + 0x08]
194 mov 1, %g2
195 stx %g2, [%sp + 2047 + 128 + 0x10]
196 sethi %hi(dtlb_load), %g2
197 or %g2, %lo(dtlb_load), %g2
198 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 199 sethi %hi(prom_mmu_ihandle_cache), %g2
200 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 201 stx %g2, [%sp + 2047 + 128 + 0x20]
202 sethi %hi(KERNBASE), %g2
203 stx %g2, [%sp + 2047 + 128 + 0x28]
204 sethi %hi(kern_locked_tte_data), %g2
205 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
206 stx %g2, [%sp + 2047 + 128 + 0x30]
207
208 mov 15, %g2
209 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
210
211 mov 63, %g2
2121:
213
214 stx %g2, [%sp + 2047 + 128 + 0x38]
215 sethi %hi(p1275buf), %g2
216 or %g2, %lo(p1275buf), %g2
217 ldx [%g2 + 0x08], %o1
218 call %o1
219 add %sp, (2047 + 128), %o0
220
221 sethi %hi(bigkernel), %g2
222 lduw [%g2 + %lo(bigkernel)], %g2
d82ace7d 223 brz,pt %g2, do_unlock
1da177e4
LT		 224 nop
225
226 sethi %hi(call_method), %g2
227 or %g2, %lo(call_method), %g2
228 stx %g2, [%sp + 2047 + 128 + 0x00]
229 mov 5, %g2
230 stx %g2, [%sp + 2047 + 128 + 0x08]
231 mov 1, %g2
232 stx %g2, [%sp + 2047 + 128 + 0x10]
233 sethi %hi(dtlb_load), %g2
234 or %g2, %lo(dtlb_load), %g2
235 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 236 sethi %hi(prom_mmu_ihandle_cache), %g2
237 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 238 stx %g2, [%sp + 2047 + 128 + 0x20]
239 sethi %hi(KERNBASE + 0x400000), %g2
240 stx %g2, [%sp + 2047 + 128 + 0x28]
241 sethi %hi(kern_locked_tte_data), %g2
242 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
243 sethi %hi(0x400000), %g1
244 add %g2, %g1, %g2
245 stx %g2, [%sp + 2047 + 128 + 0x30]
246
247 mov 14, %g2
248 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
249
250 mov 62, %g2
2511:
252
253 stx %g2, [%sp + 2047 + 128 + 0x38]
254 sethi %hi(p1275buf), %g2
255 or %g2, %lo(p1275buf), %g2
256 ldx [%g2 + 0x08], %o1
257 call %o1
258 add %sp, (2047 + 128), %o0
259
260do_unlock:
261 sethi %hi(prom_entry_lock), %g2
262 stb %g0, [%g2 + %lo(prom_entry_lock)]
263 membar #StoreStore | #StoreLoad
264
d82ace7d
DM		 265 ba,pt %xcc, after_lock_tlb
266 nop
267
268niagara_lock_tlb:
164c220f
DM		 269 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
270 sethi %hi(KERNBASE), %o0
271 clr %o1
272 sethi %hi(kern_locked_tte_data), %o2
273 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
274 mov HV_MMU_IMMU, %o3
d82ace7d
DM		 275 ta HV_FAST_TRAP
276
164c220f
DM		 277 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
278 sethi %hi(KERNBASE), %o0
279 clr %o1
280 sethi %hi(kern_locked_tte_data), %o2
281 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
282 mov HV_MMU_DMMU, %o3
d82ace7d
DM		 283 ta HV_FAST_TRAP
284
285 sethi %hi(bigkernel), %g2
286 lduw [%g2 + %lo(bigkernel)], %g2
287 brz,pt %g2, after_lock_tlb
288 nop
289
164c220f
DM		 290 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
291 sethi %hi(KERNBASE + 0x400000), %o0
292 clr %o1
293 sethi %hi(kern_locked_tte_data), %o2
294 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
295 sethi %hi(0x400000), %o3
296 add %o2, %o3, %o2
297 mov HV_MMU_IMMU, %o3
d82ace7d
DM		 298 ta HV_FAST_TRAP
299
164c220f
DM		 300 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
301 sethi %hi(KERNBASE + 0x400000), %o0
302 clr %o1
303 sethi %hi(kern_locked_tte_data), %o2
304 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
305 sethi %hi(0x400000), %o3
306 add %o2, %o3, %o2
307 mov HV_MMU_DMMU, %o3
d82ace7d
DM		 308 ta HV_FAST_TRAP
309
310after_lock_tlb:
1da177e4
LT		 311 mov %l1, %sp
312 flushw
313
314 mov %l0, %o0
315
316 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
317 wr %g0, 0, %fprs
318
319 /* XXX Buggy PROM... */
320 srl %o0, 0, %o0
321 ldx [%o0], %g6
322
323 wr %g0, ASI_P, %asi
324
325 mov PRIMARY_CONTEXT, %g7
8b11bd12
DM		 326
327661: stxa %g0, [%g7] ASI_DMMU
328 .section .sun4v_1insn_patch, "ax"
329 .word 661b
330 stxa %g0, [%g7] ASI_MMU
331 .previous
332
1da177e4
LT		 333 membar #Sync
334 mov SECONDARY_CONTEXT, %g7
8b11bd12
DM		 335
336661: stxa %g0, [%g7] ASI_DMMU
337 .section .sun4v_1insn_patch, "ax"
338 .word 661b
339 stxa %g0, [%g7] ASI_MMU
340 .previous
341
1da177e4
LT		 342 membar #Sync
343
344 mov 1, %g5
345 sllx %g5, THREAD_SHIFT, %g5
346 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
347 add %g6, %g5, %sp
348 mov 0, %fp
349
350 wrpr %g0, 0, %wstate
351 wrpr %g0, 0, %tl
352
56fb4df6 353 /* Load TBA, then we can resurface. */
1da177e4
LT		 354 sethi %hi(sparc64_ttable_tl0), %g5
355 wrpr %g5, %tba
1da177e4 356
1da177e4
LT		 357 ldx [%g6 + TI_TASK], %g4
358
359 wrpr %g0, 0, %wstate
360
361 call init_irqwork_curcpu
362 nop
ac29c11d
DM		 363
364 sethi %hi(tlb_type), %g3
365 lduw [%g3 + %lo(tlb_type)], %g2
366 cmp %g2, 3
367 bne,pt %icc, 1f
368 nop
369
370 call sun4v_init_mondo_queues
b5a37e96 371 mov 0, %o0
ac29c11d
DM		 372
3731: call init_cur_cpu_trap
56fb4df6 374 nop
1da177e4 375
0835ae0f 376 /* Start using proper page size encodings in ctx register. */
8b11bd12
DM		 377 sethi %hi(sparc64_kern_pri_context), %g3
378 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
379 mov PRIMARY_CONTEXT, %g1
380
381661: stxa %g2, [%g1] ASI_DMMU
382 .section .sun4v_1insn_patch, "ax"
383 .word 661b
384 stxa %g2, [%g1] ASI_MMU
385 .previous
386
387 membar #Sync
1da177e4 388
1da177e4
LT		 389 rdpr %pstate, %o1
390 or %o1, PSTATE_IE, %o1
391 wrpr %o1, 0, %pstate
392
12eaa328
DM		 393 sethi %hi(is_sun4v), %o0
394 lduw [%o0 + %lo(is_sun4v)], %o0
395 brz,pt %o0, 1f
396 nop
397
398 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
399 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
400 stxa %g2, [%g0] ASI_SCRATCHPAD
401
402 /* Compute physical address:
403 *
404 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
405 */
406 sethi %hi(KERNBASE), %g3
407 sub %g2, %g3, %g2
408 sethi %hi(kern_base), %g3
409 ldx [%g3 + %lo(kern_base)], %g3
410 add %g2, %g3, %o1
411
412 call prom_set_trap_table_sun4v
413 sethi %hi(sparc64_ttable_tl0), %o0
414
415 ba,pt %xcc, 2f
416 nop
417
4181: call prom_set_trap_table
1da177e4
LT		 419 sethi %hi(sparc64_ttable_tl0), %o0
420
12eaa328 4212: call smp_callin
1da177e4
LT		 422 nop
423 call cpu_idle
424 mov 0, %o0
425 call cpu_panic
426 nop
4271: b,a,pt %xcc, 1b
428
429 .align 8
430sparc64_cpu_startup_end:
Linux kernel - Deliverables
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