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[SPARC64]: Convert cpu_find_by_*() interface to in-kernel PROM device tree.
[deliverable/linux.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
c4bce90e 9#include <linux/module.h>
1da177e4
LT		 10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/slab.h>
18#include <linux/initrd.h>
19#include <linux/swap.h>
20#include <linux/pagemap.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
1da177e4
LT		 26
27#include <asm/head.h>
28#include <asm/system.h>
29#include <asm/page.h>
30#include <asm/pgalloc.h>
31#include <asm/pgtable.h>
32#include <asm/oplib.h>
33#include <asm/iommu.h>
34#include <asm/io.h>
35#include <asm/uaccess.h>
36#include <asm/mmu_context.h>
37#include <asm/tlbflush.h>
38#include <asm/dma.h>
39#include <asm/starfire.h>
40#include <asm/tlb.h>
41#include <asm/spitfire.h>
42#include <asm/sections.h>
517af332 43#include <asm/tsb.h>
481295f9 44#include <asm/hypervisor.h>
372b07bb 45#include <asm/prom.h>
1da177e4
LT		 46
47extern void device_scan(void);
48
9cc3a1ac
DM		 49#define MAX_PHYS_ADDRESS (1UL << 42UL)
50#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
51#define KPTE_BITMAP_BYTES \
52 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53
54unsigned long kern_linear_pte_xor[2] __read_mostly;
55
56/* A bitmap, one bit for every 256MB of physical memory. If the bit
57 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
58 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 */
60unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
61
d7744a09
DM		 62/* A special kernel TSB for 4MB and 256MB linear mappings. */
63struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
64
13edad7a
DM		 65#define MAX_BANKS 32
66
67static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
68static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
69static int pavail_ents __initdata;
70static int pavail_rescan_ents __initdata;
71
72static int cmp_p64(const void *a, const void *b)
73{
74 const struct linux_prom64_registers *x = a, *y = b;
75
76 if (x->phys_addr > y->phys_addr)
77 return 1;
78 if (x->phys_addr < y->phys_addr)
79 return -1;
80 return 0;
81}
82
83static void __init read_obp_memory(const char *property,
84 struct linux_prom64_registers *regs,
85 int *num_ents)
86{
87 int node = prom_finddevice("/memory");
88 int prop_size = prom_getproplen(node, property);
89 int ents, ret, i;
90
91 ents = prop_size / sizeof(struct linux_prom64_registers);
92 if (ents > MAX_BANKS) {
93 prom_printf("The machine has more %s property entries than "
94 "this kernel can support (%d).\n",
95 property, MAX_BANKS);
96 prom_halt();
97 }
98
99 ret = prom_getproperty(node, property, (char *) regs, prop_size);
100 if (ret == -1) {
101 prom_printf("Couldn't get %s property from /memory.\n");
102 prom_halt();
103 }
104
105 *num_ents = ents;
10147570 106
13edad7a
DM		 107 /* Sanitize what we got from the firmware, by page aligning
108 * everything.
109 */
110 for (i = 0; i < ents; i++) {
111 unsigned long base, size;
112
113 base = regs[i].phys_addr;
114 size = regs[i].reg_size;
10147570 115
13edad7a
DM		 116 size &= PAGE_MASK;
117 if (base & ~PAGE_MASK) {
118 unsigned long new_base = PAGE_ALIGN(base);
119
120 size -= new_base - base;
121 if ((long) size < 0L)
122 size = 0UL;
123 base = new_base;
124 }
125 regs[i].phys_addr = base;
126 regs[i].reg_size = size;
127 }
c9c10830 128 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 129 cmp_p64, NULL);
130}
1da177e4 131
2bdb3cb2 132unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 133
d1112018 134/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 135unsigned long kern_base __read_mostly;
136unsigned long kern_size __read_mostly;
1da177e4 137
1da177e4
LT		 138/* get_new_mmu_context() uses "cache + 1". */
139DEFINE_SPINLOCK(ctx_alloc_lock);
140unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
141#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
142unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
143
144/* References to special section boundaries */
145extern char _start[], _end[];
146
147/* Initial ramdisk setup */
148extern unsigned long sparc_ramdisk_image64;
149extern unsigned int sparc_ramdisk_image;
150extern unsigned int sparc_ramdisk_size;
151
1ac4f5eb 152struct page *mem_map_zero __read_mostly;
1da177e4 153
0835ae0f
DM		 154unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
155
156unsigned long sparc64_kern_pri_context __read_mostly;
157unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
158unsigned long sparc64_kern_sec_context __read_mostly;
159
1da177e4
LT		 160int bigkernel = 0;
161
3c936465 162kmem_cache_t *pgtable_cache __read_mostly;
1da177e4 163
3c936465
DM		 164static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
165{
166 clear_page(addr);
167}
05e28f9d 168
9b4006dc
DM		 169extern void tsb_cache_init(void);
170
3c936465 171void pgtable_cache_init(void)
1da177e4 172{
3c936465
DM		 173 pgtable_cache = kmem_cache_create("pgtable_cache",
174 PAGE_SIZE, PAGE_SIZE,
175 SLAB_HWCACHE_ALIGN |
176 SLAB_MUST_HWCACHE_ALIGN,
177 zero_ctor,
178 NULL);
179 if (!pgtable_cache) {
9b4006dc 180 prom_printf("Could not create pgtable_cache\n");
3c936465 181 prom_halt();
1da177e4 182 }
9b4006dc 183 tsb_cache_init();
1da177e4
LT		 184}
185
186#ifdef CONFIG_DEBUG_DCFLUSH
187atomic_t dcpage_flushes = ATOMIC_INIT(0);
188#ifdef CONFIG_SMP
189atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
190#endif
191#endif
192
7a591cfe 193inline void flush_dcache_page_impl(struct page *page)
1da177e4 194{
7a591cfe 195 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 196#ifdef CONFIG_DEBUG_DCFLUSH
197 atomic_inc(&dcpage_flushes);
198#endif
199
200#ifdef DCACHE_ALIASING_POSSIBLE
201 __flush_dcache_page(page_address(page),
202 ((tlb_type == spitfire) &&
203 page_mapping(page) != NULL));
204#else
205 if (page_mapping(page) != NULL &&
206 tlb_type == spitfire)
207 __flush_icache_page(__pa(page_address(page)));
208#endif
209}
210
211#define PG_dcache_dirty PG_arch_1
17b0e199
DM		 212#define PG_dcache_cpu_shift 24UL
213#define PG_dcache_cpu_mask (256UL - 1UL)
48b0e548
DM		 214
215#if NR_CPUS > 256
216#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
217#endif
1da177e4
LT		 218
219#define dcache_dirty_cpu(page) \
48b0e548 220 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 221
222static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
223{
224 unsigned long mask = this_cpu;
48b0e548
DM		 225 unsigned long non_cpu_bits;
226
227 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
228 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
229
1da177e4
LT		 230 __asm__ __volatile__("1:\n\t"
231 "ldx [%2], %%g7\n\t"
232 "and %%g7, %1, %%g1\n\t"
233 "or %%g1, %0, %%g1\n\t"
234 "casx [%2], %%g7, %%g1\n\t"
235 "cmp %%g7, %%g1\n\t"
b445e26c 236 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 237 "bne,pn %%xcc, 1b\n\t"
b445e26c 238 " nop"
1da177e4
LT		 239 : /* no outputs */
240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
241 : "g1", "g7");
242}
243
244static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
245{
246 unsigned long mask = (1UL << PG_dcache_dirty);
247
248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249 "1:\n\t"
250 "ldx [%2], %%g7\n\t"
48b0e548 251 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 252 "and %%g1, %3, %%g1\n\t"
253 "cmp %%g1, %0\n\t"
254 "bne,pn %%icc, 2f\n\t"
255 " andn %%g7, %1, %%g1\n\t"
256 "casx [%2], %%g7, %%g1\n\t"
257 "cmp %%g7, %%g1\n\t"
b445e26c 258 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 259 "bne,pn %%xcc, 1b\n\t"
b445e26c 260 " nop\n"
1da177e4
LT		 261 "2:"
262 : /* no outputs */
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 266 : "g1", "g7");
267}
268
517af332
DM		 269static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270{
271 unsigned long tsb_addr = (unsigned long) ent;
272
3b3ab2eb 273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 274 tsb_addr = __pa(tsb_addr);
275
276 __tsb_insert(tsb_addr, tag, pte);
277}
278
c4bce90e
DM		 279unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
280unsigned long _PAGE_SZBITS __read_mostly;
281
1da177e4
LT		 282void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
283{
bd40791e 284 struct mm_struct *mm;
74ae9987 285 struct tsb *tsb;
7a1ac526 286 unsigned long tag, flags;
dcc1e8dd 287 unsigned long tsb_index, tsb_hash_shift;
7a591cfe
DM		 288
289 if (tlb_type != hypervisor) {
290 unsigned long pfn = pte_pfn(pte);
291 unsigned long pg_flags;
292 struct page *page;
293
294 if (pfn_valid(pfn) &&
295 (page = pfn_to_page(pfn), page_mapping(page)) &&
296 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
297 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
298 PG_dcache_cpu_mask);
299 int this_cpu = get_cpu();
300
301 /* This is just to optimize away some function calls
302 * in the SMP case.
303 */
304 if (cpu == this_cpu)
305 flush_dcache_page_impl(page);
306 else
307 smp_flush_dcache_page_impl(page, cpu);
308
309 clear_dcache_dirty_cpu(page, cpu);
310
311 put_cpu();
312 }
1da177e4 313 }
bd40791e
DM		 314
315 mm = vma->vm_mm;
7a1ac526 316
dcc1e8dd
DM		 317 tsb_index = MM_TSB_BASE;
318 tsb_hash_shift = PAGE_SHIFT;
319
7a1ac526
DM		 320 spin_lock_irqsave(&mm->context.lock, flags);
321
dcc1e8dd
DM		 322#ifdef CONFIG_HUGETLB_PAGE
323 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
324 if ((tlb_type == hypervisor &&
325 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
326 (tlb_type != hypervisor &&
327 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
328 tsb_index = MM_TSB_HUGE;
329 tsb_hash_shift = HPAGE_SHIFT;
330 }
331 }
332#endif
333
334 tsb = mm->context.tsb_block[tsb_index].tsb;
335 tsb += ((address >> tsb_hash_shift) &
336 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 337 tag = (address >> 22UL);
338 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 339
340 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 341}
342
343void flush_dcache_page(struct page *page)
344{
a9546f59
DM		 345 struct address_space *mapping;
346 int this_cpu;
1da177e4 347
7a591cfe
DM		 348 if (tlb_type == hypervisor)
349 return;
350
a9546f59
DM		 351 /* Do not bother with the expensive D-cache flush if it
352 * is merely the zero page. The 'bigcore' testcase in GDB
353 * causes this case to run millions of times.
354 */
355 if (page == ZERO_PAGE(0))
356 return;
357
358 this_cpu = get_cpu();
359
360 mapping = page_mapping(page);
1da177e4 361 if (mapping && !mapping_mapped(mapping)) {
a9546f59 362 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 363 if (dirty) {
a9546f59
DM		 364 int dirty_cpu = dcache_dirty_cpu(page);
365
1da177e4
LT		 366 if (dirty_cpu == this_cpu)
367 goto out;
368 smp_flush_dcache_page_impl(page, dirty_cpu);
369 }
370 set_dcache_dirty(page, this_cpu);
371 } else {
372 /* We could delay the flush for the !page_mapping
373 * case too. But that case is for exec env/arg
374 * pages and those are %99 certainly going to get
375 * faulted into the tlb (and thus flushed) anyways.
376 */
377 flush_dcache_page_impl(page);
378 }
379
380out:
381 put_cpu();
382}
383
05e14cb3 384void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 385{
a43fe0e7 386 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 387 if (tlb_type == spitfire) {
388 unsigned long kaddr;
389
390 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
391 __flush_icache_page(__get_phys(kaddr));
392 }
393}
394
1da177e4
LT		 395void show_mem(void)
396{
397 printk("Mem-info:\n");
398 show_free_areas();
399 printk("Free swap: %6ldkB\n",
400 nr_swap_pages << (PAGE_SHIFT-10));
401 printk("%ld pages of RAM\n", num_physpages);
402 printk("%d free pages\n", nr_free_pages());
1da177e4
LT		 403}
404
405void mmu_info(struct seq_file *m)
406{
407 if (tlb_type == cheetah)
408 seq_printf(m, "MMU Type\t: Cheetah\n");
409 else if (tlb_type == cheetah_plus)
410 seq_printf(m, "MMU Type\t: Cheetah+\n");
411 else if (tlb_type == spitfire)
412 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 413 else if (tlb_type == hypervisor)
414 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 415 else
416 seq_printf(m, "MMU Type\t: ???\n");
417
418#ifdef CONFIG_DEBUG_DCFLUSH
419 seq_printf(m, "DCPageFlushes\t: %d\n",
420 atomic_read(&dcpage_flushes));
421#ifdef CONFIG_SMP
422 seq_printf(m, "DCPageFlushesXC\t: %d\n",
423 atomic_read(&dcpage_flushes_xcall));
424#endif /* CONFIG_SMP */
425#endif /* CONFIG_DEBUG_DCFLUSH */
426}
427
428struct linux_prom_translation {
429 unsigned long virt;
430 unsigned long size;
431 unsigned long data;
432};
c9c10830
DM		 433
434/* Exported for kernel TLB miss handling in ktlb.S */
435struct linux_prom_translation prom_trans[512] __read_mostly;
436unsigned int prom_trans_ents __read_mostly;
1da177e4 437
1da177e4
LT		 438/* Exported for SMP bootup purposes. */
439unsigned long kern_locked_tte_data;
440
c9c10830
DM		 441/* The obp translations are saved based on 8k pagesize, since obp can
442 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 443 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 444 */
5085b4a5
DM		 445static inline int in_obp_range(unsigned long vaddr)
446{
447 return (vaddr >= LOW_OBP_ADDRESS &&
448 vaddr < HI_OBP_ADDRESS);
449}
450
c9c10830 451static int cmp_ptrans(const void *a, const void *b)
405599bd 452{
c9c10830 453 const struct linux_prom_translation *x = a, *y = b;
405599bd 454
c9c10830
DM		 455 if (x->virt > y->virt)
456 return 1;
457 if (x->virt < y->virt)
458 return -1;
459 return 0;
405599bd
DM		 460}
461
c9c10830 462/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 463static void __init read_obp_translations(void)
405599bd 464{
c9c10830 465 int n, node, ents, first, last, i;
1da177e4
LT		 466
467 node = prom_finddevice("/virtual-memory");
468 n = prom_getproplen(node, "translations");
405599bd 469 if (unlikely(n == 0 || n == -1)) {
b206fc4c 470 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 471 prom_halt();
472 }
405599bd
DM		 473 if (unlikely(n > sizeof(prom_trans))) {
474 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 475 prom_halt();
476 }
405599bd 477
b206fc4c 478 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 479 (char *)&prom_trans[0],
480 sizeof(prom_trans))) == -1) {
b206fc4c 481 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 482 prom_halt();
483 }
9ad98c5b 484
b206fc4c 485 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 486
c9c10830
DM		 487 ents = n;
488
489 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
490 cmp_ptrans, NULL);
491
492 /* Now kick out all the non-OBP entries. */
493 for (i = 0; i < ents; i++) {
494 if (in_obp_range(prom_trans[i].virt))
495 break;
496 }
497 first = i;
498 for (; i < ents; i++) {
499 if (!in_obp_range(prom_trans[i].virt))
500 break;
501 }
502 last = i;
503
504 for (i = 0; i < (last - first); i++) {
505 struct linux_prom_translation *src = &prom_trans[i + first];
506 struct linux_prom_translation *dest = &prom_trans[i];
507
508 *dest = *src;
509 }
510 for (; i < ents; i++) {
511 struct linux_prom_translation *dest = &prom_trans[i];
512 dest->virt = dest->size = dest->data = 0x0UL;
513 }
514
515 prom_trans_ents = last - first;
516
517 if (tlb_type == spitfire) {
518 /* Clear diag TTE bits. */
519 for (i = 0; i < prom_trans_ents; i++)
520 prom_trans[i].data &= ~0x0003fe0000000000UL;
521 }
405599bd 522}
1da177e4 523
d82ace7d
DM		 524static void __init hypervisor_tlb_lock(unsigned long vaddr,
525 unsigned long pte,
526 unsigned long mmu)
527{
164c220f
DM		 528 register unsigned long func asm("%o5");
529 register unsigned long arg0 asm("%o0");
530 register unsigned long arg1 asm("%o1");
531 register unsigned long arg2 asm("%o2");
532 register unsigned long arg3 asm("%o3");
d82ace7d
DM		 533
534 func = HV_FAST_MMU_MAP_PERM_ADDR;
535 arg0 = vaddr;
536 arg1 = 0;
537 arg2 = pte;
538 arg3 = mmu;
539 __asm__ __volatile__("ta 0x80"
540 : "=&r" (func), "=&r" (arg0),
541 "=&r" (arg1), "=&r" (arg2),
542 "=&r" (arg3)
543 : "0" (func), "1" (arg0), "2" (arg1),
544 "3" (arg2), "4" (arg3));
12e126ad
DM		 545 if (arg0 != 0) {
546 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
547 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
548 prom_halt();
549 }
d82ace7d
DM		 550}
551
c4bce90e
DM		 552static unsigned long kern_large_tte(unsigned long paddr);
553
898cf0ec 554static void __init remap_kernel(void)
405599bd
DM		 555{
556 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 557 int tlb_ent = sparc64_highest_locked_tlbent();
558
1da177e4 559 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 560 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 561 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 562
563 kern_locked_tte_data = tte_data;
564
d82ace7d
DM		 565 /* Now lock us into the TLBs via Hypervisor or OBP. */
566 if (tlb_type == hypervisor) {
567 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
568 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
569 if (bigkernel) {
570 tte_vaddr += 0x400000;
571 tte_data += 0x400000;
572 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
573 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
574 }
575 } else {
576 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
577 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
578 if (bigkernel) {
579 tlb_ent -= 1;
580 prom_dtlb_load(tlb_ent,
581 tte_data + 0x400000,
582 tte_vaddr + 0x400000);
583 prom_itlb_load(tlb_ent,
584 tte_data + 0x400000,
585 tte_vaddr + 0x400000);
586 }
587 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
1da177e4 588 }
0835ae0f
DM		 589 if (tlb_type == cheetah_plus) {
590 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
591 CTX_CHEETAH_PLUS_NUC);
592 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
593 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
594 }
405599bd 595}
1da177e4 596
405599bd 597
c9c10830 598static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 599{
600 read_obp_translations();
405599bd
DM		 601
602 /* Now fixup OBP's idea about where we really are mapped. */
603 prom_printf("Remapping the kernel... ");
604 remap_kernel();
1da177e4 605 prom_printf("done.\n");
1da177e4
LT		 606}
607
1da177e4
LT		 608void prom_world(int enter)
609{
1da177e4
LT		 610 if (!enter)
611 set_fs((mm_segment_t) { get_thread_current_ds() });
612
3487d1d4 613 __asm__ __volatile__("flushw");
1da177e4
LT		 614}
615
616#ifdef DCACHE_ALIASING_POSSIBLE
617void __flush_dcache_range(unsigned long start, unsigned long end)
618{
619 unsigned long va;
620
621 if (tlb_type == spitfire) {
622 int n = 0;
623
624 for (va = start; va < end; va += 32) {
625 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
626 if (++n >= 512)
627 break;
628 }
a43fe0e7 629 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 630 start = __pa(start);
631 end = __pa(end);
632 for (va = start; va < end; va += 32)
633 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
634 "membar #Sync"
635 : /* no outputs */
636 : "r" (va),
637 "i" (ASI_DCACHE_INVALIDATE));
638 }
639}
640#endif /* DCACHE_ALIASING_POSSIBLE */
641
1da177e4
LT		 642/* Caller does TLB context flushing on local CPU if necessary.
643 * The caller also ensures that CTX_VALID(mm->context) is false.
644 *
645 * We must be careful about boundary cases so that we never
646 * let the user have CTX 0 (nucleus) or we ever use a CTX
647 * version of zero (and thus NO_CONTEXT would not be caught
648 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 649 *
650 * Always invoked with interrupts disabled.
1da177e4
LT		 651 */
652void get_new_mmu_context(struct mm_struct *mm)
653{
654 unsigned long ctx, new_ctx;
655 unsigned long orig_pgsz_bits;
a77754b4 656 unsigned long flags;
a0663a79 657 int new_version;
1da177e4 658
a77754b4 659 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 660 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
661 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
662 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 663 new_version = 0;
1da177e4
LT		 664 if (new_ctx >= (1 << CTX_NR_BITS)) {
665 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
666 if (new_ctx >= ctx) {
667 int i;
668 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
669 CTX_FIRST_VERSION;
670 if (new_ctx == 1)
671 new_ctx = CTX_FIRST_VERSION;
672
673 /* Don't call memset, for 16 entries that's just
674 * plain silly...
675 */
676 mmu_context_bmap[0] = 3;
677 mmu_context_bmap[1] = 0;
678 mmu_context_bmap[2] = 0;
679 mmu_context_bmap[3] = 0;
680 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
681 mmu_context_bmap[i + 0] = 0;
682 mmu_context_bmap[i + 1] = 0;
683 mmu_context_bmap[i + 2] = 0;
684 mmu_context_bmap[i + 3] = 0;
685 }
a0663a79 686 new_version = 1;
1da177e4
LT		 687 goto out;
688 }
689 }
690 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
691 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
692out:
693 tlb_context_cache = new_ctx;
694 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 695 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 696
697 if (unlikely(new_version))
698 smp_new_mmu_context_version();
1da177e4
LT		 699}
700
1da177e4
LT		 701void sparc_ultra_dump_itlb(void)
702{
703 int slot;
704
705 if (tlb_type == spitfire) {
706 printk ("Contents of itlb: ");
707 for (slot = 0; slot < 14; slot++) printk (" ");
708 printk ("%2x:%016lx,%016lx\n",
709 0,
710 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
711 for (slot = 1; slot < 64; slot+=3) {
712 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
713 slot,
714 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
715 slot+1,
716 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
717 slot+2,
718 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
719 }
720 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
721 printk ("Contents of itlb0:\n");
722 for (slot = 0; slot < 16; slot+=2) {
723 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
724 slot,
725 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
726 slot+1,
727 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
728 }
729 printk ("Contents of itlb2:\n");
730 for (slot = 0; slot < 128; slot+=2) {
731 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
732 slot,
733 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
734 slot+1,
735 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
736 }
737 }
738}
739
740void sparc_ultra_dump_dtlb(void)
741{
742 int slot;
743
744 if (tlb_type == spitfire) {
745 printk ("Contents of dtlb: ");
746 for (slot = 0; slot < 14; slot++) printk (" ");
747 printk ("%2x:%016lx,%016lx\n", 0,
748 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
749 for (slot = 1; slot < 64; slot+=3) {
750 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
751 slot,
752 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
753 slot+1,
754 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
755 slot+2,
756 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
757 }
758 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
759 printk ("Contents of dtlb0:\n");
760 for (slot = 0; slot < 16; slot+=2) {
761 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
762 slot,
763 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
764 slot+1,
765 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
766 }
767 printk ("Contents of dtlb2:\n");
768 for (slot = 0; slot < 512; slot+=2) {
769 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
770 slot,
771 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
772 slot+1,
773 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
774 }
775 if (tlb_type == cheetah_plus) {
776 printk ("Contents of dtlb3:\n");
777 for (slot = 0; slot < 512; slot+=2) {
778 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
779 slot,
780 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
781 slot+1,
782 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
783 }
784 }
785 }
786}
787
788extern unsigned long cmdline_memory_size;
789
d1112018
DM		 790/* Find a free area for the bootmem map, avoiding the kernel image
791 * and the initial ramdisk.
792 */
793static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
794 unsigned long end_pfn)
1da177e4 795{
d1112018
DM		 796 unsigned long avoid_start, avoid_end, bootmap_size;
797 int i;
798
799 bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
800 bootmap_size = ALIGN(bootmap_size, sizeof(long));
801
802 avoid_start = avoid_end = 0;
803#ifdef CONFIG_BLK_DEV_INITRD
804 avoid_start = initrd_start;
805 avoid_end = PAGE_ALIGN(initrd_end);
806#endif
807
808#ifdef CONFIG_DEBUG_BOOTMEM
809 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
810 kern_base, PAGE_ALIGN(kern_base + kern_size),
811 avoid_start, avoid_end);
812#endif
813 for (i = 0; i < pavail_ents; i++) {
814 unsigned long start, end;
815
816 start = pavail[i].phys_addr;
817 end = start + pavail[i].reg_size;
818
819 while (start < end) {
820 if (start >= kern_base &&
821 start < PAGE_ALIGN(kern_base + kern_size)) {
822 start = PAGE_ALIGN(kern_base + kern_size);
823 continue;
824 }
825 if (start >= avoid_start && start < avoid_end) {
826 start = avoid_end;
827 continue;
828 }
829
830 if ((end - start) < bootmap_size)
831 break;
832
833 if (start < kern_base &&
834 (start + bootmap_size) > kern_base) {
835 start = PAGE_ALIGN(kern_base + kern_size);
836 continue;
837 }
838
839 if (start < avoid_start &&
840 (start + bootmap_size) > avoid_start) {
841 start = avoid_end;
842 continue;
843 }
844
845 /* OK, it doesn't overlap anything, use it. */
846#ifdef CONFIG_DEBUG_BOOTMEM
847 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
848 start >> PAGE_SHIFT, start);
849#endif
850 return start >> PAGE_SHIFT;
851 }
852 }
853
854 prom_printf("Cannot find free area for bootmap, aborting.\n");
855 prom_halt();
856}
857
858static unsigned long __init bootmem_init(unsigned long *pages_avail,
859 unsigned long phys_base)
860{
861 unsigned long bootmap_size, end_pfn;
1da177e4
LT		 862 unsigned long end_of_phys_memory = 0UL;
863 unsigned long bootmap_pfn, bytes_avail, size;
864 int i;
865
866#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 867 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 868#endif
869
870 bytes_avail = 0UL;
13edad7a
DM		 871 for (i = 0; i < pavail_ents; i++) {
872 end_of_phys_memory = pavail[i].phys_addr +
873 pavail[i].reg_size;
874 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 875 if (cmdline_memory_size) {
876 if (bytes_avail > cmdline_memory_size) {
877 unsigned long slack = bytes_avail - cmdline_memory_size;
878
879 bytes_avail -= slack;
880 end_of_phys_memory -= slack;
881
13edad7a
DM		 882 pavail[i].reg_size -= slack;
883 if ((long)pavail[i].reg_size <= 0L) {
884 pavail[i].phys_addr = 0xdeadbeefUL;
885 pavail[i].reg_size = 0UL;
886 pavail_ents = i;
1da177e4 887 } else {
13edad7a
DM		 888 pavail[i+1].reg_size = 0Ul;
889 pavail[i+1].phys_addr = 0xdeadbeefUL;
890 pavail_ents = i + 1;
1da177e4
LT		 891 }
892 break;
893 }
894 }
895 }
896
897 *pages_avail = bytes_avail >> PAGE_SHIFT;
898
1da177e4
LT		 899 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
900
901#ifdef CONFIG_BLK_DEV_INITRD
902 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
903 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
904 unsigned long ramdisk_image = sparc_ramdisk_image ?
905 sparc_ramdisk_image : sparc_ramdisk_image64;
906 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
907 ramdisk_image -= KERNBASE;
908 initrd_start = ramdisk_image + phys_base;
909 initrd_end = initrd_start + sparc_ramdisk_size;
910 if (initrd_end > end_of_phys_memory) {
911 printk(KERN_CRIT "initrd extends beyond end of memory "
912 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
913 initrd_end, end_of_phys_memory);
914 initrd_start = 0;
d1112018 915 initrd_end = 0;
1da177e4
LT		 916 }
917 }
918#endif
919 /* Initialize the boot-time allocator. */
920 max_pfn = max_low_pfn = end_pfn;
d1112018
DM		 921 min_low_pfn = (phys_base >> PAGE_SHIFT);
922
923 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1da177e4
LT		 924
925#ifdef CONFIG_DEBUG_BOOTMEM
926 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
927 min_low_pfn, bootmap_pfn, max_low_pfn);
928#endif
d1112018 929 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
17b0e199 930 min_low_pfn, end_pfn);
1da177e4 931
1da177e4
LT		 932 /* Now register the available physical memory with the
933 * allocator.
934 */
13edad7a 935 for (i = 0; i < pavail_ents; i++) {
1da177e4 936#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 937 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
938 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 939#endif
13edad7a 940 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 941 }
942
943#ifdef CONFIG_BLK_DEV_INITRD
944 if (initrd_start) {
945 size = initrd_end - initrd_start;
946
947 /* Resert the initrd image area. */
948#ifdef CONFIG_DEBUG_BOOTMEM
949 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
950 initrd_start, initrd_end);
951#endif
952 reserve_bootmem(initrd_start, size);
953 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
954
955 initrd_start += PAGE_OFFSET;
956 initrd_end += PAGE_OFFSET;
957 }
958#endif
959 /* Reserve the kernel text/data/bss. */
960#ifdef CONFIG_DEBUG_BOOTMEM
961 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
962#endif
963 reserve_bootmem(kern_base, kern_size);
964 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
965
966 /* Reserve the bootmem map. We do not account for it
967 * in pages_avail because we will release that memory
968 * in free_all_bootmem.
969 */
970 size = bootmap_size;
971#ifdef CONFIG_DEBUG_BOOTMEM
972 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
973 (bootmap_pfn << PAGE_SHIFT), size);
974#endif
975 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
976 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
977
d1112018
DM		 978 for (i = 0; i < pavail_ents; i++) {
979 unsigned long start_pfn, end_pfn;
980
981 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
982 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
983#ifdef CONFIG_DEBUG_BOOTMEM
984 prom_printf("memory_present(0, %lx, %lx)\n",
985 start_pfn, end_pfn);
986#endif
987 memory_present(0, start_pfn, end_pfn);
988 }
989
990 sparse_init();
991
1da177e4
LT		 992 return end_pfn;
993}
994
9cc3a1ac
DM		 995static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
996static int pall_ents __initdata;
997
56425306
DM		 998#ifdef CONFIG_DEBUG_PAGEALLOC
999static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1000{
1001 unsigned long vstart = PAGE_OFFSET + pstart;
1002 unsigned long vend = PAGE_OFFSET + pend;
1003 unsigned long alloc_bytes = 0UL;
1004
1005 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1006 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1007 vstart, vend);
1008 prom_halt();
1009 }
1010
1011 while (vstart < vend) {
1012 unsigned long this_end, paddr = __pa(vstart);
1013 pgd_t *pgd = pgd_offset_k(vstart);
1014 pud_t *pud;
1015 pmd_t *pmd;
1016 pte_t *pte;
1017
1018 pud = pud_offset(pgd, vstart);
1019 if (pud_none(*pud)) {
1020 pmd_t *new;
1021
1022 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1023 alloc_bytes += PAGE_SIZE;
1024 pud_populate(&init_mm, pud, new);
1025 }
1026
1027 pmd = pmd_offset(pud, vstart);
1028 if (!pmd_present(*pmd)) {
1029 pte_t *new;
1030
1031 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1032 alloc_bytes += PAGE_SIZE;
1033 pmd_populate_kernel(&init_mm, pmd, new);
1034 }
1035
1036 pte = pte_offset_kernel(pmd, vstart);
1037 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1038 if (this_end > vend)
1039 this_end = vend;
1040
1041 while (vstart < this_end) {
1042 pte_val(*pte) = (paddr | pgprot_val(prot));
1043
1044 vstart += PAGE_SIZE;
1045 paddr += PAGE_SIZE;
1046 pte++;
1047 }
1048 }
1049
1050 return alloc_bytes;
1051}
1052
56425306 1053extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1054#endif /* CONFIG_DEBUG_PAGEALLOC */
1055
1056static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1057{
1058 const unsigned long shift_256MB = 28;
1059 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1060 const unsigned long size_256MB = (1UL << shift_256MB);
1061
1062 while (start < end) {
1063 long remains;
1064
f7c00338
DM		 1065 remains = end - start;
1066 if (remains < size_256MB)
1067 break;
1068
9cc3a1ac
DM		 1069 if (start & mask_256MB) {
1070 start = (start + size_256MB) & ~mask_256MB;
1071 continue;
1072 }
1073
9cc3a1ac
DM		 1074 while (remains >= size_256MB) {
1075 unsigned long index = start >> shift_256MB;
1076
1077 __set_bit(index, kpte_linear_bitmap);
1078
1079 start += size_256MB;
1080 remains -= size_256MB;
1081 }
1082 }
1083}
56425306
DM		 1084
1085static void __init kernel_physical_mapping_init(void)
1086{
9cc3a1ac
DM		 1087 unsigned long i;
1088#ifdef CONFIG_DEBUG_PAGEALLOC
1089 unsigned long mem_alloced = 0UL;
1090#endif
56425306 1091
13edad7a
DM		 1092 read_obp_memory("reg", &pall[0], &pall_ents);
1093
1094 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1095 unsigned long phys_start, phys_end;
1096
13edad7a
DM		 1097 phys_start = pall[i].phys_addr;
1098 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1099
1100 mark_kpte_bitmap(phys_start, phys_end);
1101
1102#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1103 mem_alloced += kernel_map_range(phys_start, phys_end,
1104 PAGE_KERNEL);
9cc3a1ac 1105#endif
56425306
DM		 1106 }
1107
9cc3a1ac 1108#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1109 printk("Allocated %ld bytes for kernel page tables.\n",
1110 mem_alloced);
1111
1112 kvmap_linear_patch[0] = 0x01000000; /* nop */
1113 flushi(&kvmap_linear_patch[0]);
1114
1115 __flush_tlb_all();
9cc3a1ac 1116#endif
56425306
DM		 1117}
1118
9cc3a1ac 1119#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1120void kernel_map_pages(struct page *page, int numpages, int enable)
1121{
1122 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1123 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1124
1125 kernel_map_range(phys_start, phys_end,
1126 (enable ? PAGE_KERNEL : __pgprot(0)));
1127
74bf4312
DM		 1128 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1129 PAGE_OFFSET + phys_end);
1130
56425306
DM		 1131 /* we should perform an IPI and flush all tlbs,
1132 * but that can deadlock->flush only current cpu.
1133 */
1134 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1135 PAGE_OFFSET + phys_end);
1136}
1137#endif
1138
10147570
DM		 1139unsigned long __init find_ecache_flush_span(unsigned long size)
1140{
0836a0eb
DM		 1141 int i;
1142
13edad7a
DM		 1143 for (i = 0; i < pavail_ents; i++) {
1144 if (pavail[i].reg_size >= size)
1145 return pavail[i].phys_addr;
0836a0eb
DM		 1146 }
1147
13edad7a 1148 return ~0UL;
0836a0eb
DM		 1149}
1150
517af332
DM		 1151static void __init tsb_phys_patch(void)
1152{
d257d5da 1153 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1154 struct tsb_phys_patch_entry *p;
1155
d257d5da
DM		 1156 pquad = &__tsb_ldquad_phys_patch;
1157 while (pquad < &__tsb_ldquad_phys_patch_end) {
1158 unsigned long addr = pquad->addr;
1159
1160 if (tlb_type == hypervisor)
1161 *(unsigned int *) addr = pquad->sun4v_insn;
1162 else
1163 *(unsigned int *) addr = pquad->sun4u_insn;
1164 wmb();
1165 __asm__ __volatile__("flush %0"
1166 : /* no outputs */
1167 : "r" (addr));
1168
1169 pquad++;
1170 }
1171
517af332
DM		 1172 p = &__tsb_phys_patch;
1173 while (p < &__tsb_phys_patch_end) {
1174 unsigned long addr = p->addr;
1175
1176 *(unsigned int *) addr = p->insn;
1177 wmb();
1178 __asm__ __volatile__("flush %0"
1179 : /* no outputs */
1180 : "r" (addr));
1181
1182 p++;
1183 }
1184}
1185
490384e7
DM		 1186/* Don't mark as init, we give this to the Hypervisor. */
1187static struct hv_tsb_descr ktsb_descr[2];
1188extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1189
1190static void __init sun4v_ktsb_init(void)
1191{
1192 unsigned long ktsb_pa;
1193
d7744a09 1194 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1195 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1196
1197 switch (PAGE_SIZE) {
1198 case 8 * 1024:
1199 default:
1200 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1201 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1202 break;
1203
1204 case 64 * 1024:
1205 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1206 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1207 break;
1208
1209 case 512 * 1024:
1210 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1211 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1212 break;
1213
1214 case 4 * 1024 * 1024:
1215 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1216 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1217 break;
1218 };
1219
3f19a84e 1220 ktsb_descr[0].assoc = 1;
490384e7
DM		 1221 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1222 ktsb_descr[0].ctx_idx = 0;
1223 ktsb_descr[0].tsb_base = ktsb_pa;
1224 ktsb_descr[0].resv = 0;
1225
d7744a09
DM		 1226 /* Second KTSB for 4MB/256MB mappings. */
1227 ktsb_pa = (kern_base +
1228 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1229
1230 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1231 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1232 HV_PGSZ_MASK_256MB);
1233 ktsb_descr[1].assoc = 1;
1234 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1235 ktsb_descr[1].ctx_idx = 0;
1236 ktsb_descr[1].tsb_base = ktsb_pa;
1237 ktsb_descr[1].resv = 0;
490384e7
DM		 1238}
1239
1240void __cpuinit sun4v_ktsb_register(void)
1241{
1242 register unsigned long func asm("%o5");
1243 register unsigned long arg0 asm("%o0");
1244 register unsigned long arg1 asm("%o1");
1245 unsigned long pa;
1246
1247 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1248
1249 func = HV_FAST_MMU_TSB_CTX0;
d7744a09 1250 arg0 = 2;
490384e7
DM		 1251 arg1 = pa;
1252 __asm__ __volatile__("ta %6"
1253 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1254 : "0" (func), "1" (arg0), "2" (arg1),
1255 "i" (HV_FAST_TRAP));
1256}
1257
1da177e4
LT		 1258/* paging_init() sets up the page tables */
1259
1260extern void cheetah_ecache_flush_init(void);
d257d5da 1261extern void sun4v_patch_tlb_handlers(void);
1da177e4
LT		 1262
1263static unsigned long last_valid_pfn;
56425306 1264pgd_t swapper_pg_dir[2048];
1da177e4 1265
c4bce90e
DM		 1266static void sun4u_pgprot_init(void);
1267static void sun4v_pgprot_init(void);
1268
1da177e4
LT		 1269void __init paging_init(void)
1270{
d1112018 1271 unsigned long end_pfn, pages_avail, shift, phys_base;
0836a0eb
DM		 1272 unsigned long real_end, i;
1273
481295f9
DM		 1274 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1275 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1276
d7744a09 1277 /* Invalidate both kernel TSBs. */
8b234274 1278 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d7744a09 1279 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
8b234274 1280
c4bce90e
DM		 1281 if (tlb_type == hypervisor)
1282 sun4v_pgprot_init();
1283 else
1284 sun4u_pgprot_init();
1285
d257d5da
DM		 1286 if (tlb_type == cheetah_plus ||
1287 tlb_type == hypervisor)
517af332
DM		 1288 tsb_phys_patch();
1289
490384e7 1290 if (tlb_type == hypervisor) {
d257d5da 1291 sun4v_patch_tlb_handlers();
490384e7
DM		 1292 sun4v_ktsb_init();
1293 }
d257d5da 1294
13edad7a
DM		 1295 /* Find available physical memory... */
1296 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1297
1298 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1299 for (i = 0; i < pavail_ents; i++)
1300 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1301
1da177e4
LT		 1302 set_bit(0, mmu_context_bmap);
1303
2bdb3cb2
DM		 1304 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1305
1da177e4
LT		 1306 real_end = (unsigned long)_end;
1307 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1308 bigkernel = 1;
2bdb3cb2
DM		 1309 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1310 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1311 prom_halt();
1da177e4 1312 }
2bdb3cb2
DM		 1313
1314 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1315 * work.
1316 */
1317 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1318
56425306 1319 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1320
1321 /* Now can init the kernel/bad page tables. */
1322 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1323 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1324
c9c10830 1325 inherit_prom_mappings();
5085b4a5 1326
a8b900d8
DM		 1327 /* Ok, we can use our TLB miss and window trap handlers safely. */
1328 setup_tba();
1da177e4 1329
c9c10830 1330 __flush_tlb_all();
9ad98c5b 1331
490384e7
DM		 1332 if (tlb_type == hypervisor)
1333 sun4v_ktsb_register();
1334
2bdb3cb2
DM		 1335 /* Setup bootmem... */
1336 pages_avail = 0;
d1112018
DM		 1337 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1338
17b0e199 1339 max_mapnr = last_valid_pfn;
2bdb3cb2 1340
56425306 1341 kernel_physical_mapping_init();
56425306 1342
372b07bb
DM		 1343 prom_build_devicetree();
1344
1da177e4
LT		 1345 {
1346 unsigned long zones_size[MAX_NR_ZONES];
1347 unsigned long zholes_size[MAX_NR_ZONES];
1da177e4
LT		 1348 int znum;
1349
1350 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1351 zones_size[znum] = zholes_size[znum] = 0;
1352
17b0e199
DM		 1353 zones_size[ZONE_DMA] = end_pfn;
1354 zholes_size[ZONE_DMA] = end_pfn - pages_avail;
1da177e4
LT		 1355
1356 free_area_init_node(0, &contig_page_data, zones_size,
17b0e199
DM		 1357 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1358 zholes_size);
1da177e4
LT		 1359 }
1360
1361 device_scan();
1362}
1363
1da177e4
LT		 1364static void __init taint_real_pages(void)
1365{
1da177e4
LT		 1366 int i;
1367
13edad7a 1368 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1369
13edad7a 1370 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1371 * reserve the lost portions in the bootmem maps.
1372 */
13edad7a 1373 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1374 unsigned long old_start, old_end;
1375
13edad7a 1376 old_start = pavail[i].phys_addr;
1da177e4 1377 old_end = old_start +
13edad7a 1378 pavail[i].reg_size;
1da177e4
LT		 1379 while (old_start < old_end) {
1380 int n;
1381
13edad7a 1382 for (n = 0; pavail_rescan_ents; n++) {
1da177e4
LT		 1383 unsigned long new_start, new_end;
1384
13edad7a
DM		 1385 new_start = pavail_rescan[n].phys_addr;
1386 new_end = new_start +
1387 pavail_rescan[n].reg_size;
1da177e4
LT		 1388
1389 if (new_start <= old_start &&
1390 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1391 set_bit(old_start >> 22,
1392 sparc64_valid_addr_bitmap);
1da177e4
LT		 1393 goto do_next_page;
1394 }
1395 }
1396 reserve_bootmem(old_start, PAGE_SIZE);
1397
1398 do_next_page:
1399 old_start += PAGE_SIZE;
1400 }
1401 }
1402}
1403
1404void __init mem_init(void)
1405{
1406 unsigned long codepages, datapages, initpages;
1407 unsigned long addr, last;
1408 int i;
1409
1410 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1411 i += 1;
2bdb3cb2 1412 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1413 if (sparc64_valid_addr_bitmap == NULL) {
1414 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1415 prom_halt();
1416 }
1417 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1418
1419 addr = PAGE_OFFSET + kern_base;
1420 last = PAGE_ALIGN(kern_size) + addr;
1421 while (addr < last) {
1422 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1423 addr += PAGE_SIZE;
1424 }
1425
1426 taint_real_pages();
1427
1da177e4
LT		 1428 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1429
1430#ifdef CONFIG_DEBUG_BOOTMEM
1431 prom_printf("mem_init: Calling free_all_bootmem().\n");
1432#endif
1433 totalram_pages = num_physpages = free_all_bootmem() - 1;
1434
1435 /*
1436 * Set up the zero page, mark it reserved, so that page count
1437 * is not manipulated when freeing the page from user ptes.
1438 */
1439 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1440 if (mem_map_zero == NULL) {
1441 prom_printf("paging_init: Cannot alloc zero page.\n");
1442 prom_halt();
1443 }
1444 SetPageReserved(mem_map_zero);
1445
1446 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1447 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1448 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1449 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1450 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1451 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1452
1453 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1454 nr_free_pages() << (PAGE_SHIFT-10),
1455 codepages << (PAGE_SHIFT-10),
1456 datapages << (PAGE_SHIFT-10),
1457 initpages << (PAGE_SHIFT-10),
1458 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1459
1460 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1461 cheetah_ecache_flush_init();
1462}
1463
898cf0ec 1464void free_initmem(void)
1da177e4
LT		 1465{
1466 unsigned long addr, initend;
1467
1468 /*
1469 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1470 */
1471 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1472 initend = (unsigned long)(__init_end) & PAGE_MASK;
1473 for (; addr < initend; addr += PAGE_SIZE) {
1474 unsigned long page;
1475 struct page *p;
1476
1477 page = (addr +
1478 ((unsigned long) __va(kern_base)) -
1479 ((unsigned long) KERNBASE));
1480 memset((void *)addr, 0xcc, PAGE_SIZE);
1481 p = virt_to_page(page);
1482
1483 ClearPageReserved(p);
7835e98b 1484 init_page_count(p);
1da177e4
LT		 1485 __free_page(p);
1486 num_physpages++;
1487 totalram_pages++;
1488 }
1489}
1490
1491#ifdef CONFIG_BLK_DEV_INITRD
1492void free_initrd_mem(unsigned long start, unsigned long end)
1493{
1494 if (start < end)
1495 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1496 for (; start < end; start += PAGE_SIZE) {
1497 struct page *p = virt_to_page(start);
1498
1499 ClearPageReserved(p);
7835e98b 1500 init_page_count(p);
1da177e4
LT		 1501 __free_page(p);
1502 num_physpages++;
1503 totalram_pages++;
1504 }
1505}
1506#endif
c4bce90e 1507
c4bce90e
DM		 1508#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1509#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1510#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1511#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1512#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1513#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1514
1515pgprot_t PAGE_KERNEL __read_mostly;
1516EXPORT_SYMBOL(PAGE_KERNEL);
1517
1518pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1519pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1520
1521pgprot_t PAGE_SHARED __read_mostly;
1522EXPORT_SYMBOL(PAGE_SHARED);
1523
c4bce90e
DM		 1524pgprot_t PAGE_EXEC __read_mostly;
1525unsigned long pg_iobits __read_mostly;
1526
1527unsigned long _PAGE_IE __read_mostly;
b2bef442 1528
c4bce90e 1529unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1530EXPORT_SYMBOL(_PAGE_E);
1531
c4bce90e 1532unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1533EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e
DM		 1534
1535static void prot_init_common(unsigned long page_none,
1536 unsigned long page_shared,
1537 unsigned long page_copy,
1538 unsigned long page_readonly,
1539 unsigned long page_exec_bit)
1540{
1541 PAGE_COPY = __pgprot(page_copy);
0f15952a 1542 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1543
1544 protection_map[0x0] = __pgprot(page_none);
1545 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1546 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1547 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1548 protection_map[0x4] = __pgprot(page_readonly);
1549 protection_map[0x5] = __pgprot(page_readonly);
1550 protection_map[0x6] = __pgprot(page_copy);
1551 protection_map[0x7] = __pgprot(page_copy);
1552 protection_map[0x8] = __pgprot(page_none);
1553 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1554 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1555 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1556 protection_map[0xc] = __pgprot(page_readonly);
1557 protection_map[0xd] = __pgprot(page_readonly);
1558 protection_map[0xe] = __pgprot(page_shared);
1559 protection_map[0xf] = __pgprot(page_shared);
1560}
1561
1562static void __init sun4u_pgprot_init(void)
1563{
1564 unsigned long page_none, page_shared, page_copy, page_readonly;
1565 unsigned long page_exec_bit;
1566
1567 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1568 _PAGE_CACHE_4U | _PAGE_P_4U |
1569 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1570 _PAGE_EXEC_4U);
1571 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1572 _PAGE_CACHE_4U | _PAGE_P_4U |
1573 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1574 _PAGE_EXEC_4U | _PAGE_L_4U);
1575 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1576
1577 _PAGE_IE = _PAGE_IE_4U;
1578 _PAGE_E = _PAGE_E_4U;
1579 _PAGE_CACHE = _PAGE_CACHE_4U;
1580
1581 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1582 __ACCESS_BITS_4U | _PAGE_E_4U);
1583
9cc3a1ac 1584 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1585 0xfffff80000000000;
9cc3a1ac
DM		 1586 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1587 _PAGE_P_4U | _PAGE_W_4U);
1588
1589 /* XXX Should use 256MB on Panther. XXX */
1590 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1591
1592 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1593 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1594 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1595 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1596
1597
1598 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1599 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1600 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1601 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1602 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1603 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1604 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1605
1606 page_exec_bit = _PAGE_EXEC_4U;
1607
1608 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1609 page_exec_bit);
1610}
1611
1612static void __init sun4v_pgprot_init(void)
1613{
1614 unsigned long page_none, page_shared, page_copy, page_readonly;
1615 unsigned long page_exec_bit;
1616
1617 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1618 _PAGE_CACHE_4V | _PAGE_P_4V |
1619 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1620 _PAGE_EXEC_4V);
1621 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1622 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1623
1624 _PAGE_IE = _PAGE_IE_4V;
1625 _PAGE_E = _PAGE_E_4V;
1626 _PAGE_CACHE = _PAGE_CACHE_4V;
1627
9cc3a1ac
DM		 1628 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1629 0xfffff80000000000;
1630 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1631 _PAGE_P_4V | _PAGE_W_4V);
1632
1633 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1634 0xfffff80000000000;
9cc3a1ac
DM		 1635 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1636 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1637
1638 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1639 __ACCESS_BITS_4V | _PAGE_E_4V);
1640
1641 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1642 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1643 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1644 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1645 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1646
1647 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1648 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1649 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1650 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1651 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1652 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1653 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1654
1655 page_exec_bit = _PAGE_EXEC_4V;
1656
1657 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1658 page_exec_bit);
1659}
1660
1661unsigned long pte_sz_bits(unsigned long sz)
1662{
1663 if (tlb_type == hypervisor) {
1664 switch (sz) {
1665 case 8 * 1024:
1666 default:
1667 return _PAGE_SZ8K_4V;
1668 case 64 * 1024:
1669 return _PAGE_SZ64K_4V;
1670 case 512 * 1024:
1671 return _PAGE_SZ512K_4V;
1672 case 4 * 1024 * 1024:
1673 return _PAGE_SZ4MB_4V;
1674 };
1675 } else {
1676 switch (sz) {
1677 case 8 * 1024:
1678 default:
1679 return _PAGE_SZ8K_4U;
1680 case 64 * 1024:
1681 return _PAGE_SZ64K_4U;
1682 case 512 * 1024:
1683 return _PAGE_SZ512K_4U;
1684 case 4 * 1024 * 1024:
1685 return _PAGE_SZ4MB_4U;
1686 };
1687 }
1688}
1689
1690pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1691{
1692 pte_t pte;
cf627156
DM		 1693
1694 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1695 pte_val(pte) |= (((unsigned long)space) << 32);
1696 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1697
cf627156 1698 return pte;
c4bce90e
DM		 1699}
1700
1701static unsigned long kern_large_tte(unsigned long paddr)
1702{
1703 unsigned long val;
1704
1705 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1706 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1707 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1708 if (tlb_type == hypervisor)
1709 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1710 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1711 _PAGE_EXEC_4V | _PAGE_W_4V);
1712
1713 return val | paddr;
1714}
1715
1716/*
1717 * Translate PROM's mapping we capture at boot time into physical address.
1718 * The second parameter is only set from prom_callback() invocations.
1719 */
1720unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1721{
1722 unsigned long mask;
1723 int i;
1724
1725 mask = _PAGE_PADDR_4U;
1726 if (tlb_type == hypervisor)
1727 mask = _PAGE_PADDR_4V;
1728
1729 for (i = 0; i < prom_trans_ents; i++) {
1730 struct linux_prom_translation *p = &prom_trans[i];
1731
1732 if (promva >= p->virt &&
1733 promva < (p->virt + p->size)) {
1734 unsigned long base = p->data & mask;
1735
1736 if (error)
1737 *error = 0;
1738 return base + (promva & (8192 - 1));
1739 }
1740 }
1741 if (error)
1742 *error = 1;
1743 return 0UL;
1744}
1745
1746/* XXX We should kill off this ugly thing at so me point. XXX */
1747unsigned long sun4u_get_pte(unsigned long addr)
1748{
1749 pgd_t *pgdp;
1750 pud_t *pudp;
1751 pmd_t *pmdp;
1752 pte_t *ptep;
1753 unsigned long mask = _PAGE_PADDR_4U;
1754
1755 if (tlb_type == hypervisor)
1756 mask = _PAGE_PADDR_4V;
1757
1758 if (addr >= PAGE_OFFSET)
1759 return addr & mask;
1760
1761 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1762 return prom_virt_to_phys(addr, NULL);
1763
1764 pgdp = pgd_offset_k(addr);
1765 pudp = pud_offset(pgdp, addr);
1766 pmdp = pmd_offset(pudp, addr);
1767 ptep = pte_offset_kernel(pmdp, addr);
1768
1769 return pte_val(*ptep) & mask;
1770}
1771
1772/* If not locked, zap it. */
1773void __flush_tlb_all(void)
1774{
1775 unsigned long pstate;
1776 int i;
1777
1778 __asm__ __volatile__("flushw\n\t"
1779 "rdpr %%pstate, %0\n\t"
1780 "wrpr %0, %1, %%pstate"
1781 : "=r" (pstate)
1782 : "i" (PSTATE_IE));
1783 if (tlb_type == spitfire) {
1784 for (i = 0; i < 64; i++) {
1785 /* Spitfire Errata #32 workaround */
1786 /* NOTE: Always runs on spitfire, so no
1787 * cheetah+ page size encodings.
1788 */
1789 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1790 "flush %%g6"
1791 : /* No outputs */
1792 : "r" (0),
1793 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1794
1795 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1796 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1797 "membar #Sync"
1798 : /* no outputs */
1799 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1800 spitfire_put_dtlb_data(i, 0x0UL);
1801 }
1802
1803 /* Spitfire Errata #32 workaround */
1804 /* NOTE: Always runs on spitfire, so no
1805 * cheetah+ page size encodings.
1806 */
1807 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1808 "flush %%g6"
1809 : /* No outputs */
1810 : "r" (0),
1811 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1812
1813 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1814 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1815 "membar #Sync"
1816 : /* no outputs */
1817 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1818 spitfire_put_itlb_data(i, 0x0UL);
1819 }
1820 }
1821 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1822 cheetah_flush_dtlb_all();
1823 cheetah_flush_itlb_all();
1824 }
1825 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1826 : : "r" (pstate));
1827}
88d70794
DM		 1828
1829#ifdef CONFIG_MEMORY_HOTPLUG
1830
1831void online_page(struct page *page)
1832{
1833 ClearPageReserved(page);
fcab1e51
NP		 1834 init_page_count(page);
1835 __free_page(page);
88d70794
DM		 1836 totalram_pages++;
1837 num_physpages++;
1838}
1839
1840int remove_memory(u64 start, u64 size)
1841{
1842 return -EINVAL;
1843}
1844
1845#endif /* CONFIG_MEMORY_HOTPLUG */
Linux kernel - Deliverables
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