[deliverable/linux.git] / arch / tile / include / asm / pci.h

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#ifndef _ASM_TILE_PCI_H
#define _ASM_TILE_PCI_H

#include <linux/pci.h>

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	int index;		/* PCI domain number */
	struct pci_bus *root_bus;

	int first_busno;
	int last_busno;

	int hv_cfg_fd[2];	/* config{0,1} fds for this PCIe controller */
	int hv_mem_fd;		/* fd to Hypervisor for MMIO operations */

	struct pci_ops *ops;

	int irq_base;		/* Base IRQ from the Hypervisor	*/
	int plx_gen1;		/* flag for PLX Gen 1 configuration */

	/* Address ranges that are routed to this controller/bridge. */
	struct resource mem_resources[3];
};

/*
 * The hypervisor maps the entirety of CPA-space as bus addresses, so
 * bus addresses are physical addresses.  The networking and block
 * device layers use this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS     1

int __init tile_pci_init(void);

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}

void __devinit pcibios_fixup_bus(struct pci_bus *bus);

#define	TILE_NUM_PCIE	2

#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)

/*
 * This decides whether to display the domain number in /proc.
 */
static inline int pci_proc_domain(struct pci_bus *bus)
{
	return 1;
}

/*
 * pcibios_assign_all_busses() tells whether or not the bus numbers
 * should be reassigned, in case the BIOS didn't do it correctly, or
 * in case we don't have a BIOS and we want to let Linux do it.
 */
static inline int pcibios_assign_all_busses(void)
{
	return 1;
}

/*
 * No special bus mastering setup handling.
 */
static inline void pcibios_set_master(struct pci_dev *dev)
{
}

#define PCIBIOS_MIN_MEM		0
#define PCIBIOS_MIN_IO		0

/*
 * This flag tells if the platform is TILEmpower that needs
 * special configuration for the PLX switch chip.
 */
extern int tile_plx_gen1;

/* Use any cpu for PCI. */
#define cpumask_of_pcibus(bus) cpu_online_mask

/* implement the pci_ DMA API in terms of the generic device dma_ one */
#include <asm-generic/pci-dma-compat.h>

/* generic pci stuff */
#include <asm-generic/pci.h>

#endif /* _ASM_TILE_PCI_H */
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef _ASM_TILE_PCI_H
	16	#define _ASM_TILE_PCI_H
	17
f02cbbe6 CM	18	#include <linux/pci.h>
	19
	20	/*
	21	* Structure of a PCI controller (host bridge)
	22	*/
	23	struct pci_controller {
	24	int index; /* PCI domain number */
	25	struct pci_bus *root_bus;
	26
	27	int first_busno;
	28	int last_busno;
	29
	30	int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
	31	int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
	32
	33	struct pci_ops *ops;
	34
	35	int irq_base; /* Base IRQ from the Hypervisor */
	36	int plx_gen1; /* flag for PLX Gen 1 configuration */
	37
	38	/* Address ranges that are routed to this controller/bridge. */
	39	struct resource mem_resources[3];
	40	};
867e359b CM	41
	42	/*
	43	* The hypervisor maps the entirety of CPA-space as bus addresses, so
	44	* bus addresses are physical addresses. The networking and block
	45	* device layers use this boolean for bounce buffer decisions.
	46	*/
	47	#define PCI_DMA_BUS_IS_PHYS 1
	48
867e359b	49	int __init tile_pci_init(void);
867e359b	50
f02cbbe6 CM	51	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long max);
f02cbbe6 CM	52	static inline void pci_iounmap(struct pci_dev dev, void __iomem addr) {}
867e359b	53
f02cbbe6	54	void __devinit pcibios_fixup_bus(struct pci_bus *bus);
867e359b CM	55
	56	#define TILE_NUM_PCIE 2
	57
	58	#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
	59
	60	/*
	61	* This decides whether to display the domain number in /proc.
	62	*/
	63	static inline int pci_proc_domain(struct pci_bus *bus)
	64	{
	65	return 1;
	66	}
	67
	68	/*
f02cbbe6 CM	69	* pcibios_assign_all_busses() tells whether or not the bus numbers
	70	* should be reassigned, in case the BIOS didn't do it correctly, or
	71	* in case we don't have a BIOS and we want to let Linux do it.
867e359b	72	*/
f02cbbe6 CM	73	static inline int pcibios_assign_all_busses(void)
	74	{
	75	return 1;
	76	}
867e359b	77
f02cbbe6 CM	78	/*
	79	* No special bus mastering setup handling.
	80	*/
867e359b CM	81	static inline void pcibios_set_master(struct pci_dev *dev)
867e359b CM	82	{
867e359b CM	83	}
	84
	85	#define PCIBIOS_MIN_MEM 0
f02cbbe6	86	#define PCIBIOS_MIN_IO 0
867e359b CM	87
	88	/*
	89	* This flag tells if the platform is TILEmpower that needs
	90	* special configuration for the PLX switch chip.
	91	*/
f02cbbe6 CM	92	extern int tile_plx_gen1;
	93
	94	/* Use any cpu for PCI. */
	95	#define cpumask_of_pcibus(bus) cpu_online_mask
867e359b CM	96
	97	/* implement the pci_ DMA API in terms of the generic device dma_ one */
	98	#include <asm-generic/pci-dma-compat.h>
	99
	100	/* generic pci stuff */
	101	#include <asm-generic/pci.h>
	102
867e359b	103	#endif /* _ASM_TILE_PCI_H */