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18aecc2b CM |
1 | /* |
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #ifndef __ARCH_INTERRUPTS_H__ | |
16 | #define __ARCH_INTERRUPTS_H__ | |
17 | ||
7f04f081 | 18 | #ifndef __KERNEL__ |
18aecc2b CM |
19 | /** Mask for an interrupt. */ |
20 | #ifdef __ASSEMBLER__ | |
21 | /* Note: must handle breaking interrupts into high and low words manually. */ | |
22 | #define INT_MASK(intno) (1 << (intno)) | |
23 | #else | |
24 | #define INT_MASK(intno) (1ULL << (intno)) | |
25 | #endif | |
7f04f081 | 26 | #endif |
18aecc2b CM |
27 | |
28 | ||
29 | /** Where a given interrupt executes */ | |
30 | #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8)) | |
31 | ||
32 | /** Where to store a vector for a given interrupt. */ | |
33 | #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0) | |
34 | ||
35 | /** The base address of user-level interrupts. */ | |
36 | #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0) | |
37 | ||
38 | ||
39 | /** Additional synthetic interrupt. */ | |
40 | #define INT_BREAKPOINT (63) | |
41 | ||
42 | #define INT_MEM_ERROR 0 | |
43 | #define INT_SINGLE_STEP_3 1 | |
44 | #define INT_SINGLE_STEP_2 2 | |
45 | #define INT_SINGLE_STEP_1 3 | |
46 | #define INT_SINGLE_STEP_0 4 | |
47 | #define INT_IDN_COMPLETE 5 | |
48 | #define INT_UDN_COMPLETE 6 | |
49 | #define INT_ITLB_MISS 7 | |
50 | #define INT_ILL 8 | |
51 | #define INT_GPV 9 | |
52 | #define INT_IDN_ACCESS 10 | |
53 | #define INT_UDN_ACCESS 11 | |
54 | #define INT_SWINT_3 12 | |
55 | #define INT_SWINT_2 13 | |
56 | #define INT_SWINT_1 14 | |
57 | #define INT_SWINT_0 15 | |
58 | #define INT_ILL_TRANS 16 | |
59 | #define INT_UNALIGN_DATA 17 | |
60 | #define INT_DTLB_MISS 18 | |
61 | #define INT_DTLB_ACCESS 19 | |
62 | #define INT_IDN_FIREWALL 20 | |
63 | #define INT_UDN_FIREWALL 21 | |
64 | #define INT_TILE_TIMER 22 | |
65 | #define INT_AUX_TILE_TIMER 23 | |
66 | #define INT_IDN_TIMER 24 | |
67 | #define INT_UDN_TIMER 25 | |
68 | #define INT_IDN_AVAIL 26 | |
69 | #define INT_UDN_AVAIL 27 | |
70 | #define INT_IPI_3 28 | |
71 | #define INT_IPI_2 29 | |
72 | #define INT_IPI_1 30 | |
73 | #define INT_IPI_0 31 | |
74 | #define INT_PERF_COUNT 32 | |
75 | #define INT_AUX_PERF_COUNT 33 | |
76 | #define INT_INTCTRL_3 34 | |
77 | #define INT_INTCTRL_2 35 | |
78 | #define INT_INTCTRL_1 36 | |
79 | #define INT_INTCTRL_0 37 | |
80 | #define INT_BOOT_ACCESS 38 | |
81 | #define INT_WORLD_ACCESS 39 | |
82 | #define INT_I_ASID 40 | |
83 | #define INT_D_ASID 41 | |
84 | #define INT_DOUBLE_FAULT 42 | |
85 | ||
86 | #define NUM_INTERRUPTS 43 | |
87 | ||
88 | #ifndef __ASSEMBLER__ | |
89 | #define QUEUED_INTERRUPTS ( \ | |
7f04f081 CM |
90 | (1ULL << INT_MEM_ERROR) | \ |
91 | (1ULL << INT_IDN_COMPLETE) | \ | |
92 | (1ULL << INT_UDN_COMPLETE) | \ | |
93 | (1ULL << INT_IDN_FIREWALL) | \ | |
94 | (1ULL << INT_UDN_FIREWALL) | \ | |
95 | (1ULL << INT_TILE_TIMER) | \ | |
96 | (1ULL << INT_AUX_TILE_TIMER) | \ | |
97 | (1ULL << INT_IDN_TIMER) | \ | |
98 | (1ULL << INT_UDN_TIMER) | \ | |
99 | (1ULL << INT_IDN_AVAIL) | \ | |
100 | (1ULL << INT_UDN_AVAIL) | \ | |
101 | (1ULL << INT_IPI_3) | \ | |
102 | (1ULL << INT_IPI_2) | \ | |
103 | (1ULL << INT_IPI_1) | \ | |
104 | (1ULL << INT_IPI_0) | \ | |
105 | (1ULL << INT_PERF_COUNT) | \ | |
106 | (1ULL << INT_AUX_PERF_COUNT) | \ | |
107 | (1ULL << INT_INTCTRL_3) | \ | |
108 | (1ULL << INT_INTCTRL_2) | \ | |
109 | (1ULL << INT_INTCTRL_1) | \ | |
110 | (1ULL << INT_INTCTRL_0) | \ | |
111 | (1ULL << INT_BOOT_ACCESS) | \ | |
112 | (1ULL << INT_WORLD_ACCESS) | \ | |
113 | (1ULL << INT_I_ASID) | \ | |
114 | (1ULL << INT_D_ASID) | \ | |
115 | (1ULL << INT_DOUBLE_FAULT) | \ | |
18aecc2b CM |
116 | 0) |
117 | #define NONQUEUED_INTERRUPTS ( \ | |
7f04f081 CM |
118 | (1ULL << INT_SINGLE_STEP_3) | \ |
119 | (1ULL << INT_SINGLE_STEP_2) | \ | |
120 | (1ULL << INT_SINGLE_STEP_1) | \ | |
121 | (1ULL << INT_SINGLE_STEP_0) | \ | |
122 | (1ULL << INT_ITLB_MISS) | \ | |
123 | (1ULL << INT_ILL) | \ | |
124 | (1ULL << INT_GPV) | \ | |
125 | (1ULL << INT_IDN_ACCESS) | \ | |
126 | (1ULL << INT_UDN_ACCESS) | \ | |
127 | (1ULL << INT_SWINT_3) | \ | |
128 | (1ULL << INT_SWINT_2) | \ | |
129 | (1ULL << INT_SWINT_1) | \ | |
130 | (1ULL << INT_SWINT_0) | \ | |
131 | (1ULL << INT_ILL_TRANS) | \ | |
132 | (1ULL << INT_UNALIGN_DATA) | \ | |
133 | (1ULL << INT_DTLB_MISS) | \ | |
134 | (1ULL << INT_DTLB_ACCESS) | \ | |
18aecc2b CM |
135 | 0) |
136 | #define CRITICAL_MASKED_INTERRUPTS ( \ | |
7f04f081 CM |
137 | (1ULL << INT_MEM_ERROR) | \ |
138 | (1ULL << INT_SINGLE_STEP_3) | \ | |
139 | (1ULL << INT_SINGLE_STEP_2) | \ | |
140 | (1ULL << INT_SINGLE_STEP_1) | \ | |
141 | (1ULL << INT_SINGLE_STEP_0) | \ | |
142 | (1ULL << INT_IDN_COMPLETE) | \ | |
143 | (1ULL << INT_UDN_COMPLETE) | \ | |
144 | (1ULL << INT_IDN_FIREWALL) | \ | |
145 | (1ULL << INT_UDN_FIREWALL) | \ | |
146 | (1ULL << INT_TILE_TIMER) | \ | |
147 | (1ULL << INT_AUX_TILE_TIMER) | \ | |
148 | (1ULL << INT_IDN_TIMER) | \ | |
149 | (1ULL << INT_UDN_TIMER) | \ | |
150 | (1ULL << INT_IDN_AVAIL) | \ | |
151 | (1ULL << INT_UDN_AVAIL) | \ | |
152 | (1ULL << INT_IPI_3) | \ | |
153 | (1ULL << INT_IPI_2) | \ | |
154 | (1ULL << INT_IPI_1) | \ | |
155 | (1ULL << INT_IPI_0) | \ | |
156 | (1ULL << INT_PERF_COUNT) | \ | |
157 | (1ULL << INT_AUX_PERF_COUNT) | \ | |
158 | (1ULL << INT_INTCTRL_3) | \ | |
159 | (1ULL << INT_INTCTRL_2) | \ | |
160 | (1ULL << INT_INTCTRL_1) | \ | |
161 | (1ULL << INT_INTCTRL_0) | \ | |
18aecc2b CM |
162 | 0) |
163 | #define CRITICAL_UNMASKED_INTERRUPTS ( \ | |
7f04f081 CM |
164 | (1ULL << INT_ITLB_MISS) | \ |
165 | (1ULL << INT_ILL) | \ | |
166 | (1ULL << INT_GPV) | \ | |
167 | (1ULL << INT_IDN_ACCESS) | \ | |
168 | (1ULL << INT_UDN_ACCESS) | \ | |
169 | (1ULL << INT_SWINT_3) | \ | |
170 | (1ULL << INT_SWINT_2) | \ | |
171 | (1ULL << INT_SWINT_1) | \ | |
172 | (1ULL << INT_SWINT_0) | \ | |
173 | (1ULL << INT_ILL_TRANS) | \ | |
174 | (1ULL << INT_UNALIGN_DATA) | \ | |
175 | (1ULL << INT_DTLB_MISS) | \ | |
176 | (1ULL << INT_DTLB_ACCESS) | \ | |
177 | (1ULL << INT_BOOT_ACCESS) | \ | |
178 | (1ULL << INT_WORLD_ACCESS) | \ | |
179 | (1ULL << INT_I_ASID) | \ | |
180 | (1ULL << INT_D_ASID) | \ | |
181 | (1ULL << INT_DOUBLE_FAULT) | \ | |
18aecc2b CM |
182 | 0) |
183 | #define MASKABLE_INTERRUPTS ( \ | |
7f04f081 CM |
184 | (1ULL << INT_MEM_ERROR) | \ |
185 | (1ULL << INT_SINGLE_STEP_3) | \ | |
186 | (1ULL << INT_SINGLE_STEP_2) | \ | |
187 | (1ULL << INT_SINGLE_STEP_1) | \ | |
188 | (1ULL << INT_SINGLE_STEP_0) | \ | |
189 | (1ULL << INT_IDN_COMPLETE) | \ | |
190 | (1ULL << INT_UDN_COMPLETE) | \ | |
191 | (1ULL << INT_IDN_FIREWALL) | \ | |
192 | (1ULL << INT_UDN_FIREWALL) | \ | |
193 | (1ULL << INT_TILE_TIMER) | \ | |
194 | (1ULL << INT_AUX_TILE_TIMER) | \ | |
195 | (1ULL << INT_IDN_TIMER) | \ | |
196 | (1ULL << INT_UDN_TIMER) | \ | |
197 | (1ULL << INT_IDN_AVAIL) | \ | |
198 | (1ULL << INT_UDN_AVAIL) | \ | |
199 | (1ULL << INT_IPI_3) | \ | |
200 | (1ULL << INT_IPI_2) | \ | |
201 | (1ULL << INT_IPI_1) | \ | |
202 | (1ULL << INT_IPI_0) | \ | |
203 | (1ULL << INT_PERF_COUNT) | \ | |
204 | (1ULL << INT_AUX_PERF_COUNT) | \ | |
205 | (1ULL << INT_INTCTRL_3) | \ | |
206 | (1ULL << INT_INTCTRL_2) | \ | |
207 | (1ULL << INT_INTCTRL_1) | \ | |
208 | (1ULL << INT_INTCTRL_0) | \ | |
18aecc2b CM |
209 | 0) |
210 | #define UNMASKABLE_INTERRUPTS ( \ | |
7f04f081 CM |
211 | (1ULL << INT_ITLB_MISS) | \ |
212 | (1ULL << INT_ILL) | \ | |
213 | (1ULL << INT_GPV) | \ | |
214 | (1ULL << INT_IDN_ACCESS) | \ | |
215 | (1ULL << INT_UDN_ACCESS) | \ | |
216 | (1ULL << INT_SWINT_3) | \ | |
217 | (1ULL << INT_SWINT_2) | \ | |
218 | (1ULL << INT_SWINT_1) | \ | |
219 | (1ULL << INT_SWINT_0) | \ | |
220 | (1ULL << INT_ILL_TRANS) | \ | |
221 | (1ULL << INT_UNALIGN_DATA) | \ | |
222 | (1ULL << INT_DTLB_MISS) | \ | |
223 | (1ULL << INT_DTLB_ACCESS) | \ | |
224 | (1ULL << INT_BOOT_ACCESS) | \ | |
225 | (1ULL << INT_WORLD_ACCESS) | \ | |
226 | (1ULL << INT_I_ASID) | \ | |
227 | (1ULL << INT_D_ASID) | \ | |
228 | (1ULL << INT_DOUBLE_FAULT) | \ | |
18aecc2b CM |
229 | 0) |
230 | #define SYNC_INTERRUPTS ( \ | |
7f04f081 CM |
231 | (1ULL << INT_SINGLE_STEP_3) | \ |
232 | (1ULL << INT_SINGLE_STEP_2) | \ | |
233 | (1ULL << INT_SINGLE_STEP_1) | \ | |
234 | (1ULL << INT_SINGLE_STEP_0) | \ | |
235 | (1ULL << INT_IDN_COMPLETE) | \ | |
236 | (1ULL << INT_UDN_COMPLETE) | \ | |
237 | (1ULL << INT_ITLB_MISS) | \ | |
238 | (1ULL << INT_ILL) | \ | |
239 | (1ULL << INT_GPV) | \ | |
240 | (1ULL << INT_IDN_ACCESS) | \ | |
241 | (1ULL << INT_UDN_ACCESS) | \ | |
242 | (1ULL << INT_SWINT_3) | \ | |
243 | (1ULL << INT_SWINT_2) | \ | |
244 | (1ULL << INT_SWINT_1) | \ | |
245 | (1ULL << INT_SWINT_0) | \ | |
246 | (1ULL << INT_ILL_TRANS) | \ | |
247 | (1ULL << INT_UNALIGN_DATA) | \ | |
248 | (1ULL << INT_DTLB_MISS) | \ | |
249 | (1ULL << INT_DTLB_ACCESS) | \ | |
18aecc2b CM |
250 | 0) |
251 | #define NON_SYNC_INTERRUPTS ( \ | |
7f04f081 CM |
252 | (1ULL << INT_MEM_ERROR) | \ |
253 | (1ULL << INT_IDN_FIREWALL) | \ | |
254 | (1ULL << INT_UDN_FIREWALL) | \ | |
255 | (1ULL << INT_TILE_TIMER) | \ | |
256 | (1ULL << INT_AUX_TILE_TIMER) | \ | |
257 | (1ULL << INT_IDN_TIMER) | \ | |
258 | (1ULL << INT_UDN_TIMER) | \ | |
259 | (1ULL << INT_IDN_AVAIL) | \ | |
260 | (1ULL << INT_UDN_AVAIL) | \ | |
261 | (1ULL << INT_IPI_3) | \ | |
262 | (1ULL << INT_IPI_2) | \ | |
263 | (1ULL << INT_IPI_1) | \ | |
264 | (1ULL << INT_IPI_0) | \ | |
265 | (1ULL << INT_PERF_COUNT) | \ | |
266 | (1ULL << INT_AUX_PERF_COUNT) | \ | |
267 | (1ULL << INT_INTCTRL_3) | \ | |
268 | (1ULL << INT_INTCTRL_2) | \ | |
269 | (1ULL << INT_INTCTRL_1) | \ | |
270 | (1ULL << INT_INTCTRL_0) | \ | |
271 | (1ULL << INT_BOOT_ACCESS) | \ | |
272 | (1ULL << INT_WORLD_ACCESS) | \ | |
273 | (1ULL << INT_I_ASID) | \ | |
274 | (1ULL << INT_D_ASID) | \ | |
275 | (1ULL << INT_DOUBLE_FAULT) | \ | |
18aecc2b CM |
276 | 0) |
277 | #endif /* !__ASSEMBLER__ */ | |
278 | #endif /* !__ARCH_INTERRUPTS_H__ */ |