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12962267 CM |
1 | /* |
2 | * Copyright 2012 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/mmzone.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/capability.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/msi.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/uaccess.h> | |
28 | #include <linux/ctype.h> | |
29 | ||
30 | #include <asm/processor.h> | |
31 | #include <asm/sections.h> | |
32 | #include <asm/byteorder.h> | |
33 | ||
34 | #include <gxio/iorpc_globals.h> | |
35 | #include <gxio/kiorpc.h> | |
36 | #include <gxio/trio.h> | |
37 | #include <gxio/iorpc_trio.h> | |
38 | #include <hv/drv_trio_intf.h> | |
39 | ||
40 | #include <arch/sim.h> | |
41 | ||
42 | /* | |
41bb38fc | 43 | * This file containes the routines to search for PCI buses, |
12962267 | 44 | * enumerate the buses, and configure any attached devices. |
12962267 CM |
45 | */ |
46 | ||
47 | #define DEBUG_PCI_CFG 0 | |
48 | ||
49 | #if DEBUG_PCI_CFG | |
50 | #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \ | |
51 | pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \ | |
52 | size, val, bus, dev, func, offset & 0xFFF); | |
53 | #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \ | |
54 | pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \ | |
55 | size, val, bus, dev, func, offset & 0xFFF); | |
56 | #else | |
57 | #define TRACE_CFG_WR(...) | |
58 | #define TRACE_CFG_RD(...) | |
59 | #endif | |
60 | ||
b881bc46 | 61 | static int pci_probe = 1; |
12962267 CM |
62 | |
63 | /* Information on the PCIe RC ports configuration. */ | |
b881bc46 | 64 | static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; |
12962267 CM |
65 | |
66 | /* | |
67 | * On some platforms with one or more Gx endpoint ports, we need to | |
68 | * delay the PCIe RC port probe for a few seconds to work around | |
69 | * a HW PCIe link-training bug. The exact delay is specified with | |
70 | * a kernel boot argument in the form of "pcie_rc_delay=T,P,S", | |
71 | * where T is the TRIO instance number, P is the port number and S is | |
b3ad73a3 CM |
72 | * the delay in seconds. If the argument is specified, but the delay is |
73 | * not provided, the value will be DEFAULT_RC_DELAY. | |
12962267 | 74 | */ |
b881bc46 | 75 | static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; |
12962267 CM |
76 | |
77 | /* Default number of seconds that the PCIe RC port probe can be delayed. */ | |
78 | #define DEFAULT_RC_DELAY 10 | |
79 | ||
cf89c426 CM |
80 | /* The PCI I/O space size in each PCI domain. */ |
81 | #define IO_SPACE_SIZE 0x10000 | |
82 | ||
1c43649a CM |
83 | /* Provide shorter versions of some very long constant names. */ |
84 | #define AUTO_CONFIG_RC \ | |
85 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC | |
86 | #define AUTO_CONFIG_RC_G1 \ | |
87 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1 | |
88 | #define AUTO_CONFIG_EP \ | |
89 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT | |
90 | #define AUTO_CONFIG_EP_G1 \ | |
91 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 | |
92 | ||
12962267 | 93 | /* Array of the PCIe ports configuration info obtained from the BIB. */ |
8d9e53b9 | 94 | struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO]; |
12962267 | 95 | |
1c43649a CM |
96 | /* Number of configured TRIO instances. */ |
97 | int num_trio_shims; | |
98 | ||
12962267 CM |
99 | /* All drivers share the TRIO contexts defined here. */ |
100 | gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; | |
101 | ||
102 | /* Pointer to an array of PCIe RC controllers. */ | |
103 | struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; | |
104 | int num_rc_controllers; | |
12962267 CM |
105 | |
106 | static struct pci_ops tile_cfg_ops; | |
107 | ||
108 | /* Mask of CPUs that should receive PCIe interrupts. */ | |
109 | static struct cpumask intr_cpus_map; | |
110 | ||
eafa5c8a | 111 | /* We don't need to worry about the alignment of resources. */ |
12962267 | 112 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
eafa5c8a CM |
113 | resource_size_t size, |
114 | resource_size_t align) | |
12962267 CM |
115 | { |
116 | return res->start; | |
117 | } | |
118 | EXPORT_SYMBOL(pcibios_align_resource); | |
119 | ||
12962267 CM |
120 | /* |
121 | * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #. | |
122 | * For now, we simply send interrupts to non-dataplane CPUs. | |
123 | * We may implement methods to allow user to specify the target CPUs, | |
124 | * e.g. via boot arguments. | |
125 | */ | |
126 | static int tile_irq_cpu(int irq) | |
127 | { | |
128 | unsigned int count; | |
129 | int i = 0; | |
130 | int cpu; | |
131 | ||
132 | count = cpumask_weight(&intr_cpus_map); | |
133 | if (unlikely(count == 0)) { | |
134 | pr_warning("intr_cpus_map empty, interrupts will be" | |
135 | " delievered to dataplane tiles\n"); | |
136 | return irq % (smp_height * smp_width); | |
137 | } | |
138 | ||
139 | count = irq % count; | |
140 | for_each_cpu(cpu, &intr_cpus_map) { | |
141 | if (i++ == count) | |
142 | break; | |
143 | } | |
144 | return cpu; | |
145 | } | |
146 | ||
eafa5c8a | 147 | /* Open a file descriptor to the TRIO shim. */ |
b881bc46 | 148 | static int tile_pcie_open(int trio_index) |
12962267 CM |
149 | { |
150 | gxio_trio_context_t *context = &trio_contexts[trio_index]; | |
151 | int ret; | |
1c43649a | 152 | int mac; |
12962267 | 153 | |
eafa5c8a | 154 | /* This opens a file descriptor to the TRIO shim. */ |
12962267 CM |
155 | ret = gxio_trio_init(context, trio_index); |
156 | if (ret < 0) | |
1c43649a | 157 | goto gxio_trio_init_failure; |
12962267 | 158 | |
eafa5c8a | 159 | /* Allocate an ASID for the kernel. */ |
12962267 CM |
160 | ret = gxio_trio_alloc_asids(context, 1, 0, 0); |
161 | if (ret < 0) { | |
162 | pr_err("PCI: ASID alloc failure on TRIO %d, give up\n", | |
163 | trio_index); | |
164 | goto asid_alloc_failure; | |
165 | } | |
166 | ||
167 | context->asid = ret; | |
168 | ||
169 | #ifdef USE_SHARED_PCIE_CONFIG_REGION | |
170 | /* | |
171 | * Alloc a PIO region for config access, shared by all MACs per TRIO. | |
172 | * This shouldn't fail since the kernel is supposed to the first | |
173 | * client of the TRIO's PIO regions. | |
174 | */ | |
175 | ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0); | |
176 | if (ret < 0) { | |
177 | pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n", | |
178 | trio_index); | |
179 | goto pio_alloc_failure; | |
180 | } | |
181 | ||
182 | context->pio_cfg_index = ret; | |
183 | ||
184 | /* | |
185 | * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter | |
186 | * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR. | |
187 | */ | |
188 | ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index, | |
189 | 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE); | |
190 | if (ret < 0) { | |
191 | pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n", | |
192 | trio_index); | |
193 | goto pio_alloc_failure; | |
194 | } | |
195 | #endif | |
196 | ||
1c43649a | 197 | /* Get the properties of the PCIe ports on this TRIO instance. */ |
8d9e53b9 | 198 | ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]); |
1c43649a CM |
199 | if (ret < 0) { |
200 | pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d," | |
201 | " on TRIO %d\n", ret, trio_index); | |
202 | goto get_port_property_failure; | |
203 | } | |
204 | ||
205 | context->mmio_base_mac = | |
206 | iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE); | |
207 | if (context->mmio_base_mac == NULL) { | |
208 | pr_err("PCI: TRIO config space mapping failure, error %d," | |
209 | " on TRIO %d\n", ret, trio_index); | |
210 | ret = -ENOMEM; | |
211 | ||
212 | goto trio_mmio_mapping_failure; | |
213 | } | |
214 | ||
215 | /* Check the port strap state which will override the BIB setting. */ | |
216 | for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) { | |
217 | TRIO_PCIE_INTFC_PORT_CONFIG_t port_config; | |
218 | unsigned int reg_offset; | |
219 | ||
220 | /* Ignore ports that are not specified in the BIB. */ | |
8d9e53b9 CM |
221 | if (!pcie_ports[trio_index].ports[mac].allow_rc && |
222 | !pcie_ports[trio_index].ports[mac].allow_ep) | |
1c43649a CM |
223 | continue; |
224 | ||
225 | reg_offset = | |
226 | (TRIO_PCIE_INTFC_PORT_CONFIG << | |
227 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
228 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
229 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT) | | |
230 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
231 | ||
232 | port_config.word = | |
233 | __gxio_mmio_read(context->mmio_base_mac + reg_offset); | |
234 | ||
235 | if (port_config.strap_state != AUTO_CONFIG_RC && | |
236 | port_config.strap_state != AUTO_CONFIG_RC_G1) { | |
237 | /* | |
238 | * If this is really intended to be an EP port, record | |
239 | * it so that the endpoint driver will know about it. | |
240 | */ | |
241 | if (port_config.strap_state == AUTO_CONFIG_EP || | |
242 | port_config.strap_state == AUTO_CONFIG_EP_G1) | |
8d9e53b9 | 243 | pcie_ports[trio_index].ports[mac].allow_ep = 1; |
1c43649a CM |
244 | } |
245 | } | |
246 | ||
12962267 CM |
247 | return ret; |
248 | ||
1c43649a CM |
249 | trio_mmio_mapping_failure: |
250 | get_port_property_failure: | |
12962267 CM |
251 | asid_alloc_failure: |
252 | #ifdef USE_SHARED_PCIE_CONFIG_REGION | |
253 | pio_alloc_failure: | |
254 | #endif | |
255 | hv_dev_close(context->fd); | |
1c43649a CM |
256 | gxio_trio_init_failure: |
257 | context->fd = -1; | |
12962267 CM |
258 | |
259 | return ret; | |
260 | } | |
261 | ||
1c43649a CM |
262 | static int __init tile_trio_init(void) |
263 | { | |
264 | int i; | |
265 | ||
266 | /* We loop over all the TRIO shims. */ | |
267 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | |
268 | if (tile_pcie_open(i) < 0) | |
269 | continue; | |
270 | num_trio_shims++; | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | postcore_initcall(tile_trio_init); | |
276 | ||
eafa5c8a | 277 | static void tilegx_legacy_irq_ack(struct irq_data *d) |
12962267 CM |
278 | { |
279 | __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq); | |
280 | } | |
281 | ||
eafa5c8a | 282 | static void tilegx_legacy_irq_mask(struct irq_data *d) |
12962267 CM |
283 | { |
284 | __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); | |
285 | } | |
286 | ||
eafa5c8a | 287 | static void tilegx_legacy_irq_unmask(struct irq_data *d) |
12962267 CM |
288 | { |
289 | __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); | |
290 | } | |
291 | ||
292 | static struct irq_chip tilegx_legacy_irq_chip = { | |
293 | .name = "tilegx_legacy_irq", | |
294 | .irq_ack = tilegx_legacy_irq_ack, | |
295 | .irq_mask = tilegx_legacy_irq_mask, | |
296 | .irq_unmask = tilegx_legacy_irq_unmask, | |
297 | ||
298 | /* TBD: support set_affinity. */ | |
299 | }; | |
300 | ||
301 | /* | |
302 | * This is a wrapper function of the kernel level-trigger interrupt | |
303 | * handler handle_level_irq() for PCI legacy interrupts. The TRIO | |
304 | * is configured such that only INTx Assert interrupts are proxied | |
305 | * to Linux which just calls handle_level_irq() after clearing the | |
306 | * MAC INTx Assert status bit associated with this interrupt. | |
307 | */ | |
eafa5c8a | 308 | static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc) |
12962267 CM |
309 | { |
310 | struct pci_controller *controller = irq_desc_get_handler_data(desc); | |
311 | gxio_trio_context_t *trio_context = controller->trio; | |
312 | uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc); | |
313 | int mac = controller->mac; | |
314 | unsigned int reg_offset; | |
315 | uint64_t level_mask; | |
316 | ||
317 | handle_level_irq(irq, desc); | |
318 | ||
319 | /* | |
320 | * Clear the INTx Level status, otherwise future interrupts are | |
321 | * not sent. | |
322 | */ | |
323 | reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS << | |
324 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
325 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
326 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
327 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
328 | ||
329 | level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx; | |
330 | ||
331 | __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask); | |
332 | } | |
333 | ||
334 | /* | |
335 | * Create kernel irqs and set up the handlers for the legacy interrupts. | |
336 | * Also some minimum initialization for the MSI support. | |
337 | */ | |
b881bc46 | 338 | static int tile_init_irqs(struct pci_controller *controller) |
12962267 CM |
339 | { |
340 | int i; | |
341 | int j; | |
342 | int irq; | |
343 | int result; | |
344 | ||
345 | cpumask_copy(&intr_cpus_map, cpu_online_mask); | |
346 | ||
347 | ||
348 | for (i = 0; i < 4; i++) { | |
349 | gxio_trio_context_t *context = controller->trio; | |
350 | int cpu; | |
351 | ||
352 | /* Ask the kernel to allocate an IRQ. */ | |
353 | irq = create_irq(); | |
354 | if (irq < 0) { | |
355 | pr_err("PCI: no free irq vectors, failed for %d\n", i); | |
356 | ||
357 | goto free_irqs; | |
358 | } | |
359 | controller->irq_intx_table[i] = irq; | |
360 | ||
361 | /* Distribute the 4 IRQs to different tiles. */ | |
362 | cpu = tile_irq_cpu(irq); | |
363 | ||
364 | /* Configure the TRIO intr binding for this IRQ. */ | |
365 | result = gxio_trio_config_legacy_intr(context, cpu_x(cpu), | |
366 | cpu_y(cpu), KERNEL_PL, | |
367 | irq, controller->mac, i); | |
368 | if (result < 0) { | |
369 | pr_err("PCI: MAC intx config failed for %d\n", i); | |
370 | ||
371 | goto free_irqs; | |
372 | } | |
373 | ||
eafa5c8a | 374 | /* Register the IRQ handler with the kernel. */ |
12962267 CM |
375 | irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip, |
376 | trio_handle_level_irq); | |
377 | irq_set_chip_data(irq, (void *)(uint64_t)i); | |
378 | irq_set_handler_data(irq, controller); | |
379 | } | |
380 | ||
381 | return 0; | |
382 | ||
383 | free_irqs: | |
384 | for (j = 0; j < i; j++) | |
385 | destroy_irq(controller->irq_intx_table[j]); | |
386 | ||
387 | return -1; | |
388 | } | |
389 | ||
1c43649a CM |
390 | /* |
391 | * Return 1 if the port is strapped to operate in RC mode. | |
392 | */ | |
393 | static int | |
394 | strapped_for_rc(gxio_trio_context_t *trio_context, int mac) | |
395 | { | |
396 | TRIO_PCIE_INTFC_PORT_CONFIG_t port_config; | |
397 | unsigned int reg_offset; | |
398 | ||
399 | /* Check the port configuration. */ | |
400 | reg_offset = | |
401 | (TRIO_PCIE_INTFC_PORT_CONFIG << | |
402 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
403 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
404 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT) | | |
405 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
406 | port_config.word = | |
407 | __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset); | |
408 | ||
409 | if (port_config.strap_state == AUTO_CONFIG_RC || | |
410 | port_config.strap_state == AUTO_CONFIG_RC_G1) | |
411 | return 1; | |
412 | else | |
413 | return 0; | |
414 | } | |
415 | ||
12962267 | 416 | /* |
12962267 CM |
417 | * Find valid controllers and fill in pci_controller structs for each |
418 | * of them. | |
419 | * | |
1c43649a | 420 | * Return the number of controllers discovered. |
12962267 CM |
421 | */ |
422 | int __init tile_pci_init(void) | |
423 | { | |
12962267 CM |
424 | int ctl_index = 0; |
425 | int i, j; | |
426 | ||
427 | if (!pci_probe) { | |
428 | pr_info("PCI: disabled by boot argument\n"); | |
429 | return 0; | |
430 | } | |
431 | ||
432 | pr_info("PCI: Searching for controllers...\n"); | |
433 | ||
12962267 CM |
434 | if (num_trio_shims == 0 || sim_is_simulator()) |
435 | return 0; | |
436 | ||
437 | /* | |
8d9e53b9 | 438 | * Now determine which PCIe ports are configured to operate in RC |
5026dafa CM |
439 | * mode. There is a differece in the port configuration capability |
440 | * between the Gx36 and Gx72 devices. | |
441 | * | |
442 | * The Gx36 has configuration capability for each of the 3 PCIe | |
443 | * interfaces (disable, auto endpoint, auto RC, etc.). | |
444 | * On the Gx72, you can only select one of the 3 PCIe interfaces per | |
445 | * TRIO to train automatically. Further, the allowable training modes | |
446 | * are reduced to four options (auto endpoint, auto RC, stream x1, | |
447 | * stream x4). | |
448 | * | |
449 | * For Gx36 ports, it must be allowed to be in RC mode by the | |
8d9e53b9 CM |
450 | * Board Information Block, and the hardware strapping pins must be |
451 | * set to RC mode. | |
5026dafa CM |
452 | * |
453 | * For Gx72 ports, the port will operate in RC mode if either of the | |
454 | * following is true: | |
455 | * 1. It is allowed to be in RC mode by the Board Information Block, | |
456 | * and the BIB doesn't allow the EP mode. | |
457 | * 2. It is allowed to be in either the RC or the EP mode by the BIB, | |
458 | * and the hardware strapping pin is set to RC mode. | |
12962267 CM |
459 | */ |
460 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | |
461 | gxio_trio_context_t *context = &trio_contexts[i]; | |
12962267 CM |
462 | |
463 | if (context->fd < 0) | |
464 | continue; | |
465 | ||
12962267 | 466 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { |
5026dafa CM |
467 | int is_rc = 0; |
468 | ||
469 | if (pcie_ports[i].is_gx72 && | |
470 | pcie_ports[i].ports[j].allow_rc) { | |
471 | if (!pcie_ports[i].ports[j].allow_ep || | |
472 | strapped_for_rc(context, j)) | |
473 | is_rc = 1; | |
474 | } else if (pcie_ports[i].ports[j].allow_rc && | |
475 | strapped_for_rc(context, j)) { | |
476 | is_rc = 1; | |
477 | } | |
478 | if (is_rc) { | |
12962267 CM |
479 | pcie_rc[i][j] = 1; |
480 | num_rc_controllers++; | |
481 | } | |
12962267 CM |
482 | } |
483 | } | |
484 | ||
eafa5c8a | 485 | /* Return if no PCIe ports are configured to operate in RC mode. */ |
12962267 CM |
486 | if (num_rc_controllers == 0) |
487 | return 0; | |
488 | ||
eafa5c8a | 489 | /* Set the TRIO pointer and MAC index for each PCIe RC port. */ |
12962267 CM |
490 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { |
491 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { | |
492 | if (pcie_rc[i][j]) { | |
493 | pci_controllers[ctl_index].trio = | |
494 | &trio_contexts[i]; | |
495 | pci_controllers[ctl_index].mac = j; | |
496 | pci_controllers[ctl_index].trio_index = i; | |
497 | ctl_index++; | |
498 | if (ctl_index == num_rc_controllers) | |
499 | goto out; | |
500 | } | |
501 | } | |
502 | } | |
503 | ||
504 | out: | |
eafa5c8a | 505 | /* Configure each PCIe RC port. */ |
12962267 | 506 | for (i = 0; i < num_rc_controllers; i++) { |
12962267 | 507 | |
eafa5c8a | 508 | /* Configure the PCIe MAC to run in RC mode. */ |
12962267 CM |
509 | struct pci_controller *controller = &pci_controllers[i]; |
510 | ||
511 | controller->index = i; | |
12962267 CM |
512 | controller->ops = &tile_cfg_ops; |
513 | ||
cf89c426 CM |
514 | controller->io_space.start = PCIBIOS_MIN_IO + |
515 | (i * IO_SPACE_SIZE); | |
516 | controller->io_space.end = controller->io_space.start + | |
517 | IO_SPACE_SIZE - 1; | |
518 | BUG_ON(controller->io_space.end > IO_SPACE_LIMIT); | |
519 | controller->io_space.flags = IORESOURCE_IO; | |
520 | snprintf(controller->io_space_name, | |
521 | sizeof(controller->io_space_name), | |
522 | "PCI I/O domain %d", i); | |
523 | controller->io_space.name = controller->io_space_name; | |
524 | ||
f6d2ce00 CM |
525 | /* |
526 | * The PCI memory resource is located above the PA space. | |
527 | * For every host bridge, the BAR window or the MMIO aperture | |
528 | * is in range [3GB, 4GB - 1] of a 4GB space beyond the | |
529 | * PA space. | |
530 | */ | |
f6d2ce00 CM |
531 | controller->mem_offset = TILE_PCI_MEM_START + |
532 | (i * TILE_PCI_BAR_WINDOW_TOP); | |
533 | controller->mem_space.start = controller->mem_offset + | |
534 | TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE; | |
535 | controller->mem_space.end = controller->mem_offset + | |
536 | TILE_PCI_BAR_WINDOW_TOP - 1; | |
537 | controller->mem_space.flags = IORESOURCE_MEM; | |
538 | snprintf(controller->mem_space_name, | |
539 | sizeof(controller->mem_space_name), | |
540 | "PCI mem domain %d", i); | |
541 | controller->mem_space.name = controller->mem_space_name; | |
12962267 CM |
542 | } |
543 | ||
544 | return num_rc_controllers; | |
545 | } | |
546 | ||
547 | /* | |
548 | * (pin - 1) converts from the PCI standard's [1:4] convention to | |
549 | * a normal [0:3] range. | |
550 | */ | |
551 | static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin) | |
552 | { | |
553 | struct pci_controller *controller = | |
554 | (struct pci_controller *)dev->sysdata; | |
555 | return controller->irq_intx_table[pin - 1]; | |
556 | } | |
557 | ||
b881bc46 | 558 | static void fixup_read_and_payload_sizes(struct pci_controller *controller) |
12962267 CM |
559 | { |
560 | gxio_trio_context_t *trio_context = controller->trio; | |
561 | struct pci_bus *root_bus = controller->root_bus; | |
562 | TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control; | |
563 | TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap; | |
564 | unsigned int reg_offset; | |
565 | struct pci_bus *child; | |
566 | int mac; | |
567 | int err; | |
568 | ||
569 | mac = controller->mac; | |
570 | ||
eafa5c8a | 571 | /* Set our max read request size to be 4KB. */ |
12962267 CM |
572 | reg_offset = |
573 | (TRIO_PCIE_RC_DEVICE_CONTROL << | |
574 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
575 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
576 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
577 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
578 | ||
579 | dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac + | |
eafa5c8a | 580 | reg_offset); |
12962267 CM |
581 | dev_control.max_read_req_sz = 5; |
582 | __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, | |
eafa5c8a | 583 | dev_control.word); |
12962267 CM |
584 | |
585 | /* | |
586 | * Set the max payload size supported by this Gx PCIe MAC. | |
587 | * Though Gx PCIe supports Max Payload Size of up to 1024 bytes, | |
588 | * experiments have shown that setting MPS to 256 yields the | |
589 | * best performance. | |
590 | */ | |
591 | reg_offset = | |
592 | (TRIO_PCIE_RC_DEVICE_CAP << | |
593 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
594 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
595 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
596 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
597 | ||
598 | rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac + | |
eafa5c8a | 599 | reg_offset); |
12962267 CM |
600 | rc_dev_cap.mps_sup = 1; |
601 | __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, | |
eafa5c8a | 602 | rc_dev_cap.word); |
12962267 CM |
603 | |
604 | /* Configure PCI Express MPS setting. */ | |
605 | list_for_each_entry(child, &root_bus->children, node) { | |
606 | struct pci_dev *self = child->self; | |
607 | if (!self) | |
608 | continue; | |
609 | ||
610 | pcie_bus_configure_settings(child, self->pcie_mpss); | |
611 | } | |
612 | ||
613 | /* | |
614 | * Set the mac_config register in trio based on the MPS/MRS of the link. | |
615 | */ | |
616 | reg_offset = | |
617 | (TRIO_PCIE_RC_DEVICE_CONTROL << | |
618 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
619 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
620 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
621 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
622 | ||
623 | dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac + | |
624 | reg_offset); | |
625 | ||
626 | err = gxio_trio_set_mps_mrs(trio_context, | |
627 | dev_control.max_payload_size, | |
628 | dev_control.max_read_req_sz, | |
629 | mac); | |
eafa5c8a | 630 | if (err < 0) { |
12962267 CM |
631 | pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, " |
632 | "MAC %d on TRIO %d\n", | |
633 | mac, controller->trio_index); | |
634 | } | |
635 | } | |
636 | ||
b881bc46 | 637 | static int setup_pcie_rc_delay(char *str) |
12962267 CM |
638 | { |
639 | unsigned long delay = 0; | |
640 | unsigned long trio_index; | |
641 | unsigned long mac; | |
642 | ||
643 | if (str == NULL || !isdigit(*str)) | |
644 | return -EINVAL; | |
645 | trio_index = simple_strtoul(str, (char **)&str, 10); | |
646 | if (trio_index >= TILEGX_NUM_TRIO) | |
647 | return -EINVAL; | |
648 | ||
649 | if (*str != ',') | |
650 | return -EINVAL; | |
651 | ||
652 | str++; | |
653 | if (!isdigit(*str)) | |
654 | return -EINVAL; | |
655 | mac = simple_strtoul(str, (char **)&str, 10); | |
656 | if (mac >= TILEGX_TRIO_PCIES) | |
657 | return -EINVAL; | |
658 | ||
659 | if (*str != '\0') { | |
660 | if (*str != ',') | |
661 | return -EINVAL; | |
662 | ||
663 | str++; | |
664 | if (!isdigit(*str)) | |
665 | return -EINVAL; | |
666 | delay = simple_strtoul(str, (char **)&str, 10); | |
12962267 CM |
667 | } |
668 | ||
669 | rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY; | |
12962267 CM |
670 | return 0; |
671 | } | |
672 | early_param("pcie_rc_delay", setup_pcie_rc_delay); | |
673 | ||
eafa5c8a | 674 | /* PCI initialization entry point, called by subsys_initcall. */ |
12962267 CM |
675 | int __init pcibios_init(void) |
676 | { | |
677 | resource_size_t offset; | |
678 | LIST_HEAD(resources); | |
f6d2ce00 | 679 | int next_busno; |
12962267 CM |
680 | int i; |
681 | ||
41bb38fc CM |
682 | tile_pci_init(); |
683 | ||
1c43649a | 684 | if (num_rc_controllers == 0) |
12962267 CM |
685 | return 0; |
686 | ||
12962267 CM |
687 | /* |
688 | * Delay a bit in case devices aren't ready. Some devices are | |
689 | * known to require at least 20ms here, but we use a more | |
690 | * conservative value. | |
691 | */ | |
692 | msleep(250); | |
693 | ||
694 | /* Scan all of the recorded PCI controllers. */ | |
f6d2ce00 | 695 | for (next_busno = 0, i = 0; i < num_rc_controllers; i++) { |
12962267 CM |
696 | struct pci_controller *controller = &pci_controllers[i]; |
697 | gxio_trio_context_t *trio_context = controller->trio; | |
12962267 CM |
698 | TRIO_PCIE_INTFC_PORT_STATUS_t port_status; |
699 | TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl; | |
700 | struct pci_bus *bus; | |
701 | unsigned int reg_offset; | |
702 | unsigned int class_code_revision; | |
703 | int trio_index; | |
704 | int mac; | |
12962267 | 705 | int ret; |
12962267 CM |
706 | |
707 | if (trio_context->fd < 0) | |
708 | continue; | |
709 | ||
710 | trio_index = controller->trio_index; | |
711 | mac = controller->mac; | |
712 | ||
26cde05a CM |
713 | /* |
714 | * Check for PCIe link-up status to decide if we need | |
715 | * to force the link to come up. | |
716 | */ | |
717 | reg_offset = | |
718 | (TRIO_PCIE_INTFC_PORT_STATUS << | |
719 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
720 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
721 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT) | | |
722 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
723 | ||
724 | port_status.word = | |
725 | __gxio_mmio_read(trio_context->mmio_base_mac + | |
726 | reg_offset); | |
727 | if (!port_status.dl_up) { | |
728 | if (rc_delay[trio_index][mac]) { | |
729 | pr_info("Delaying PCIe RC TRIO init %d sec" | |
730 | " on MAC %d on TRIO %d\n", | |
731 | rc_delay[trio_index][mac], mac, | |
732 | trio_index); | |
733 | msleep(rc_delay[trio_index][mac] * 1000); | |
734 | } | |
735 | ret = gxio_trio_force_rc_link_up(trio_context, mac); | |
736 | if (ret < 0) | |
737 | pr_err("PCI: PCIE_FORCE_LINK_UP failure, " | |
738 | "MAC %d on TRIO %d\n", mac, trio_index); | |
739 | } | |
12962267 CM |
740 | |
741 | pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i, | |
742 | trio_index, controller->mac); | |
743 | ||
eafa5c8a | 744 | /* Delay the bus probe if needed. */ |
b3ad73a3 CM |
745 | if (rc_delay[trio_index][mac]) { |
746 | pr_info("Delaying PCIe RC bus enumerating %d sec" | |
747 | " on MAC %d on TRIO %d\n", | |
748 | rc_delay[trio_index][mac], mac, | |
749 | trio_index); | |
750 | msleep(rc_delay[trio_index][mac] * 1000); | |
751 | } else { | |
752 | /* | |
753 | * Wait a bit here because some EP devices | |
754 | * take longer to come up. | |
755 | */ | |
756 | msleep(1000); | |
757 | } | |
12962267 | 758 | |
eafa5c8a | 759 | /* Check for PCIe link-up status again. */ |
12962267 CM |
760 | port_status.word = |
761 | __gxio_mmio_read(trio_context->mmio_base_mac + | |
762 | reg_offset); | |
763 | if (!port_status.dl_up) { | |
8d9e53b9 | 764 | if (pcie_ports[trio_index].ports[mac].removable) { |
a3c4f2fb CM |
765 | pr_info("PCI: link is down, MAC %d on TRIO %d\n", |
766 | mac, trio_index); | |
767 | pr_info("This is expected if no PCIe card" | |
768 | " is connected to this link\n"); | |
769 | } else | |
770 | pr_err("PCI: link is down, MAC %d on TRIO %d\n", | |
771 | mac, trio_index); | |
12962267 CM |
772 | continue; |
773 | } | |
774 | ||
775 | /* | |
776 | * Ensure that the link can come out of L1 power down state. | |
777 | * Strictly speaking, this is needed only in the case of | |
778 | * heavy RC-initiated DMAs. | |
779 | */ | |
780 | reg_offset = | |
781 | (TRIO_PCIE_INTFC_TX_FIFO_CTL << | |
782 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
783 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
784 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
785 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
786 | tx_fifo_ctl.word = | |
787 | __gxio_mmio_read(trio_context->mmio_base_mac + | |
788 | reg_offset); | |
789 | tx_fifo_ctl.min_p_credits = 0; | |
790 | __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, | |
791 | tx_fifo_ctl.word); | |
792 | ||
793 | /* | |
794 | * Change the device ID so that Linux bus crawl doesn't confuse | |
795 | * the internal bridge with any Tilera endpoints. | |
796 | */ | |
12962267 CM |
797 | reg_offset = |
798 | (TRIO_PCIE_RC_DEVICE_ID_VEN_ID << | |
799 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
800 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
801 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
802 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
803 | ||
804 | __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, | |
805 | (TILERA_GX36_RC_DEV_ID << | |
806 | TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) | | |
807 | TILERA_VENDOR_ID); | |
808 | ||
eafa5c8a | 809 | /* Set the internal P2P bridge class code. */ |
12962267 CM |
810 | reg_offset = |
811 | (TRIO_PCIE_RC_REVISION_ID << | |
812 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
813 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
814 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
815 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
816 | ||
817 | class_code_revision = | |
818 | __gxio_mmio_read32(trio_context->mmio_base_mac + | |
819 | reg_offset); | |
eafa5c8a CM |
820 | class_code_revision = (class_code_revision & 0xff) | |
821 | (PCI_CLASS_BRIDGE_PCI << 16); | |
12962267 CM |
822 | |
823 | __gxio_mmio_write32(trio_context->mmio_base_mac + | |
824 | reg_offset, class_code_revision); | |
825 | ||
826 | #ifdef USE_SHARED_PCIE_CONFIG_REGION | |
827 | ||
eafa5c8a | 828 | /* Map in the MMIO space for the PIO region. */ |
12962267 CM |
829 | offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) | |
830 | (((unsigned long long)mac) << | |
831 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT); | |
832 | ||
833 | #else | |
834 | ||
eafa5c8a | 835 | /* Alloc a PIO region for PCI config access per MAC. */ |
12962267 CM |
836 | ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); |
837 | if (ret < 0) { | |
838 | pr_err("PCI: PCI CFG PIO alloc failure for mac %d " | |
839 | "on TRIO %d, give up\n", mac, trio_index); | |
840 | ||
12962267 CM |
841 | continue; |
842 | } | |
843 | ||
844 | trio_context->pio_cfg_index[mac] = ret; | |
845 | ||
eafa5c8a | 846 | /* For PIO CFG, the bus_address_hi parameter is 0. */ |
12962267 CM |
847 | ret = gxio_trio_init_pio_region_aux(trio_context, |
848 | trio_context->pio_cfg_index[mac], | |
849 | mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE); | |
850 | if (ret < 0) { | |
851 | pr_err("PCI: PCI CFG PIO init failure for mac %d " | |
852 | "on TRIO %d, give up\n", mac, trio_index); | |
853 | ||
12962267 CM |
854 | continue; |
855 | } | |
856 | ||
857 | offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) | | |
858 | (((unsigned long long)mac) << | |
859 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT); | |
860 | ||
861 | #endif | |
862 | ||
863 | trio_context->mmio_base_pio_cfg[mac] = | |
864 | iorpc_ioremap(trio_context->fd, offset, | |
865 | (1 << TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT)); | |
866 | if (trio_context->mmio_base_pio_cfg[mac] == NULL) { | |
867 | pr_err("PCI: PIO map failure for mac %d on TRIO %d\n", | |
868 | mac, trio_index); | |
869 | ||
12962267 CM |
870 | continue; |
871 | } | |
872 | ||
eafa5c8a | 873 | /* Initialize the PCIe interrupts. */ |
12962267 CM |
874 | if (tile_init_irqs(controller)) { |
875 | pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n", | |
876 | mac, trio_index); | |
877 | ||
878 | continue; | |
879 | } | |
880 | ||
41bb38fc CM |
881 | /* |
882 | * The PCI memory resource is located above the PA space. | |
883 | * The memory range for the PCI root bus should not overlap | |
cf89c426 | 884 | * with the physical RAM. |
41bb38fc | 885 | */ |
f6d2ce00 CM |
886 | pci_add_resource_offset(&resources, &controller->mem_space, |
887 | controller->mem_offset); | |
cf89c426 | 888 | pci_add_resource(&resources, &controller->io_space); |
f6d2ce00 CM |
889 | controller->first_busno = next_busno; |
890 | bus = pci_scan_root_bus(NULL, next_busno, controller->ops, | |
12962267 CM |
891 | controller, &resources); |
892 | controller->root_bus = bus; | |
d41ca6df | 893 | next_busno = bus->busn_res.end + 1; |
12962267 CM |
894 | } |
895 | ||
896 | /* Do machine dependent PCI interrupt routing */ | |
897 | pci_fixup_irqs(pci_common_swizzle, tile_map_irq); | |
898 | ||
899 | /* | |
900 | * This comes from the generic Linux PCI driver. | |
901 | * | |
902 | * It allocates all of the resources (I/O memory, etc) | |
903 | * associated with the devices read in above. | |
904 | */ | |
12962267 CM |
905 | pci_assign_unassigned_resources(); |
906 | ||
907 | /* Record the I/O resources in the PCI controller structure. */ | |
908 | for (i = 0; i < num_rc_controllers; i++) { | |
909 | struct pci_controller *controller = &pci_controllers[i]; | |
910 | gxio_trio_context_t *trio_context = controller->trio; | |
911 | struct pci_bus *root_bus = pci_controllers[i].root_bus; | |
12962267 CM |
912 | int ret; |
913 | int j; | |
914 | ||
915 | /* | |
916 | * Skip controllers that are not properly initialized or | |
917 | * have down links. | |
918 | */ | |
919 | if (root_bus == NULL) | |
920 | continue; | |
921 | ||
922 | /* Configure the max_payload_size values for this domain. */ | |
923 | fixup_read_and_payload_sizes(controller); | |
924 | ||
eafa5c8a | 925 | /* Alloc a PIO region for PCI memory access for each RC port. */ |
12962267 CM |
926 | ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); |
927 | if (ret < 0) { | |
928 | pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, " | |
eafa5c8a CM |
929 | "give up\n", controller->trio_index, |
930 | controller->mac); | |
12962267 | 931 | |
12962267 CM |
932 | continue; |
933 | } | |
934 | ||
935 | controller->pio_mem_index = ret; | |
936 | ||
937 | /* | |
938 | * For PIO MEM, the bus_address_hi parameter is hard-coded 0 | |
939 | * because we always assign 32-bit PCI bus BAR ranges. | |
940 | */ | |
941 | ret = gxio_trio_init_pio_region_aux(trio_context, | |
942 | controller->pio_mem_index, | |
943 | controller->mac, | |
41bb38fc | 944 | 0, |
12962267 CM |
945 | 0); |
946 | if (ret < 0) { | |
947 | pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, " | |
eafa5c8a CM |
948 | "give up\n", controller->trio_index, |
949 | controller->mac); | |
12962267 | 950 | |
12962267 CM |
951 | continue; |
952 | } | |
953 | ||
cf89c426 CM |
954 | #ifdef CONFIG_TILE_PCI_IO |
955 | /* | |
956 | * Alloc a PIO region for PCI I/O space access for each RC port. | |
957 | */ | |
958 | ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); | |
959 | if (ret < 0) { | |
960 | pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, " | |
eafa5c8a CM |
961 | "give up\n", controller->trio_index, |
962 | controller->mac); | |
cf89c426 CM |
963 | |
964 | continue; | |
965 | } | |
966 | ||
967 | controller->pio_io_index = ret; | |
968 | ||
969 | /* | |
970 | * For PIO IO, the bus_address_hi parameter is hard-coded 0 | |
971 | * because PCI I/O address space is 32-bit. | |
972 | */ | |
973 | ret = gxio_trio_init_pio_region_aux(trio_context, | |
974 | controller->pio_io_index, | |
975 | controller->mac, | |
976 | 0, | |
977 | HV_TRIO_PIO_FLAG_IO_SPACE); | |
978 | if (ret < 0) { | |
979 | pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, " | |
eafa5c8a CM |
980 | "give up\n", controller->trio_index, |
981 | controller->mac); | |
cf89c426 CM |
982 | |
983 | continue; | |
984 | } | |
985 | #endif | |
986 | ||
12962267 CM |
987 | /* |
988 | * Configure a Mem-Map region for each memory controller so | |
989 | * that Linux can map all of its PA space to the PCI bus. | |
990 | * Use the IOMMU to handle hash-for-home memory. | |
991 | */ | |
992 | for_each_online_node(j) { | |
993 | unsigned long start_pfn = node_start_pfn[j]; | |
994 | unsigned long end_pfn = node_end_pfn[j]; | |
995 | unsigned long nr_pages = end_pfn - start_pfn; | |
996 | ||
997 | ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0, | |
998 | 0); | |
999 | if (ret < 0) { | |
1000 | pr_err("PCI: Mem-Map alloc failure on TRIO %d " | |
eafa5c8a CM |
1001 | "mac %d for MC %d, give up\n", |
1002 | controller->trio_index, | |
1003 | controller->mac, j); | |
12962267 | 1004 | |
12962267 CM |
1005 | goto alloc_mem_map_failed; |
1006 | } | |
1007 | ||
1008 | controller->mem_maps[j] = ret; | |
1009 | ||
1010 | /* | |
1011 | * Initialize the Mem-Map and the I/O MMU so that all | |
1012 | * the physical memory can be accessed by the endpoint | |
1013 | * devices. The base bus address is set to the base CPA | |
41bb38fc CM |
1014 | * of this memory controller plus an offset (see pci.h). |
1015 | * The region's base VA is set to the base CPA. The | |
12962267 | 1016 | * I/O MMU table essentially translates the CPA to |
41bb38fc CM |
1017 | * the real PA. Implicitly, for node 0, we create |
1018 | * a separate Mem-Map region that serves as the inbound | |
1019 | * window for legacy 32-bit devices. This is a direct | |
1020 | * map of the low 4GB CPA space. | |
12962267 CM |
1021 | */ |
1022 | ret = gxio_trio_init_memory_map_mmu_aux(trio_context, | |
1023 | controller->mem_maps[j], | |
1024 | start_pfn << PAGE_SHIFT, | |
1025 | nr_pages << PAGE_SHIFT, | |
1026 | trio_context->asid, | |
1027 | controller->mac, | |
41bb38fc CM |
1028 | (start_pfn << PAGE_SHIFT) + |
1029 | TILE_PCI_MEM_MAP_BASE_OFFSET, | |
12962267 CM |
1030 | j, |
1031 | GXIO_TRIO_ORDER_MODE_UNORDERED); | |
1032 | if (ret < 0) { | |
1033 | pr_err("PCI: Mem-Map init failure on TRIO %d " | |
eafa5c8a CM |
1034 | "mac %d for MC %d, give up\n", |
1035 | controller->trio_index, | |
1036 | controller->mac, j); | |
12962267 | 1037 | |
12962267 CM |
1038 | goto alloc_mem_map_failed; |
1039 | } | |
12962267 CM |
1040 | continue; |
1041 | ||
1042 | alloc_mem_map_failed: | |
1043 | break; | |
1044 | } | |
12962267 CM |
1045 | } |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | subsys_initcall(pcibios_init); | |
1050 | ||
eafa5c8a | 1051 | /* No bus fixups needed. */ |
b881bc46 | 1052 | void pcibios_fixup_bus(struct pci_bus *bus) |
12962267 | 1053 | { |
12962267 CM |
1054 | } |
1055 | ||
eafa5c8a | 1056 | /* Process any "pci=" kernel boot arguments. */ |
b881bc46 | 1057 | char *pcibios_setup(char *str) |
12962267 CM |
1058 | { |
1059 | if (!strcmp(str, "off")) { | |
1060 | pci_probe = 0; | |
1061 | return NULL; | |
1062 | } | |
1063 | return str; | |
1064 | } | |
1065 | ||
12962267 CM |
1066 | /* |
1067 | * Enable memory address decoding, as appropriate, for the | |
cf89c426 | 1068 | * device described by the 'dev' struct. |
12962267 CM |
1069 | * |
1070 | * This is called from the generic PCI layer, and can be called | |
1071 | * for bridges or endpoints. | |
1072 | */ | |
1073 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1074 | { | |
1075 | return pci_enable_resources(dev, mask); | |
1076 | } | |
1077 | ||
41bb38fc | 1078 | /* Called for each device after PCI setup is done. */ |
5955a596 | 1079 | static void pcibios_fixup_final(struct pci_dev *pdev) |
41bb38fc CM |
1080 | { |
1081 | set_dma_ops(&pdev->dev, gx_pci_dma_map_ops); | |
1082 | set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET); | |
1083 | pdev->dev.archdata.max_direct_dma_addr = | |
1084 | TILE_PCI_MAX_DIRECT_DMA_ADDRESS; | |
1085 | } | |
1086 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final); | |
1087 | ||
12962267 CM |
1088 | /* Map a PCI MMIO bus address into VA space. */ |
1089 | void __iomem *ioremap(resource_size_t phys_addr, unsigned long size) | |
1090 | { | |
1091 | struct pci_controller *controller = NULL; | |
1092 | resource_size_t bar_start; | |
1093 | resource_size_t bar_end; | |
1094 | resource_size_t offset; | |
1095 | resource_size_t start; | |
1096 | resource_size_t end; | |
1097 | int trio_fd; | |
11981687 | 1098 | int i; |
12962267 CM |
1099 | |
1100 | start = phys_addr; | |
1101 | end = phys_addr + size - 1; | |
1102 | ||
1103 | /* | |
11981687 | 1104 | * By searching phys_addr in each controller's mem_space, we can |
12962267 CM |
1105 | * determine the controller that should accept the PCI memory access. |
1106 | */ | |
12962267 CM |
1107 | for (i = 0; i < num_rc_controllers; i++) { |
1108 | /* | |
1109 | * Skip controllers that are not properly initialized or | |
1110 | * have down links. | |
1111 | */ | |
1112 | if (pci_controllers[i].root_bus == NULL) | |
1113 | continue; | |
1114 | ||
11981687 CM |
1115 | bar_start = pci_controllers[i].mem_space.start; |
1116 | bar_end = pci_controllers[i].mem_space.end; | |
12962267 | 1117 | |
11981687 CM |
1118 | if ((start >= bar_start) && (end <= bar_end)) { |
1119 | controller = &pci_controllers[i]; | |
1120 | break; | |
12962267 CM |
1121 | } |
1122 | } | |
1123 | ||
1124 | if (controller == NULL) | |
1125 | return NULL; | |
1126 | ||
12962267 CM |
1127 | trio_fd = controller->trio->fd; |
1128 | ||
f6d2ce00 CM |
1129 | /* Convert the resource start to the bus address offset. */ |
1130 | start = phys_addr - controller->mem_offset; | |
1131 | ||
1132 | offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start; | |
12962267 | 1133 | |
eafa5c8a | 1134 | /* We need to keep the PCI bus address's in-page offset in the VA. */ |
12962267 | 1135 | return iorpc_ioremap(trio_fd, offset, size) + |
cf89c426 | 1136 | (start & (PAGE_SIZE - 1)); |
12962267 CM |
1137 | } |
1138 | EXPORT_SYMBOL(ioremap); | |
1139 | ||
cf89c426 CM |
1140 | #ifdef CONFIG_TILE_PCI_IO |
1141 | /* Map a PCI I/O address into VA space. */ | |
1142 | void __iomem *ioport_map(unsigned long port, unsigned int size) | |
1143 | { | |
1144 | struct pci_controller *controller = NULL; | |
1145 | resource_size_t bar_start; | |
1146 | resource_size_t bar_end; | |
1147 | resource_size_t offset; | |
1148 | resource_size_t start; | |
1149 | resource_size_t end; | |
1150 | int trio_fd; | |
1151 | int i; | |
1152 | ||
1153 | start = port; | |
1154 | end = port + size - 1; | |
1155 | ||
1156 | /* | |
11981687 CM |
1157 | * By searching the port in each controller's io_space, we can |
1158 | * determine the controller that should accept the PCI I/O access. | |
cf89c426 | 1159 | */ |
cf89c426 CM |
1160 | for (i = 0; i < num_rc_controllers; i++) { |
1161 | /* | |
1162 | * Skip controllers that are not properly initialized or | |
1163 | * have down links. | |
1164 | */ | |
1165 | if (pci_controllers[i].root_bus == NULL) | |
1166 | continue; | |
1167 | ||
11981687 CM |
1168 | bar_start = pci_controllers[i].io_space.start; |
1169 | bar_end = pci_controllers[i].io_space.end; | |
cf89c426 CM |
1170 | |
1171 | if ((start >= bar_start) && (end <= bar_end)) { | |
cf89c426 | 1172 | controller = &pci_controllers[i]; |
11981687 | 1173 | break; |
cf89c426 CM |
1174 | } |
1175 | } | |
1176 | ||
1177 | if (controller == NULL) | |
1178 | return NULL; | |
1179 | ||
cf89c426 CM |
1180 | trio_fd = controller->trio->fd; |
1181 | ||
1182 | /* Convert the resource start to the bus address offset. */ | |
1183 | port -= controller->io_space.start; | |
1184 | ||
1185 | offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port; | |
1186 | ||
eafa5c8a | 1187 | /* We need to keep the PCI bus address's in-page offset in the VA. */ |
cf89c426 CM |
1188 | return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1)); |
1189 | } | |
1190 | EXPORT_SYMBOL(ioport_map); | |
1191 | ||
1192 | void ioport_unmap(void __iomem *addr) | |
1193 | { | |
1194 | iounmap(addr); | |
1195 | } | |
1196 | EXPORT_SYMBOL(ioport_unmap); | |
1197 | #endif | |
1198 | ||
12962267 CM |
1199 | void pci_iounmap(struct pci_dev *dev, void __iomem *addr) |
1200 | { | |
1201 | iounmap(addr); | |
1202 | } | |
1203 | EXPORT_SYMBOL(pci_iounmap); | |
1204 | ||
1205 | /**************************************************************** | |
1206 | * | |
1207 | * Tile PCI config space read/write routines | |
1208 | * | |
1209 | ****************************************************************/ | |
1210 | ||
1211 | /* | |
1212 | * These are the normal read and write ops | |
1213 | * These are expanded with macros from pci_bus_read_config_byte() etc. | |
1214 | * | |
1215 | * devfn is the combined PCI device & function. | |
1216 | * | |
1217 | * offset is in bytes, from the start of config space for the | |
1218 | * specified bus & device. | |
1219 | */ | |
b881bc46 GKH |
1220 | static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset, |
1221 | int size, u32 *val) | |
12962267 CM |
1222 | { |
1223 | struct pci_controller *controller = bus->sysdata; | |
1224 | gxio_trio_context_t *trio_context = controller->trio; | |
1225 | int busnum = bus->number & 0xff; | |
1226 | int device = PCI_SLOT(devfn); | |
1227 | int function = PCI_FUNC(devfn); | |
1228 | int config_type = 1; | |
1229 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr; | |
1230 | void *mmio_addr; | |
1231 | ||
1232 | /* | |
f6d2ce00 | 1233 | * Map all accesses to the local device on root bus into the |
12962267 CM |
1234 | * MMIO space of the MAC. Accesses to the downstream devices |
1235 | * go to the PIO space. | |
1236 | */ | |
f6d2ce00 | 1237 | if (pci_is_root_bus(bus)) { |
12962267 CM |
1238 | if (device == 0) { |
1239 | /* | |
1240 | * This is the internal downstream P2P bridge, | |
1241 | * access directly. | |
1242 | */ | |
1243 | unsigned int reg_offset; | |
1244 | ||
1245 | reg_offset = ((offset & 0xFFF) << | |
1246 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
1247 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED | |
1248 | << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
1249 | (controller->mac << | |
1250 | TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
1251 | ||
1252 | mmio_addr = trio_context->mmio_base_mac + reg_offset; | |
1253 | ||
1254 | goto valid_device; | |
1255 | ||
1256 | } else { | |
1257 | /* | |
1258 | * We fake an empty device for (device > 0), | |
1259 | * since there is only one device on bus 0. | |
1260 | */ | |
1261 | goto invalid_device; | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | /* | |
f6d2ce00 | 1266 | * Accesses to the directly attached device have to be |
12962267 CM |
1267 | * sent as type-0 configs. |
1268 | */ | |
f6d2ce00 | 1269 | if (busnum == (controller->first_busno + 1)) { |
12962267 CM |
1270 | /* |
1271 | * There is only one device off of our built-in P2P bridge. | |
1272 | */ | |
1273 | if (device != 0) | |
1274 | goto invalid_device; | |
1275 | ||
1276 | config_type = 0; | |
1277 | } | |
1278 | ||
1279 | cfg_addr.word = 0; | |
1280 | cfg_addr.reg_addr = (offset & 0xFFF); | |
1281 | cfg_addr.fn = function; | |
1282 | cfg_addr.dev = device; | |
1283 | cfg_addr.bus = busnum; | |
1284 | cfg_addr.type = config_type; | |
1285 | ||
1286 | /* | |
1287 | * Note that we don't set the mac field in cfg_addr because the | |
1288 | * mapping is per port. | |
1289 | */ | |
12962267 | 1290 | mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] + |
eafa5c8a | 1291 | cfg_addr.word; |
12962267 CM |
1292 | |
1293 | valid_device: | |
1294 | ||
1295 | switch (size) { | |
1296 | case 4: | |
1297 | *val = __gxio_mmio_read32(mmio_addr); | |
1298 | break; | |
1299 | ||
1300 | case 2: | |
1301 | *val = __gxio_mmio_read16(mmio_addr); | |
1302 | break; | |
1303 | ||
1304 | case 1: | |
1305 | *val = __gxio_mmio_read8(mmio_addr); | |
1306 | break; | |
1307 | ||
1308 | default: | |
1309 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
1310 | } | |
1311 | ||
1312 | TRACE_CFG_RD(size, *val, busnum, device, function, offset); | |
1313 | ||
1314 | return 0; | |
1315 | ||
1316 | invalid_device: | |
1317 | ||
1318 | switch (size) { | |
1319 | case 4: | |
1320 | *val = 0xFFFFFFFF; | |
1321 | break; | |
1322 | ||
1323 | case 2: | |
1324 | *val = 0xFFFF; | |
1325 | break; | |
1326 | ||
1327 | case 1: | |
1328 | *val = 0xFF; | |
1329 | break; | |
1330 | ||
1331 | default: | |
1332 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
1333 | } | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | ||
1339 | /* | |
1340 | * See tile_cfg_read() for relevent comments. | |
1341 | * Note that "val" is the value to write, not a pointer to that value. | |
1342 | */ | |
b881bc46 GKH |
1343 | static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset, |
1344 | int size, u32 val) | |
12962267 CM |
1345 | { |
1346 | struct pci_controller *controller = bus->sysdata; | |
1347 | gxio_trio_context_t *trio_context = controller->trio; | |
1348 | int busnum = bus->number & 0xff; | |
1349 | int device = PCI_SLOT(devfn); | |
1350 | int function = PCI_FUNC(devfn); | |
1351 | int config_type = 1; | |
1352 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr; | |
1353 | void *mmio_addr; | |
1354 | u32 val_32 = (u32)val; | |
1355 | u16 val_16 = (u16)val; | |
1356 | u8 val_8 = (u8)val; | |
1357 | ||
1358 | /* | |
f6d2ce00 | 1359 | * Map all accesses to the local device on root bus into the |
12962267 CM |
1360 | * MMIO space of the MAC. Accesses to the downstream devices |
1361 | * go to the PIO space. | |
1362 | */ | |
f6d2ce00 | 1363 | if (pci_is_root_bus(bus)) { |
12962267 CM |
1364 | if (device == 0) { |
1365 | /* | |
1366 | * This is the internal downstream P2P bridge, | |
1367 | * access directly. | |
1368 | */ | |
1369 | unsigned int reg_offset; | |
1370 | ||
1371 | reg_offset = ((offset & 0xFFF) << | |
1372 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
1373 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED | |
1374 | << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
1375 | (controller->mac << | |
1376 | TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
1377 | ||
1378 | mmio_addr = trio_context->mmio_base_mac + reg_offset; | |
1379 | ||
1380 | goto valid_device; | |
1381 | ||
1382 | } else { | |
1383 | /* | |
1384 | * We fake an empty device for (device > 0), | |
1385 | * since there is only one device on bus 0. | |
1386 | */ | |
1387 | goto invalid_device; | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | /* | |
f6d2ce00 | 1392 | * Accesses to the directly attached device have to be |
12962267 CM |
1393 | * sent as type-0 configs. |
1394 | */ | |
f6d2ce00 | 1395 | if (busnum == (controller->first_busno + 1)) { |
12962267 CM |
1396 | /* |
1397 | * There is only one device off of our built-in P2P bridge. | |
1398 | */ | |
1399 | if (device != 0) | |
1400 | goto invalid_device; | |
1401 | ||
1402 | config_type = 0; | |
1403 | } | |
1404 | ||
1405 | cfg_addr.word = 0; | |
1406 | cfg_addr.reg_addr = (offset & 0xFFF); | |
1407 | cfg_addr.fn = function; | |
1408 | cfg_addr.dev = device; | |
1409 | cfg_addr.bus = busnum; | |
1410 | cfg_addr.type = config_type; | |
1411 | ||
1412 | /* | |
1413 | * Note that we don't set the mac field in cfg_addr because the | |
1414 | * mapping is per port. | |
1415 | */ | |
12962267 CM |
1416 | mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] + |
1417 | cfg_addr.word; | |
1418 | ||
1419 | valid_device: | |
1420 | ||
1421 | switch (size) { | |
1422 | case 4: | |
1423 | __gxio_mmio_write32(mmio_addr, val_32); | |
1424 | TRACE_CFG_WR(size, val_32, busnum, device, function, offset); | |
1425 | break; | |
1426 | ||
1427 | case 2: | |
1428 | __gxio_mmio_write16(mmio_addr, val_16); | |
1429 | TRACE_CFG_WR(size, val_16, busnum, device, function, offset); | |
1430 | break; | |
1431 | ||
1432 | case 1: | |
1433 | __gxio_mmio_write8(mmio_addr, val_8); | |
1434 | TRACE_CFG_WR(size, val_8, busnum, device, function, offset); | |
1435 | break; | |
1436 | ||
1437 | default: | |
1438 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
1439 | } | |
1440 | ||
1441 | invalid_device: | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | ||
1447 | static struct pci_ops tile_cfg_ops = { | |
1448 | .read = tile_cfg_read, | |
1449 | .write = tile_cfg_write, | |
1450 | }; | |
1451 | ||
1452 | ||
eafa5c8a CM |
1453 | /* MSI support starts here. */ |
1454 | static unsigned int tilegx_msi_startup(struct irq_data *d) | |
12962267 CM |
1455 | { |
1456 | if (d->msi_desc) | |
1457 | unmask_msi_irq(d); | |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | ||
eafa5c8a | 1462 | static void tilegx_msi_ack(struct irq_data *d) |
12962267 CM |
1463 | { |
1464 | __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq); | |
1465 | } | |
1466 | ||
eafa5c8a | 1467 | static void tilegx_msi_mask(struct irq_data *d) |
12962267 CM |
1468 | { |
1469 | mask_msi_irq(d); | |
1470 | __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); | |
1471 | } | |
1472 | ||
eafa5c8a | 1473 | static void tilegx_msi_unmask(struct irq_data *d) |
12962267 CM |
1474 | { |
1475 | __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); | |
1476 | unmask_msi_irq(d); | |
1477 | } | |
1478 | ||
1479 | static struct irq_chip tilegx_msi_chip = { | |
1480 | .name = "tilegx_msi", | |
1481 | .irq_startup = tilegx_msi_startup, | |
1482 | .irq_ack = tilegx_msi_ack, | |
1483 | .irq_mask = tilegx_msi_mask, | |
1484 | .irq_unmask = tilegx_msi_unmask, | |
1485 | ||
1486 | /* TBD: support set_affinity. */ | |
1487 | }; | |
1488 | ||
1489 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1490 | { | |
1491 | struct pci_controller *controller; | |
1492 | gxio_trio_context_t *trio_context; | |
1493 | struct msi_msg msg; | |
1494 | int default_irq; | |
1495 | uint64_t mem_map_base; | |
1496 | uint64_t mem_map_limit; | |
1497 | u64 msi_addr; | |
1498 | int mem_map; | |
1499 | int cpu; | |
1500 | int irq; | |
1501 | int ret; | |
1502 | ||
1503 | irq = create_irq(); | |
1504 | if (irq < 0) | |
1505 | return irq; | |
1506 | ||
1507 | /* | |
1508 | * Since we use a 64-bit Mem-Map to accept the MSI write, we fail | |
1509 | * devices that are not capable of generating a 64-bit message address. | |
1510 | * These devices will fall back to using the legacy interrupts. | |
1511 | * Most PCIe endpoint devices do support 64-bit message addressing. | |
1512 | */ | |
1513 | if (desc->msi_attrib.is_64 == 0) { | |
1514 | dev_printk(KERN_INFO, &pdev->dev, | |
1515 | "64-bit MSI message address not supported, " | |
1516 | "falling back to legacy interrupts.\n"); | |
1517 | ||
1518 | ret = -ENOMEM; | |
1519 | goto is_64_failure; | |
1520 | } | |
1521 | ||
1522 | default_irq = desc->msi_attrib.default_irq; | |
1523 | controller = irq_get_handler_data(default_irq); | |
1524 | ||
1525 | BUG_ON(!controller); | |
1526 | ||
1527 | trio_context = controller->trio; | |
1528 | ||
1529 | /* | |
90d9dd66 CM |
1530 | * Allocate a scatter-queue that will accept the MSI write and |
1531 | * trigger the TILE-side interrupts. We use the scatter-queue regions | |
1532 | * before the mem map regions, because the latter are needed by more | |
1533 | * applications. | |
12962267 | 1534 | */ |
90d9dd66 CM |
1535 | mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0); |
1536 | if (mem_map >= 0) { | |
1537 | TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{ | |
1538 | .pop = 0, | |
1539 | .doorbell = 1, | |
1540 | }}; | |
1541 | ||
1542 | mem_map += TRIO_NUM_MAP_MEM_REGIONS; | |
1543 | mem_map_base = MEM_MAP_INTR_REGIONS_BASE + | |
1544 | mem_map * MEM_MAP_INTR_REGION_SIZE; | |
1545 | mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1; | |
1546 | ||
1547 | msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8; | |
1548 | msg.data = (unsigned int)doorbell_template.word; | |
1549 | } else { | |
1550 | /* SQ regions are out, allocate from map mem regions. */ | |
1551 | mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0); | |
1552 | if (mem_map < 0) { | |
1553 | dev_printk(KERN_INFO, &pdev->dev, | |
1554 | "%s Mem-Map alloc failure. " | |
1555 | "Failed to initialize MSI interrupts. " | |
1556 | "Falling back to legacy interrupts.\n", | |
1557 | desc->msi_attrib.is_msix ? "MSI-X" : "MSI"); | |
1558 | ret = -ENOMEM; | |
1559 | goto msi_mem_map_alloc_failure; | |
1560 | } | |
12962267 | 1561 | |
90d9dd66 CM |
1562 | mem_map_base = MEM_MAP_INTR_REGIONS_BASE + |
1563 | mem_map * MEM_MAP_INTR_REGION_SIZE; | |
1564 | mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1; | |
1565 | ||
1566 | msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 - | |
1567 | TRIO_MAP_MEM_REG_INT0; | |
1568 | ||
1569 | msg.data = mem_map; | |
12962267 CM |
1570 | } |
1571 | ||
1572 | /* We try to distribute different IRQs to different tiles. */ | |
1573 | cpu = tile_irq_cpu(irq); | |
1574 | ||
1575 | /* | |
90d9dd66 | 1576 | * Now call up to the HV to configure the MSI interrupt and |
12962267 CM |
1577 | * set up the IPI binding. |
1578 | */ | |
12962267 CM |
1579 | ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu), |
1580 | KERNEL_PL, irq, controller->mac, | |
1581 | mem_map, mem_map_base, mem_map_limit, | |
1582 | trio_context->asid); | |
1583 | if (ret < 0) { | |
1584 | dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n"); | |
1585 | ||
1586 | goto hv_msi_config_failure; | |
1587 | } | |
1588 | ||
1589 | irq_set_msi_desc(irq, desc); | |
1590 | ||
12962267 CM |
1591 | msg.address_hi = msi_addr >> 32; |
1592 | msg.address_lo = msi_addr & 0xffffffff; | |
1593 | ||
12962267 CM |
1594 | write_msi_msg(irq, &msg); |
1595 | irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq); | |
1596 | irq_set_handler_data(irq, controller); | |
1597 | ||
1598 | return 0; | |
1599 | ||
1600 | hv_msi_config_failure: | |
1601 | /* Free mem-map */ | |
1602 | msi_mem_map_alloc_failure: | |
1603 | is_64_failure: | |
1604 | destroy_irq(irq); | |
1605 | return ret; | |
1606 | } | |
1607 | ||
1608 | void arch_teardown_msi_irq(unsigned int irq) | |
1609 | { | |
1610 | destroy_irq(irq); | |
1611 | } |