[deliverable/linux.git] / arch / x86 / events / intel / uncore.h

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <asm/apicdef.h>

#include <linux/perf_event.h>
#include "../perf_event.h"

#define UNCORE_PMU_NAME_LEN		32
#define UNCORE_PMU_HRTIMER_INTERVAL	(60LL * NSEC_PER_SEC)
#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)

#define UNCORE_FIXED_EVENT		0xff
#define UNCORE_PMC_IDX_MAX_GENERIC	8
#define UNCORE_PMC_IDX_FIXED		UNCORE_PMC_IDX_MAX_GENERIC
#define UNCORE_PMC_IDX_MAX		(UNCORE_PMC_IDX_FIXED + 1)

#define UNCORE_PCI_DEV_DATA(type, idx)	((type << 8) | idx)
#define UNCORE_PCI_DEV_TYPE(data)	((data >> 8) & 0xff)
#define UNCORE_PCI_DEV_IDX(data)	(data & 0xff)
#define UNCORE_EXTRA_PCI_DEV		0xff
#define UNCORE_EXTRA_PCI_DEV_MAX	3

#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)

struct pci_extra_dev {
	struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
};

struct intel_uncore_ops;
struct intel_uncore_pmu;
struct intel_uncore_box;
struct uncore_event_desc;

struct intel_uncore_type {
	const char *name;
	int num_counters;
	int num_boxes;
	int perf_ctr_bits;
	int fixed_ctr_bits;
	unsigned perf_ctr;
	unsigned event_ctl;
	unsigned event_mask;
	unsigned fixed_ctr;
	unsigned fixed_ctl;
	unsigned box_ctl;
	unsigned msr_offset;
	unsigned num_shared_regs:8;
	unsigned single_fixed:1;
	unsigned pair_ctr_ctl:1;
	unsigned *msr_offsets;
	struct event_constraint unconstrainted;
	struct event_constraint *constraints;
	struct intel_uncore_pmu *pmus;
	struct intel_uncore_ops *ops;
	struct uncore_event_desc *event_descs;
	const struct attribute_group *attr_groups[4];
	struct pmu *pmu; /* for custom pmu ops */
};

#define pmu_group attr_groups[0]
#define format_group attr_groups[1]
#define events_group attr_groups[2]

struct intel_uncore_ops {
	void (*init_box)(struct intel_uncore_box *);
	void (*exit_box)(struct intel_uncore_box *);
	void (*disable_box)(struct intel_uncore_box *);
	void (*enable_box)(struct intel_uncore_box *);
	void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
	void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
	u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
	int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
	struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
						   struct perf_event *);
	void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
};

struct intel_uncore_pmu {
	struct pmu			pmu;
	char				name[UNCORE_PMU_NAME_LEN];
	int				pmu_idx;
	int				func_id;
	bool				registered;
	atomic_t			activeboxes;
	struct intel_uncore_type	*type;
	struct intel_uncore_box		**boxes;
};

struct intel_uncore_extra_reg {
	raw_spinlock_t lock;
	u64 config, config1, config2;
	atomic_t ref;
};

struct intel_uncore_box {
	int pci_phys_id;
	int pkgid;
	int n_active;	/* number of active events */
	int n_events;
	int cpu;	/* cpu to collect events */
	unsigned long flags;
	atomic_t refcnt;
	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
	u64 tags[UNCORE_PMC_IDX_MAX];
	struct pci_dev *pci_dev;
	struct intel_uncore_pmu *pmu;
	u64 hrtimer_duration; /* hrtimer timeout for this box */
	struct hrtimer hrtimer;
	struct list_head list;
	struct list_head active_list;
	void *io_addr;
	struct intel_uncore_extra_reg shared_regs[0];
};

#define UNCORE_BOX_FLAG_INITIATED	0

struct uncore_event_desc {
	struct kobj_attribute attr;
	const char *config;
};

struct pci2phy_map {
	struct list_head list;
	int segment;
	int pbus_to_physid[256];
};

struct pci2phy_map *__find_pci2phy_map(int segment);

ssize_t uncore_event_show(struct kobject *kobj,
			  struct kobj_attribute *attr, char *buf);

#define INTEL_UNCORE_EVENT_DESC(_name, _config)			\
{								\
	.attr	= __ATTR(_name, 0444, uncore_event_show, NULL),	\
	.config	= _config,					\
}

#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)			\
static ssize_t __uncore_##_var##_show(struct kobject *kobj,		\
				struct kobj_attribute *attr,		\
				char *page)				\
{									\
	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);			\
	return sprintf(page, _format "\n");				\
}									\
static struct kobj_attribute format_attr_##_var =			\
	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)

static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->box_ctl;
}

static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctl;
}

static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr;
}

static inline
unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
{
	return idx * 4 + box->pmu->type->event_ctl;
}

static inline
unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return idx * 8 + box->pmu->type->perf_ctr;
}

static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
{
	struct intel_uncore_pmu *pmu = box->pmu;
	return pmu->type->msr_offsets ?
		pmu->type->msr_offsets[pmu->pmu_idx] :
		pmu->type->msr_offset * pmu->pmu_idx;
}

static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->box_ctl)
		return 0;
	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->fixed_ctl)
		return 0;
	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->event_ctl +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->perf_ctr +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctl(box);
	else
		return uncore_msr_fixed_ctl(box);
}

static inline
unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctr(box);
	else
		return uncore_msr_fixed_ctr(box);
}

static inline
unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_event_ctl(box, idx);
	else
		return uncore_msr_event_ctl(box, idx);
}

static inline
unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_perf_ctr(box, idx);
	else
		return uncore_msr_perf_ctr(box, idx);
}

static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->perf_ctr_bits;
}

static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr_bits;
}

static inline int uncore_num_counters(struct intel_uncore_box *box)
{
	return box->pmu->type->num_counters;
}

static inline void uncore_disable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->disable_box)
		box->pmu->type->ops->disable_box(box);
}

static inline void uncore_enable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->enable_box)
		box->pmu->type->ops->enable_box(box);
}

static inline void uncore_disable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->disable_event(box, event);
}

static inline void uncore_enable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->enable_event(box, event);
}

static inline u64 uncore_read_counter(struct intel_uncore_box *box,
				struct perf_event *event)
{
	return box->pmu->type->ops->read_counter(box, event);
}

static inline void uncore_box_init(struct intel_uncore_box *box)
{
	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->init_box)
			box->pmu->type->ops->init_box(box);
	}
}

static inline void uncore_box_exit(struct intel_uncore_box *box)
{
	if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->exit_box)
			box->pmu->type->ops->exit_box(box);
	}
}

static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
{
	return (box->pkgid < 0);
}

static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
{
	return container_of(event->pmu, struct intel_uncore_pmu, pmu);
}

static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
{
	return event->pmu_private;
}

struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_event_read(struct perf_event *event);
void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
struct event_constraint *
uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);

extern struct intel_uncore_type **uncore_msr_uncores;
extern struct intel_uncore_type **uncore_pci_uncores;
extern struct pci_driver *uncore_pci_driver;
extern raw_spinlock_t pci2phy_map_lock;
extern struct list_head pci2phy_map_head;
extern struct pci_extra_dev *uncore_extra_pci_dev;
extern struct event_constraint uncore_constraint_empty;

/* perf_event_intel_uncore_snb.c */
int snb_uncore_pci_init(void);
int ivb_uncore_pci_init(void);
int hsw_uncore_pci_init(void);
int bdw_uncore_pci_init(void);
int skl_uncore_pci_init(void);
void snb_uncore_cpu_init(void);
void nhm_uncore_cpu_init(void);
int snb_pci2phy_map_init(int devid);

/* perf_event_intel_uncore_snbep.c */
int snbep_uncore_pci_init(void);
void snbep_uncore_cpu_init(void);
int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);
int bdx_uncore_pci_init(void);
void bdx_uncore_cpu_init(void);
int knl_uncore_pci_init(void);
void knl_uncore_cpu_init(void);

/* perf_event_intel_uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
Commit	Line	Data
087bfbb0 YZ	1	#include <linux/module.h>
087bfbb0 YZ	2	#include <linux/slab.h>
14371cce	3	#include <linux/pci.h>
6f6e1516 IM	4	#include <asm/apicdef.h>
6f6e1516 IM	5
087bfbb0	6	#include <linux/perf_event.h>
27f6d22b	7	#include "../perf_event.h"
087bfbb0 YZ	8
087bfbb0 YZ	9	#define UNCORE_PMU_NAME_LEN 32
7740dfc0	10	#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
ced2efb0	11	#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
087bfbb0	12
eca26c99	13	#define UNCORE_FIXED_EVENT 0xff
087bfbb0 YZ	14	#define UNCORE_PMC_IDX_MAX_GENERIC 8
	15	#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
	16	#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
	17
899396cf YZ	18	#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) \| idx)
	19	#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
	20	#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
	21	#define UNCORE_EXTRA_PCI_DEV 0xff
5306c31c	22	#define UNCORE_EXTRA_PCI_DEV_MAX 3
899396cf	23
087bfbb0 YZ	24	#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
087bfbb0 YZ	25
cf6d445f TG	26	struct pci_extra_dev {
	27	struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
	28	};
	29
087bfbb0 YZ	30	struct intel_uncore_ops;
	31	struct intel_uncore_pmu;
	32	struct intel_uncore_box;
	33	struct uncore_event_desc;
	34
	35	struct intel_uncore_type {
	36	const char *name;
	37	int num_counters;
	38	int num_boxes;
	39	int perf_ctr_bits;
	40	int fixed_ctr_bits;
087bfbb0 YZ	41	unsigned perf_ctr;
	42	unsigned event_ctl;
	43	unsigned event_mask;
	44	unsigned fixed_ctr;
	45	unsigned fixed_ctl;
	46	unsigned box_ctl;
	47	unsigned msr_offset;
6a67943a YZ	48	unsigned num_shared_regs:8;
6a67943a YZ	49	unsigned single_fixed:1;
254298c7	50	unsigned pair_ctr_ctl:1;
cb37af77	51	unsigned *msr_offsets;
087bfbb0 YZ	52	struct event_constraint unconstrainted;
	53	struct event_constraint *constraints;
	54	struct intel_uncore_pmu *pmus;
	55	struct intel_uncore_ops *ops;
	56	struct uncore_event_desc *event_descs;
314d9f63	57	const struct attribute_group *attr_groups[4];
d64b25b6	58	struct pmu pmu; / for custom pmu ops */
087bfbb0 YZ	59	};
087bfbb0 YZ	60
314d9f63 YZ	61	#define pmu_group attr_groups[0]
	62	#define format_group attr_groups[1]
	63	#define events_group attr_groups[2]
087bfbb0 YZ	64
	65	struct intel_uncore_ops {
	66	void (init_box)(struct intel_uncore_box );
a46195f1	67	void (exit_box)(struct intel_uncore_box );
087bfbb0 YZ	68	void (disable_box)(struct intel_uncore_box );
	69	void (enable_box)(struct intel_uncore_box );
	70	void (disable_event)(struct intel_uncore_box , struct perf_event *);
	71	void (enable_event)(struct intel_uncore_box , struct perf_event *);
	72	u64 (read_counter)(struct intel_uncore_box , struct perf_event *);
6a67943a YZ	73	int (hw_config)(struct intel_uncore_box , struct perf_event *);
	74	struct event_constraint (get_constraint)(struct intel_uncore_box *,
	75	struct perf_event *);
	76	void (put_constraint)(struct intel_uncore_box , struct perf_event *);
087bfbb0 YZ	77	};
	78
	79	struct intel_uncore_pmu {
4f089678 TG	80	struct pmu pmu;
	81	char name[UNCORE_PMU_NAME_LEN];
	82	int pmu_idx;
	83	int func_id;
	84	bool registered;
cf6d445f	85	atomic_t activeboxes;
4f089678	86	struct intel_uncore_type *type;
cf6d445f	87	struct intel_uncore_box **boxes;
087bfbb0 YZ	88	};
087bfbb0 YZ	89
6a67943a YZ	90	struct intel_uncore_extra_reg {
6a67943a YZ	91	raw_spinlock_t lock;
254298c7	92	u64 config, config1, config2;
6a67943a YZ	93	atomic_t ref;
	94	};
	95
087bfbb0	96	struct intel_uncore_box {
cf6d445f TG	97	int pci_phys_id;
cf6d445f TG	98	int pkgid;
087bfbb0 YZ	99	int n_active; /* number of active events */
	100	int n_events;
	101	int cpu; /* cpu to collect events */
	102	unsigned long flags;
	103	atomic_t refcnt;
	104	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	105	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
b371b594	106	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
087bfbb0 YZ	107	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
087bfbb0 YZ	108	u64 tags[UNCORE_PMC_IDX_MAX];
14371cce	109	struct pci_dev *pci_dev;
087bfbb0	110	struct intel_uncore_pmu *pmu;
79859cce	111	u64 hrtimer_duration; /* hrtimer timeout for this box */
087bfbb0 YZ	112	struct hrtimer hrtimer;
087bfbb0 YZ	113	struct list_head list;
ced2efb0	114	struct list_head active_list;
b9e1ab6d	115	void *io_addr;
6a67943a	116	struct intel_uncore_extra_reg shared_regs[0];
087bfbb0 YZ	117	};
	118
	119	#define UNCORE_BOX_FLAG_INITIATED 0
	120
	121	struct uncore_event_desc {
	122	struct kobj_attribute attr;
	123	const char *config;
	124	};
	125
712df65c TI	126	struct pci2phy_map {
	127	struct list_head list;
	128	int segment;
	129	int pbus_to_physid[256];
	130	};
	131
712df65c TI	132	struct pci2phy_map *__find_pci2phy_map(int segment);
712df65c TI	133
514b2346 YZ	134	ssize_t uncore_event_show(struct kobject *kobj,
	135	struct kobj_attribute attr, char buf);
	136
087bfbb0 YZ	137	#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
	138	{ \
	139	.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
	140	.config = _config, \
	141	}
	142
	143	#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
	144	static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
	145	struct kobj_attribute *attr, \
	146	char *page) \
	147	{ \
	148	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
	149	return sprintf(page, _format "\n"); \
	150	} \
	151	static struct kobj_attribute format_attr_##_var = \
	152	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
	153
14371cce YZ	154	static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
	155	{
	156	return box->pmu->type->box_ctl;
	157	}
	158
	159	static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
	160	{
	161	return box->pmu->type->fixed_ctl;
	162	}
	163
	164	static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
	165	{
	166	return box->pmu->type->fixed_ctr;
	167	}
	168
	169	static inline
	170	unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
	171	{
	172	return idx * 4 + box->pmu->type->event_ctl;
	173	}
	174
	175	static inline
	176	unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
	177	{
	178	return idx * 8 + box->pmu->type->perf_ctr;
	179	}
	180
cb37af77 YZ	181	static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
	182	{
	183	struct intel_uncore_pmu *pmu = box->pmu;
	184	return pmu->type->msr_offsets ?
	185	pmu->type->msr_offsets[pmu->pmu_idx] :
	186	pmu->type->msr_offset * pmu->pmu_idx;
	187	}
	188
	189	static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	190	{
	191	if (!box->pmu->type->box_ctl)
	192	return 0;
cb37af77	193	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	194	}
087bfbb0 YZ	195
cb37af77	196	static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	197	{
	198	if (!box->pmu->type->fixed_ctl)
	199	return 0;
cb37af77	200	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	201	}
087bfbb0 YZ	202
cb37af77	203	static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
087bfbb0	204	{
cb37af77	205	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
087bfbb0 YZ	206	}
	207
	208	static inline
	209	unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
	210	{
254298c7 YZ	211	return box->pmu->type->event_ctl +
254298c7 YZ	212	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	213	uncore_msr_box_offset(box);
087bfbb0 YZ	214	}
	215
	216	static inline
	217	unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
	218	{
254298c7 YZ	219	return box->pmu->type->perf_ctr +
254298c7 YZ	220	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	221	uncore_msr_box_offset(box);
087bfbb0 YZ	222	}
087bfbb0 YZ	223
14371cce YZ	224	static inline
	225	unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
	226	{
	227	if (box->pci_dev)
	228	return uncore_pci_fixed_ctl(box);
	229	else
	230	return uncore_msr_fixed_ctl(box);
	231	}
	232
	233	static inline
	234	unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
	235	{
	236	if (box->pci_dev)
	237	return uncore_pci_fixed_ctr(box);
	238	else
	239	return uncore_msr_fixed_ctr(box);
	240	}
	241
	242	static inline
	243	unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
	244	{
	245	if (box->pci_dev)
	246	return uncore_pci_event_ctl(box, idx);
	247	else
	248	return uncore_msr_event_ctl(box, idx);
	249	}
	250
	251	static inline
	252	unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
	253	{
	254	if (box->pci_dev)
	255	return uncore_pci_perf_ctr(box, idx);
	256	else
	257	return uncore_msr_perf_ctr(box, idx);
	258	}
	259
087bfbb0 YZ	260	static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
	261	{
	262	return box->pmu->type->perf_ctr_bits;
	263	}
	264
	265	static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
	266	{
	267	return box->pmu->type->fixed_ctr_bits;
	268	}
	269
	270	static inline int uncore_num_counters(struct intel_uncore_box *box)
	271	{
	272	return box->pmu->type->num_counters;
	273	}
	274
	275	static inline void uncore_disable_box(struct intel_uncore_box *box)
	276	{
	277	if (box->pmu->type->ops->disable_box)
	278	box->pmu->type->ops->disable_box(box);
	279	}
	280
	281	static inline void uncore_enable_box(struct intel_uncore_box *box)
	282	{
	283	if (box->pmu->type->ops->enable_box)
	284	box->pmu->type->ops->enable_box(box);
	285	}
	286
	287	static inline void uncore_disable_event(struct intel_uncore_box *box,
	288	struct perf_event *event)
	289	{
	290	box->pmu->type->ops->disable_event(box, event);
	291	}
	292
	293	static inline void uncore_enable_event(struct intel_uncore_box *box,
	294	struct perf_event *event)
	295	{
	296	box->pmu->type->ops->enable_event(box, event);
	297	}
	298
	299	static inline u64 uncore_read_counter(struct intel_uncore_box *box,
	300	struct perf_event *event)
	301	{
	302	return box->pmu->type->ops->read_counter(box, event);
	303	}
	304
15c12479 IM	305	static inline void uncore_box_init(struct intel_uncore_box *box)
	306	{
	307	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	308	if (box->pmu->type->ops->init_box)
	309	box->pmu->type->ops->init_box(box);
	310	}
	311	}
	312
a46195f1 TG	313	static inline void uncore_box_exit(struct intel_uncore_box *box)
	314	{
	315	if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	316	if (box->pmu->type->ops->exit_box)
	317	box->pmu->type->ops->exit_box(box);
	318	}
	319	}
	320
254298c7 YZ	321	static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
254298c7 YZ	322	{
cf6d445f	323	return (box->pkgid < 0);
254298c7	324	}
514b2346	325
1f2569fa TG	326	static inline struct intel_uncore_pmu uncore_event_to_pmu(struct perf_event event)
	327	{
	328	return container_of(event->pmu, struct intel_uncore_pmu, pmu);
	329	}
	330
	331	static inline struct intel_uncore_box uncore_event_to_box(struct perf_event event)
	332	{
	333	return event->pmu_private;
	334	}
	335
514b2346	336	struct intel_uncore_box uncore_pmu_to_box(struct intel_uncore_pmu pmu, int cpu);
514b2346 YZ	337	u64 uncore_msr_read_counter(struct intel_uncore_box box, struct perf_event event);
	338	void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
	339	void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
	340	void uncore_pmu_event_read(struct perf_event *event);
	341	void uncore_perf_event_update(struct intel_uncore_box box, struct perf_event event);
	342	struct event_constraint *
	343	uncore_get_constraint(struct intel_uncore_box box, struct perf_event event);
	344	void uncore_put_constraint(struct intel_uncore_box box, struct perf_event event);
	345	u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
	346
	347	extern struct intel_uncore_type **uncore_msr_uncores;
	348	extern struct intel_uncore_type **uncore_pci_uncores;
	349	extern struct pci_driver *uncore_pci_driver;
712df65c TI	350	extern raw_spinlock_t pci2phy_map_lock;
712df65c TI	351	extern struct list_head pci2phy_map_head;
cf6d445f	352	extern struct pci_extra_dev *uncore_extra_pci_dev;
514b2346	353	extern struct event_constraint uncore_constraint_empty;
92807ffd YZ	354
	355	/* perf_event_intel_uncore_snb.c */
	356	int snb_uncore_pci_init(void);
	357	int ivb_uncore_pci_init(void);
	358	int hsw_uncore_pci_init(void);
a41f3c8c	359	int bdw_uncore_pci_init(void);
0e1eb0a1	360	int skl_uncore_pci_init(void);
92807ffd YZ	361	void snb_uncore_cpu_init(void);
92807ffd YZ	362	void nhm_uncore_cpu_init(void);
77af0037	363	int snb_pci2phy_map_init(int devid);
8268fdfc YZ	364
	365	/* perf_event_intel_uncore_snbep.c */
	366	int snbep_uncore_pci_init(void);
	367	void snbep_uncore_cpu_init(void);
ddcd0973 PZ	368	int ivbep_uncore_pci_init(void);
ddcd0973 PZ	369	void ivbep_uncore_cpu_init(void);
e735b9db YZ	370	int hswep_uncore_pci_init(void);
e735b9db YZ	371	void hswep_uncore_cpu_init(void);
070e9887 KL	372	int bdx_uncore_pci_init(void);
070e9887 KL	373	void bdx_uncore_cpu_init(void);
77af0037 HC	374	int knl_uncore_pci_init(void);
77af0037 HC	375	void knl_uncore_cpu_init(void);
c1e46580 YZ	376
	377	/* perf_event_intel_uncore_nhmex.c */
	378	void nhmex_uncore_cpu_init(void);