Commit | Line | Data |
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1965aae3 PA |
1 | #ifndef _ASM_X86_ACPI_H |
2 | #define _ASM_X86_ACPI_H | |
c1c30634 | 3 | |
0b80fc72 TG |
4 | /* |
5 | * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org> | |
7 | * | |
8 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
25 | */ | |
26 | #include <acpi/pdc_intel.h> | |
c1c30634 | 27 | |
0b80fc72 | 28 | #include <asm/numa.h> |
bee7f9c8 | 29 | #include <asm/fixmap.h> |
c1c30634 | 30 | #include <asm/processor.h> |
bde6f5f5 | 31 | #include <asm/mmu.h> |
4c1cbafb | 32 | #include <asm/mpspec.h> |
319b6ffc | 33 | #include <asm/realmode.h> |
c1c30634 | 34 | |
0b80fc72 TG |
35 | #ifdef CONFIG_ACPI |
36 | extern int acpi_lapic; | |
37 | extern int acpi_ioapic; | |
38 | extern int acpi_noirq; | |
39 | extern int acpi_strict; | |
40 | extern int acpi_disabled; | |
0b80fc72 TG |
41 | extern int acpi_pci_disabled; |
42 | extern int acpi_skip_timer_override; | |
43 | extern int acpi_use_timer_override; | |
7f74f8f2 | 44 | extern int acpi_fix_pin2_polarity; |
9ad95879 | 45 | extern int acpi_disable_cmcff; |
0b80fc72 | 46 | |
6697c052 HH |
47 | extern u8 acpi_sci_flags; |
48 | extern int acpi_sci_override_gsi; | |
49 | void acpi_pic_sci_set_trigger(unsigned int, u16); | |
50 | ||
90f6881e JF |
51 | extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi, |
52 | int trigger, int polarity); | |
53 | ||
0b80fc72 TG |
54 | static inline void disable_acpi(void) |
55 | { | |
56 | acpi_disabled = 1; | |
0b80fc72 TG |
57 | acpi_pci_disabled = 1; |
58 | acpi_noirq = 1; | |
59 | } | |
60 | ||
0b80fc72 TG |
61 | extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq); |
62 | ||
63 | static inline void acpi_noirq_set(void) { acpi_noirq = 1; } | |
64 | static inline void acpi_disable_pci(void) | |
65 | { | |
66 | acpi_pci_disabled = 1; | |
67 | acpi_noirq_set(); | |
68 | } | |
0b80fc72 | 69 | |
f1a2003e | 70 | /* Low-level suspend routine. */ |
d6a77ead | 71 | extern int (*acpi_suspend_lowlevel)(void); |
0b80fc72 | 72 | |
319b6ffc PA |
73 | /* Physical address to resume after wakeup */ |
74 | #define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start)) | |
0b80fc72 | 75 | |
c1c30634 AS |
76 | /* |
77 | * Check if the CPU can handle C2 and deeper | |
78 | */ | |
79 | static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) | |
80 | { | |
81 | /* | |
82 | * Early models (<=5) of AMD Opterons are not supposed to go into | |
83 | * C2 state. | |
84 | * | |
85 | * Steppings 0x0A and later are good | |
86 | */ | |
87 | if (boot_cpu_data.x86 == 0x0F && | |
88 | boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
89 | boot_cpu_data.x86_model <= 0x05 && | |
90 | boot_cpu_data.x86_mask < 0x0A) | |
91 | return 1; | |
02c68a02 | 92 | else if (amd_e400_c1e_detected) |
a8d68290 | 93 | return 1; |
c1c30634 AS |
94 | else |
95 | return max_cstate; | |
96 | } | |
97 | ||
1d9cb470 AC |
98 | static inline bool arch_has_acpi_pdc(void) |
99 | { | |
100 | struct cpuinfo_x86 *c = &cpu_data(0); | |
101 | return (c->x86_vendor == X86_VENDOR_INTEL || | |
102 | c->x86_vendor == X86_VENDOR_CENTAUR); | |
103 | } | |
104 | ||
6c5807d7 AC |
105 | static inline void arch_acpi_set_pdc_bits(u32 *buf) |
106 | { | |
107 | struct cpuinfo_x86 *c = &cpu_data(0); | |
108 | ||
109 | buf[2] |= ACPI_PDC_C_CAPABILITY_SMP; | |
110 | ||
111 | if (cpu_has(c, X86_FEATURE_EST)) | |
112 | buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; | |
113 | ||
114 | if (cpu_has(c, X86_FEATURE_ACPI)) | |
115 | buf[2] |= ACPI_PDC_T_FFH; | |
116 | ||
117 | /* | |
118 | * If mwait/monitor is unsupported, C2/C3_FFH will be disabled | |
119 | */ | |
120 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
121 | buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); | |
122 | } | |
123 | ||
0b80fc72 TG |
124 | #else /* !CONFIG_ACPI */ |
125 | ||
126 | #define acpi_lapic 0 | |
127 | #define acpi_ioapic 0 | |
9ad95879 | 128 | #define acpi_disable_cmcff 0 |
0b80fc72 TG |
129 | static inline void acpi_noirq_set(void) { } |
130 | static inline void acpi_disable_pci(void) { } | |
131 | static inline void disable_acpi(void) { } | |
132 | ||
133 | #endif /* !CONFIG_ACPI */ | |
134 | ||
135 | #define ARCH_HAS_POWER_INIT 1 | |
136 | ||
0b80fc72 TG |
137 | #ifdef CONFIG_ACPI_NUMA |
138 | extern int acpi_numa; | |
a9aec56a | 139 | extern int x86_acpi_numa_init(void); |
4e76f4e6 | 140 | #endif /* CONFIG_ACPI_NUMA */ |
0b80fc72 | 141 | |
bde6f5f5 VP |
142 | #define acpi_unlazy_tlb(x) leave_mm(x) |
143 | ||
1965aae3 | 144 | #endif /* _ASM_X86_ACPI_H */ |